PIPE接口协议解析.pdf

发布时间：2022-06-09 发布人：admin 分类：说明书资料大小：1.44M 资料格式：pdf 举报版权申诉

niuchicao6-10376317-4744300845380433156.pdf-第1页.png

第1页 / 共90页

niuchicao6-10376317-4744300845380433156.pdf-第2页.png

第2页 / 共90页

niuchicao6-10376317-4744300845380433156.pdf-第3页.png

第3页 / 共90页

niuchicao6-10376317-4744300845380433156.pdf-第4页.png

第4页 / 共90页

niuchicao6-10376317-4744300845380433156.pdf-第5页.png

第5页 / 共90页

niuchicao6-10376317-4744300845380433156.pdf-第6页.png

第6页 / 共90页

niuchicao6-10376317-4744300845380433156.pdf-第7页.png

第7页 / 共90页

niuchicao6-10376317-4744300845380433156.pdf-第8页.png

第8页 / 共90页

1 Preface

1.1 Scope of this Revision

1.2 Revision History

2 Introduction

2.1 PCI Express PHY Layer

2.2 USB SuperSpeed PHY Layer

2.3 SATA PHY Layer

3 PHY/MAC Interface

4 PCI Express and USB PHY Functionality

4.1 Transmitter Block Diagram (2.5 and 5.0 GT/s)

4.2 Transmitter Block Diagram (8.0/10 GT/s)

4.3 Receiver Block Diagram (2.5 and 5.0 GT/s)

4.4 Receiver Block Diagram (8.0/10.0 GT/s)

4.5 Clocking

5 SATA PHY Functionality

5.1 Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s)

5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s)

5.3 Clocking

6 PIPE Interface Signal Descriptions

6.1 PHY/MAC Interface Signals

6.2 External Signals

7 PIPE Operational Behavior

7.1 Clocking

7.2 Reset

7.3 Power Management – PCI Express Mode

7.4 Power Management – USB SuperSpeed Mode

7.5 Power Management – SATA Mode

7.6 Changing Signaling Rate, PCLK Rate, or Data Bus Width

7.6.1 PCI Express Mode

7.6.2 USB Mode

7.6.3 SATA Mode

7.6.4 Fixed data path implementations

7.6.5 Fixed PCLK implementations

7.7 Transmitter Margining – PCI Express Mode and USB SuperSpeed Mode

7.8 Selectable De-emphasis – PCI Express Mode

7.9 Receiver Detection – PCI Express Mode and USB SuperSpeed Mode

7.10 Transmitting a beacon – PCI Express Mode

7.11 Transmitting LFPS – USB SuperSpeed Mode

7.12 Detecting a beacon – PCI Express Mode

7.13 Detecting Low Frequency Periodic Signaling – USB SuperSpeed Mode

7.14 Clock Tolerance Compensation

7.15 Error Detection

7.15.1 8B/10B Decode Errors

7.15.2 Disparity Errors

7.15.3 Elastic Buffer Errors

7.16 Loopback

7.17 Polarity Inversion – PCI Express and USB SuperSpeed Modes

7.18 Setting negative disparity (PCI Express Mode)

7.19 Electrical Idle – PCI Express Mode

7.20 Link Equalization Evaluation

7.21 Implementation specific timing and selectable parameter support

7.22 Control Signal Decode table – PCI Express Mode

7.23 Control Signal Decode table – USB SuperSpeed Mode

7.24 Control Signal Decode table – SATA Mode

7.25 Required synchronous signal timings

7.26 128b/130b Encoding and Block Synchronization (PCI Express 8 GT/s)

7.27 128b/132b Encoding and Block Synchronization (USB 10 GT/s)

8 Sample Operational Sequences

8.1 Active PM L0 to L0s and back to L0 – PCI Express Mode

8.2 Active PM to L1 and back to L0 - – PCI Express Mode

8.3 Receivers and Electrical Idle – PCI Express Mode Example

8.4 Using CLKREQ# with PIPE – PCI Express Mode

9 Multi-lane PIPE – PCI Express Mode

PHY Interface for the PCI Express, SATA, and USB 3.10 Architectures Intellectual Property Disclaimer THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. A COPYRIGHT LICENSE IS HEREBY GRANTED TO REPRODUCE AND DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THIS DOCUMENT AND THE SPECIFICATION. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION ALSO DO NOT WARRANT OR REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH RIGHTS. ALL SUGGESTIONS OR FEEDBACK RELATED TO THIS SPECIFICATION BECOME THE PROPERTY OF INTEL CORPORATION UPON SUBMISSION. INTEL CORPORATION MAY MAKE CHANGES TO SPECIFICATIONS, PRODUCT DESCRIPTIONS, AND PLANS AT ANY TIME, WITHOUT NOTICE. Notice: Implementations developed using the information provided in this specification may infringe the patent rights of various parties including the parties involved in the development of this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights (including without limitation rights under any party’s patents) are granted herein. All product names are trademarks, registered trademarks, or service marks of their respective owners Contributors Jeff Morris Andy Martwick Brad Hosler Matthew Myers Bob Dunstan Saleem Mohammad Sue Vining Tadashi Iwasaki Yoichi Iizuka Rahman Ismail Ben Graniello Jim Choate Paul Mattos Dan Froelich Duane Quiet Hajime Nozaki Peter Teng Karthi Vadivelu Mineru Nishizawa Takanori Saeki Andrew Lillie Frank Kavanagh ©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 2 of 90

PHY Interface for the PCI Express, SATA, and USB 3.10 Architectures Dedicated to the memory of Brad Hosler, the impact of whose accomplishments made the Universal Serial Bus one of the most successful technology innovations of the Personal Computer era. ©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 3 of 90

PHY Interface for the PCI Express, SATA, and USB 3.10 Architectures Table of Contents 2 6.1 6.2 1 Preface ...................................................................................................................................... 7 1.1 Scope of this Revision ...................................................................................................... 7 1.2 Revision History ............................................................................................................... 7 Introduction .............................................................................................................................. 9 2.1 PCI Express PHY Layer ................................................................................................. 11 2.2 USB PHY Layer ............................................................................................................. 11 2.3 SATA PHY Layer ........................................................................................................... 12 3 PHY/MAC Interface .............................................................................................................. 12 4 PCI Express and USB PHY Functionality ............................................................................. 16 Transmitter Block Diagram (2.5 and 5.0 GT/s) .............................................................. 17 4.1 4.2 Transmitter Block Diagram (8.0/10 GT/s) ...................................................................... 17 4.3 Receiver Block Diagram (2.5 and 5.0 GT/s) .................................................................. 18 4.4 Receiver Block Diagram (8.0/10.0 GT/s) ....................................................................... 19 4.5 Clocking .......................................................................................................................... 20 5 SATA PHY Functionality ...................................................................................................... 20 5.1 Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ..................................................... 21 5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ........................................................... 22 5.3 Clocking .......................................................................................................................... 22 6 PIPE Interface Signal Descriptions ........................................................................................ 23 PHY/MAC Interface Signals .......................................................................................... 23 External Signals .............................................................................................................. 49 7 PIPE Operational Behavior .................................................................................................... 51 7.1 Clocking .......................................................................................................................... 51 7.2 Reset ................................................................................................................................ 51 Power Management – PCI Express Mode ...................................................................... 52 7.3 Power Management – USB Mode .................................................................................. 54 7.4 7.5 Power Management – SATA Mode ................................................................................ 55 7.6 Changing Signaling Rate, PCLK Rate, or Data Bus Width ............................................ 56 7.6.1 PCI Express Mode ................................................................................................... 56 7.6.2 USB Mode ............................................................................................................... 56 7.6.3 SATA Mode ............................................................................................................ 57 Fixed data path implementations ............................................................................. 58 7.6.4 7.6.5 Fixed PCLK implementations ................................................................................. 58 Transmitter Margining – PCI Express Mode and USB Mode ........................................ 59 7.7 Selectable De-emphasis – PCI Express Mode ................................................................ 59 7.8 7.9 Receiver Detection – PCI Express Mode and USB Mode .............................................. 60 Transmitting a beacon – PCI Express Mode ............................................................... 61 7.10 Transmitting LFPS – USB Mode ................................................................................ 61 7.11 7.12 Detecting a beacon – PCI Express Mode .................................................................... 62 Detecting Low Frequency Periodic Signaling – USB Mode ....................................... 62 7.13 Clock Tolerance Compensation .................................................................................. 62 7.14 Error Detection ............................................................................................................ 64 7.15 7.15.1 8B/10B Decode Errors ............................................................................................. 65 7.15.2 Disparity Errors ....................................................................................................... 65 7.15.3 Elastic Buffer Errors ................................................................................................ 66 Loopback ..................................................................................................................... 67 Polarity Inversion – PCI Express and USBModes ...................................................... 69 Setting negative disparity (PCI Express Mode) .......................................................... 69 Electrical Idle – PCI Express Mode ............................................................................ 70 7.16 7.17 7.18 7.19 ©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 4 of 90

PHY Interface for the PCI Express, SATA, and USB 3.10 Architectures 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 Link Equalization Evaluation ...................................................................................... 71 Implementation specific timing and selectable parameter support ............................. 72 Control Signal Decode table – PCI Express Mode ..................................................... 77 Control Signal Decode table – USB Mode ................................................................. 79 Control Signal Decode table – SATA Mode ............................................................... 79 Required synchronous signal timings .......................................................................... 80 128b/130b Encoding and Block Synchronization (PCI Express 8 GT/s) .................... 80 128b/132b Encoding and Block Synchronization (USB 10 GT/s) .............................. 82 8 Sample Operational Sequences .............................................................................................. 82 8.1 Active PM L0 to L0s and back to L0 – PCI Express Mode ............................................ 82 8.2 Active PM to L1 and back to L0 - – PCI Express Mode ................................................ 83 8.3 Receivers and Electrical Idle – PCI Express Mode Example ......................................... 84 8.4 Using CLKREQ# with PIPE – PCI Express Mode ......................................................... 86 9 Multi-lane PIPE – PCI Express Mode .................................................................................... 87 ©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 5 of 90

PHY Interface for the PCI Express, SATA, and USB 3.10 Architectures Table of Figures Figure 2-1: Partitioning PHY Layer for PCI Express .................................................................... 10 Figure 2-2 Partitioning PHY Layer for USB ................................................................................. 10 Figure 3-1: PHY/MAC Interface ............................................................................................... 12 Figure 4-1: PHY Functional Block Diagram ................................................................................. 16 Figure 4-2: Transmitter Block Diagram ................................................................................... 17 Figure 4-3: Transmitter Block Diagram (8.0/10 GT/s) ............................................................ 17 Figure 4-4: Receiver Block Diagram ......................................................................................... 18 Figure 4-5: Receiver Block Diagram (8.0 GT/s) ....................................................................... 19 Figure 4-6: Clocking and Power Block Diagram ...................................................................... 20 Figure 5-1: PHY Functional Block Diagram ................................................................................. 20 Figure 5-2: Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ............................................ 21 Figure 5-3: Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ................................................... 22 Figure 5-4: Clocking and Power Block Diagram .......................................................................... 22 Figure 6-1 – PCI Express 3.0 Example Timings For BlockAlignControl ..................................... 48 Figure 7-1 PCI Express P2 Entry and Exit with PCLK as PHY Output ....................................... 53 Figure 7-2PCI Express P2 Entry and Exit with PCLK as PHY Input ........................................... 54 Figure 7-3 Change from PCI Express 2.5 Gt/s to 5.0 Gt/s with PCLK as PHY Input. ................. 58 Figure 7-5 – PCI Express 3.0 Successful Equalization Evaluation Request ................................. 71 Figure 7-6 – PCI Express 3.0 Equalization Evaluation Request Resulting in Invalid Feedback .. 72 Figure 7-7 – PCI Express 3.0 TxDataValid Timing for 8 Bit Wide TxData Interface .................. 81 Figure 7-8 – PCI Express 3.0 TxDataValid Timing for 16 Bit Wide TxData Interface ................ 81 Figure 7-9 – PCI Express 3.0 RxDataValid Timing for 16 Bit Wide RxData Interface ............... 81 Table of Tables Table 3-2. PCI Express Mode - Possible PCLK rates and data widths ........................................ 15 3-3. USB Mode – Possible PCLK rates and data widths .............................................................. 15 Table 6-1: Transmit Data Interface Signals ................................................................................... 23 Table 6-2: Receive Data Interface Signals .................................................................................... 24 Table 6-3: Command Interface Signals ......................................................................................... 26 Table 6-4: Status Interface Signals ................................................................................................ 44 Table 6-5: External Signals ........................................................................................................... 49 ©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 6 of 90

PHY Interface for the PCI Express, SATA, and USB 3.10 Architectures 1 Preface 1.1 Scope of this Revision The PCI Express, SATA and USB SuperSpeed PHY Interface Specification has definitions of all functional blocks and signals. This revision includes support for PCI Express implementations conforming to the PCI Express Base Specification, Revision 3.0, SATA implementations conforming to the SATA specification, revision 3.0, and USB implementations conforming to the Universal Serial Bus Specification, Revision 3.0. 1.2 Revision History Date Description 7/31/02 8/16/02 10/4/02 11/4/02 11/22/02 12/16/02 4/25/03 6/19/03 11/6/05 12/4/2005 2/27/2006 9/28/2006 3/24/2007 7/21/2007 12/31/200 7 1/21/2008 2/8/08 8/11/08 3/11/09 4/5/11 4/13/11 9/1/11 12/7/11 12/12/11 5/21/12 7/1/13 Initial Draft Draft for industry review Provides operational detail Includes timing diagrams More operational detail. Receiver detection sequence changed. Minor updates. Solid enough for implementations to be finalized. Updates to reflect 1.0a Base Spec. Added multilane suggestions. Stable revision for implementation. First pass at Gen. 2 PIPE Fixed up areas based on feedback. Fixed up more areas based on feedback. Added a section on how to handle CLKREQ#. Removed references to Compliance Rate determination. Added sections for TX Margining and Selectable De-emphasis. Fixed up areas (6.4) based on feedback. Minor updates, mostly editorial. Minor updates, stable revision for implementation. Initial draft of updates to support the USB specification, revision 3.0. Updates for SKP handling and USB SuperSpeed PHY power management. Additional updates for SKP handling. Added 32 bit data interface support for USB SuperSpeed mode, support for USB SuperSpeed mode receiver equalization training, and support for USB SuperSpeed mode compliance patterns that are not 8b/10b encoded. Solid enough for implementation architectures to be finalized. Final update Draft 1 update adding SATA. Draft 3 update adding PCI Express 3.0 rev .9. Draft 6 update adding updates based on PCI Express 3.0 rev .9 feedback. Initial draft with per lane clocking option Draft 2. Updates for initial review feedback and addition of several example timing diagrams for PCI Express 3.0 related signals. Updated for Draft 2 feedback from various reviewers. Added support for USB 3.1 – preliminary review release based on USB 3.1 specification revision .9 Revision Number 0.1 0.5 0.6 0.7 0.8 0.9 0.95 1.00 1.70 1.81 1.86 1.87 1.90 2.00 2.7 2.71 2.75 2.90 3.0 4.0 4.0 4.0 4.1 4.1 4.1 4.2 ©2007 - 2013, 2008, 2009 Intel Corporation—All rights reserved. Page 7 of 90

分享到：

赞收藏

资料库

PIPE接口协议解析.pdf

相关推荐

课程资源

热门标签

最新资料