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PCI Express Architecture PHY Test Specification.pdf
PCI Express® Architecture
PHY Test Specification
Revision 4.0
February 13, 2016
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 4.0
Revision
Revision History
DATE
PCI-SIG® disclaims all warranties and liability for the use of this document and the information
contained herein and assumes no responsibility for any errors that may appear in this document, nor
does PCI-SIG make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding this specification or membership in PCI-SIG may be forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-619-0569
Fax:
503-644-6708
Technical Support
techsupp@pcisig.com
DISCLAIMER
This specification is provided “as is” with no warranties whatsoever, including any
warranty of merchantability, noninfringement, fitness for any particular purpose, or any
warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG
disclaims all liability for infringement of proprietary rights, relating to use of information
in this specification. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted herein.
PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or service marks of their respective
owners.
Copyright © 2014-2017 PCI-SIG
2
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 4.0
Contents
1. INTRODUCTION....................................................................................................................5
1.1. COVERAGE ................................................................................................................................ 5
2.2.1.
2.2.2.
2.6.1.
2.6.2.
2.7.1.
2.7.2.
2.8.1.
2.8.2.
2.9.1.
2.9.2.
2.3.1.
2.3.2.
2.4.1.
2.4.2.
2.1.1.
2.1.2.
2.1.3.
2.5.1.
2.5.2.
2.5.3.
2. TEST DESCRIPTIONS ..........................................................................................................6
2.1. ADD-IN CARD TRANSMITTER SIGNAL QUALITY ............................................................. 6
Add-in Card Transmitter Electrical Compliance Test for 2.5 GT/s and 5.0 GT/s ....... 6
Add-in Card Transmitter Electrical Compliance Test for 8.0 GT/s ............................. 6
Add-in Card Transmitter Electrical Compliance Test for 16.0 GT/s ........................... 6
2.2. ADD-IN CARD TRANSMITTER PRESET TEST ..................................................................... 6
Add-in Card Transmitter Preset Test for 8.0 GT/s ....................................................... 6
Add-in Card Transmitter Preset Test for 16.0 GT/s ..................................................... 6
2.3. ADD-IN CARD TRANSMITTER INITIAL TX EQ TEST ........................................................ 7
Add-in Card Transmitter Initial TX EQ test for 8.0 GT/s ............................................ 7
Add-in Card Transmitter Initial TX EQ test for 16.0 GT/s .......................................... 7
2.4. ADD-IN CARD TRANSMITTER LINK EQUALIZATION RESPONSE TEST ...................... 7
Add-in Card Transmitter Link Equalization Response Test for 8.0 GT/s .................... 7
Add-in Card Transmitter Link Equalization Response Test for 16.0 GT/s .................. 7
2.5. SYSTEM BOARD TRANSMITTER SIGNAL QUALITY ........................................................ 7
System Board Transmitter Electrical Compliance Test for 2.5 GT/s and 5.0 GT/s ..... 8
System Board Transmitter Electrical Compliance Test for 8.0 GT/s ........................... 8
System Board Transmitter Electrical Compliance Test for 16.0 GT/s ......................... 8
2.6. SYSTEM BOARD TRANSMITTER PRESET TEST................................................................. 8
System Board Transmitter Preset Test for 8.0 GT/s ..................................................... 8
System Board Transmitter Preset Test for 16.0 GT/s ................................................... 8
2.7. SYSTEM BOARD TRANSMITTER LINK EQUALIZATION RESPONSE TEST .................. 8
System Board Transmitter Link Equalization Response Test for 8.0 GT/s .................. 9
System Board Transmitter Link Equalization Response Test for 16.0 GT/s ................ 9
2.8. ADD-IN CARD RECEIVER JITTER TOLERANCE TEST ...................................................... 9
Add-in Card Receiver Jitter Tolerance Test at 8.0 GT/s .............................................. 9
Add-in Card Receiver Jitter Tolerance Test at 16.0 GT/s ............................................ 9
2.9. SYSTEM RECEIVER JITTER TOLERANCE TEST ................................................................. 9
System Receiver Jitter Tolerance Test for 8.0 GT/s ..................................................... 9
System Receiver Jitter Tolerance Test for 16.0 GT/s ................................................... 9
2.10. ADD-IN CARD RECEIVER LINK EQUALIZATION TEST .................................................... 9
System Receiver Jitter Tolerance Test for 8.0 GT/s ................................................... 10
System Receiver Jitter Tolerance Test for 16.0 GT/s ................................................. 10
2.11. ADD-IN CARD RECEIVER LINK EQUALIZATION TEST .................................................. 10
System Receiver Link Equalization Test for 8.0 GT/s ................................................ 10
System Receiver Link Equalization Test for 16.0 GT/s .............................................. 10
2.12. ADD-IN CARD PLL BANDWIDTH ........................................................................................ 10
2.13. ADD-IN CARD PCB IMPEDANCE (INFORMATIVE) .......................................................... 10
2.14. SYSTEM BOARD PCB IMPEDANCE (INFORMATIVE) ..................................................... 10
2.10.1.
2.10.2.
2.11.1.
2.11.2.
3. APPENDIX A: GETTING INTO LOOPBACK .................................................................11
3.1. LOOPBACK TRAINING .......................................................................................................... 11
3.2. STEP BY STEP SEQUENCE .................................................................................................... 12
3.3. LOOPBACK TRAINING AT 2.5 GT/S .................................................................................... 12
3
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 4.0
3.4. LOOPBACK TRAINING AT 5.0 GT/S .................................................................................... 13
3.5. LOOPBACK TRAINING AT 8.0 GT/S .................................................................................... 15
4.1.2.
4.1.3.
4. APPENDIX B: TRANSMITTER SIGNALING ANALYSIS ............................................16
4.1. OUTLINE OF TX SIGNAL ANALYSIS .................................................................................. 16
Input Waveform Conditioning .................................................................................... 16
Channel Embedding ................................................................................ 16
4.1.1.1
CTLE Equalization ................................................................................. 17
4.1.1.2
4.1.1.3
DFE Equalization ................................................................................... 17
Crossover and Interval Determination ....................................................................... 17
Time Interval Error (or Phase Jitter) Determination ................................................. 17
Single Port (Add-In Card) Jitter Determination ..................................... 18
4.1.3.1
4.1.3.2
Least Suqares Fit Clock Interval Method ............................................... 18
Mean Clock Interval Method .................................................................. 18
4.1.3.3
Single Port Data Waveform Phase Jitter Computation .......................... 18
4.1.3.4
Dual Port (System Board) Jitter Determination ..................................... 18
4.1.3.5
4.1.3.6
Phase-Locked Loop (PLL) Filter of Clock Jitter .................................... 18
Clock to Data Skew ................................................................................. 18
4.1.3.7
4.1.3.8
Dual Port Data Waveform Phase Jitter Computation ............................ 19
Jitter Determination ................................................................................................... 19
4.1.4.1
Phase Jitter High Pass Filter .................................................................. 19
Jitter Metrics ........................................................................................... 19
4.1.4.2
4.1.4.3
Dual Dirac Fitting .................................................................................. 19
4.1.1.
4.1.4.
4
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 4.0
1
1.Introduction
This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone
building add-in cards or system boards to the PCI Express Card Electromechanical Specification
4.0. This specification does not describe the full set of PCI Express tests and assertions for these
devices.
In particular, devices must also meet the requirements and tests described in the latest versions of
the following documents as well as any other tests provided by the PCI-SIG:
PCI Express Architecture Configuration Space Test Specification
Platform BIOS Test Considerations for the PCI Express Architecture
PCI Express Architecture Link Layer Test Specification
PCI Express Architecture Transaction Layer Test Specification
1.1.
Coverage
This document covers items in the PCI Express Card Electromechanical Revision 4.0 or Base
Specification Revision 4.0 that apply to 16 GT/s, 8.0 GT/s, 5.0 GT/s and 2.5 GT/s signaling. 5.0
GT/s signaling requirements described in the PHY Electrical Test Consideration Revision 2.0
document apply to PCIe 2.0 devices that support 5.0GT/s and 2.5 GT/s signaling. 2.5 GT/s
signaling requirements described in the PHY Electrical Test Considerations Revision 1.1 document
apply to PCIe2.0, PCIe 1.1 and PCIe 1.0a devices that support 2.5 GT/s signaling.
5
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 4.0
2
2.
Test Descriptions
2.1. Add-in Card Transmitter Signal Quality
This test is run on all card electromechanical (CEM) form factor add-in cards. The test verifies that
the signaling of the system at 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s with all specified
transmitter equalization values meets eye diagram and other jitter requirements.
Starting Configuration
Overview of Test Steps
2.1.1. Add-in Card Transmitter Electrical Compliance Test
for 2.5 GT/s and 5.0 GT/s
2.1.2. Add-in Card Transmitter Electrical Compliance Test
for 8.0 GT/s
2.1.3. Add-in Card Transmitter Electrical Compliance Test
for 16.0 GT/s
2.2. Add-in Card Transmitter Preset Test
This test is run on all card electromechanical form factor add-in cards that operate at 8.0 GT/s and
16.0 GT/s. The test verifies that the add-in card produces the correct transmitter equalization
values for each preset in the set of 11 presets.
Starting Configuration
Overview of Test Steps
2.2.1. Add-in Card Transmitter Preset Test for 8.0 GT/s
2.2.2. Add-in Card Transmitter Preset Test for 16.0 GT/s
6
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 4.0
2.3. Add-in Card Transmitter Initial TX EQ Test
This test is run on all card electromechanical form factor add-in cards that operate at 8.0 GT/s and
16.0 GT/s. The test verifies that the add-in card will start with the corrext TX EQ preset requested
through the protocol.
Starting Configuration
Overview of Test Steps
2.3.1. Add-in Card Transmitter Initial TX EQ test for 8.0 GT/s
2.3.2. Add-in Card Transmitter Initial TX EQ test for 16.0
GT/s
2.4. Add-in Card Transmitter Link Equalization
Response Test
This test is run on all card electromechanical form factor add-in cards that operate at 8.0 GT/s and
16.0 GT/s. The test verifies that the add-in card will respond correctly to transmitter equalization
commands sent via the link protocol.
Starting Configuration
Overview of Test Steps
2.4.1. Add-in Card Transmitter Link Equalization Response
Test for 8.0 GT/s
2.4.2. Add-in Card Transmitter Link Equalization Response
Test for 16.0 GT/s
2.5. System Board Transmitter Signal Quality
This test is run on all card electromechanical form factor system boards. The test verifies that the
signaling of the system at 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s with all specified
transmitter equalization values meets eye diagram and other jitter requirements.
Starting Configuration
Overview of Test Steps
7
PCI EXPRESS ARCHITECTURE PHY TEST SPECIFICATION, REV. 4.0
2.5.1. System Board Transmitter Electrical Compliance Test
for 2.5 GT/s and 5.0 GT/s
2.5.2. System Board Transmitter Electrical Compliance Test
for 8.0 GT/s
2.5.3. System Board Transmitter Electrical Compliance Test
for 16.0 GT/s
2.6. System Board Transmitter Preset Test
This test is run on all card electromechanical form factor system boards that operate at 8.0 GT/s
and 16.0 GT/s. The test verifies that the system board produces the correct transmitter equalization
values for each preset in the set of 11 presets.
Starting Configuration
Overview of Test Steps
2.6.1. System Board Transmitter Preset Test for 8.0 GT/s
2.6.2. System Board Transmitter Preset Test for 16.0 GT/s
2.7. System Board Transmitter Link Equalization
Response Test
This test is run on all card electromechanical form factor system boards that operate at 8.0 GT/s
and 16.0 GT/s. The test verifies that the system will respond correctly to transmitter equalization
commands sent via the link protocol.
Starting Configuration
Overview of Test Steps
8
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