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88E1518-datasheet--1360912.pdf
Cover
Product Overview
Features
Table of Contents
List of Tables
List of Figures
1 Signal Description
1.1 Pin Description
1.1.1 88E1510/88E1518 48-Pin QFN Package Pinout
1.1.2 88E1512 56-Pin QFN Package Pinout
1.1.3 88E1514 56-Pin QFN Package Pinout
1.2 Pin Assignment List
1.2.1 88E1510 48-Pin QFN Pin Assignment List - Alphabetical by Signal Name
1.2.2 88E1518 48-Pin QFN Pin Assignment List - Alphabetical by Signal Name
1.2.3 88E1512 56-Pin QFN Pin Assignment List - Alphabetical by Signal Name
1.2.4 88E1514 56-Pin QFN Pin Assignment List - Alphabetical by Signal Name
2 PHY Functional Specifications
2.1 Modes of Operation and Major Interfaces
2.2 Copper Media Interface
2.2.1 Transmit Side Network Interface
2.2.1.1 Multi-mode TX Digital to Analog Converter
2.2.1.2 Slew Rate Control and Waveshaping
2.2.2 Encoder
2.2.2.1 1000BASE-T
2.2.2.2 100BASE-TX
2.2.2.3 10BASE-T
2.2.3 Receive Side Network Interface
2.2.3.1 Analog to Digital Converter
2.2.3.2 Active Hybrid
2.2.3.3 Echo Canceller
2.2.3.4 NEXT Canceller
2.2.3.5 Baseline Wander Canceller
2.2.3.6 Digital Adaptive Equalizer
2.2.3.7 Digital Phase Lock Loop
2.2.3.8 Link Monitor
2.2.3.9 Signal Detection
2.2.4 Decoder
2.2.4.1 1000BASE-T
2.2.4.2 100BASE-TX
2.2.4.3 10BASE-T
2.3 1.25 GHz SERDES Interface
2.3.1 Electrical Interface
2.4 MAC Interfaces
2.4.1 SGMII
2.4.1.1 SGMII Speed and Link
2.4.1.2 SGMII TRR Blocking
2.4.1.3 False SERDES Link Up Prevention
2.4.2 RGMII
2.4.3 10/100 Mbps Functionality
2.4.4 TX_ER and RX_ER Coding
2.5 Loopback
2.5.1 System Interface Loopback
2.5.2 Line Loopback
2.5.3 External Loopback
2.6 Resets
2.7 Power Management
2.7.1 Low Power Modes
2.7.1.1 IEEE Power Down Mode
2.7.1.2 Copper Energy Detect Modes
2.7.2 RGMII/SGMII MAC Interface Power Down
2.8 Auto-Negotiation
2.8.1 10/100/1000BASE-T Auto-Negotiation
2.8.2 1000BASE-X Auto-Negotiation
2.8.3 SGMII Auto-Negotiation
2.8.3.1 Serial Interface Auto-Negotiation Bypass Mode
2.9 CRC Error Counter and Frame Counter
2.9.1 Enabling the CRC Error Counter and Packet Counter
2.10 Packet Generator
2.11 1.25G PRBS Generator and Checker
2.12 MDI/MDIX Crossover
2.13 Polarity Correction
2.14 FLP Exchange Complete with No Link
2.15 Duplex Mismatch Indicator
2.16 LED
2.16.1 LED Polarity
2.16.2 Pulse Stretching and Blinking
2.16.3 Bi-Color LED Mixing
2.16.4 Modes of Operation
2.16.4.1 Compound LED Modes
2.16.4.2 Speed Blink
2.16.4.3 Manual Override
2.16.4.4 MODE 1, MODE 2, MODE 3, MODE 4
2.17 Interrupt
2.18 Configuring the 88E1510/88E1518/88E1512/88E1514 Device
2.18.1 Hardware Configuration
2.18.2 Software Configuration - Management Interface
2.18.2.1 Preamble Suppression
2.19 Jumbo Packet Support
2.20 Temperature Sensor
2.21 Regulators and Power Supplies
2.21.1 AVDD18
2.21.2 AVDDC18
2.21.3 AVDD33
2.21.4 DVDD
2.21.5 REG_IN
2.21.6 AVDD18_OUT
2.21.7 DVDD_OUT
2.21.8 VDDO
2.21.9 Power Supply Sequencing
3 88E1510/88E1518/88E1512/88E1514 Register Description
3.1 PHY MDIO Register Description
4 Electrical Specifications
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 Package Thermal Information
4.3.1 Thermal Conditions for 88E1510/88E1518 48-pin, QFN Package
4.3.2 Thermal Conditions for 88E1512/88E1514 56-pin, QFN Package
4.4 88E1510/88E1518 Current Consumption
4.4.1 Current Consumption when using External Regulators
4.4.2 Current Consumption when using Internal Regulators
4.5 88E1512 Current Consumption
4.5.1 Current Consumption when using External Regulators
4.5.2 Current Consumption when using Internal Regulators
4.6 88E1514 Current Consumption
4.6.1 Current Consumption when using External Regulators
4.6.2 Current Consumption when using Internal Regulators
4.7 DC Operating Conditions
4.7.1 Digital Pins
4.7.2 IEEE DC Transceiver Parameters
4.8 AC Electrical Specifications
4.8.1 Reset Timing
4.8.2 XTAL_IN/XTAL_OUT Timing
4.8.3 LED to CONFIG Timing
4.9 SGMII Timing
4.9.1 SGMII Output AC Characteristics
4.9.2 SGMII Input AC Characteristics
4.10 RGMII Timing
4.10.1 RGMII AC Characteristics
4.10.2 RGMII Delay Timing for Different RGMII Modes
4.10.2.1 PHY Input - TX_CLK Delay when Register 21_2.4 = 0
4.10.2.2 PHY Input - TX_CLK Delay when Register 21_2.4 = 1
4.10.2.3 PHY Output - RX_CLK Delay
4.10.2.4 PHY Output - RX_CLK Delay
4.11 MDC/MDIO Timing
4.12 IEEE AC Transceiver Parameters
4.13 Latency Timing
4.13.1 RGMII to 1000BASE-T Transmit Latency Timing
4.13.2 RGMII to 100BASE-TX Transmit Latency Timing
4.13.3 RGMII to 10BASE-T Transmit Latency Timing
4.13.4 1000BASE-T to RGMII Receive Latency Timing
4.13.5 100BASE-TX to RGMII Receive Latency Timing
4.13.6 10BASE-T to RGMII Receive Latency Timing
4.13.7 10/100/1000BASE-T to SGMII Latency Timing
4.13.8 SGMII to 10/100/1000BASE-T Latency Timing
5 Package Mechanical Dimensions
5.1 48-Pin QFN Package
5.2 56-Pin QFN Package
6 Part Order Numbering/Package Marking
6.1 Part Order Numbering
6.2 Package Marking
6.2.1 Commercial
6.2.2 Industrial
A Revision History
Contact Information
Cover
Alaska®
88E1510/88E1518/
88E1512/88E1514
Integrated 10/100/1000 Mbps
Energy Efficient Ethernet
Transceiver
Datasheet - Public
Doc. No. MV-S107146-U0, Rev. B
February 23, 2018
Marvell. Moving Forward Faster
Document Classification: Public
Alaska 88E1510/88E1518/88E1512/88E1514
Datasheet - Public
Document Conventions
Note: Provides related information or information of special importance.
Caution: Indicates potential damage to hardware or software, or loss of data.
Warning: Indicates a risk of personal injury.
For more information, visit our website at: http://www.marvell.com
Disclaimer
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose,
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particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.
Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use
Marvell products in these types of equipment or applications.
With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
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Copyright © 1999–2018. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, FLC, HyperDuo, Kirkwood, Link Street, LinkCrypt,
Marvell logo, Marvell, Marvell EZ-Connect, Marvell Smart, Marvell VSoC, MoChi, Moving Forward Faster, PISC, Prestera, Virtual Cable Tester, The World as YOU See It,
Xelerated, and Yukon are registered trademarks of Marvell or its affiliates. ArmadaBoard, Marvell COFFEEbin, Marvell ESPRESSObin, Marvell MACCHIATObin, and
NANDEdge are trademarks of Marvell or its affiliates.
Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
Doc. No. MV-S107146-U0 Rev. B
Page 2
Document Classification: Public
Copyright © 2018 Marvell
February 23, 2018
Alaska 88E1510/88E1518/88E1512/88E1514
Integrated 10/100/1000 Mbps Energy Efficient Ethernet
Transceiver
Datasheet - Public
PRODUCT OVERVIEW
The Alaska® 88E1510/88E1518/88E1512/88E1514
device is a physical layer device containing a single
10/100/1000 Gigabit Ethernet transceiver. The
transceiver implements the Ethernet physical layer
portion of the 1000BASE-T, 100BASE-TX, and
10BASE-T standards. It is manufactured using standard
digital CMOS process and contains all the active circuitry
required to implement the physical layer functions to
transmit and receive data on standard CAT 5 unshielded
twisted pair.
The device supports the RGMII (Reduced pin count
GMII) and SGMII for direct connection to a MAC/Switch
port. The SGMII can also be used on media/line side to
connect to SFP modules that support 1000BASE-X,
100BASE-FX and SGMII. It also supports Copper/Fiber
Auto-media applications with RGMII as the MAC
interface. SGMII operates at 1.25 Gbps over a single
differential pair thus reducing power and number of I/Os
used on the MAC interface.
The device integrates MDI termination resistors into the
PHY. This resistor integration simplifies board layout and
reduces board cost by reducing the number of external
components. The new Marvell® calibrated resistor
scheme will achieve and exceed the accuracy
requirements of the IEEE 802.3 return loss
specifications.
The device has an integrated switching voltage regulator
to generate all required voltages. The device can run off
a single 3.3V supply. The device supports 1.8V, 2.5V,
and 3.3V LVCMOS I/O Standards.
The 88E1510/88E1518/88E1512/88E1514 device
supports Synchronous Ethernet (SyncE) and Precise
Timing Protocol (PTP) Time Stamping, which is based on
IEEE1588 version 2 and IEEE802.1AS.
The 88E1510/88E1518/88E1512/88E1514 device
supports IEEE 802.3az-2010 Energy Efficient Ethernet
(EEE) and is IEEE 802.3az-2010 compliant.
The device incorporates the Marvell Advanced Virtual
Cable Tester® (VCT™) feature, which uses Time Domain
Reflectometry (TDR) technology for the remote
identification of potential cable malfunctions, thus
reducing equipment returns and service calls. Using
VCT, the Alaska device detects and reports potential
cabling issues such as pair swaps, pair polarity and
excessive pair skew. The device will also detect cable
opens, shorts or any impedance mismatch in the cable
and reporting accurately within one meter the distance to
the fault.
The device uses advanced mixed-signal processing to
perform equalization, echo and crosstalk cancellation,
data recovery, and error correction at a Gigabits per
second data rate. The device achieves robust
performance in noisy environments with very low power
dissipation.
Features
10/100/1000BASE-T IEEE 802.3 compliant
Multiple Operating Modes
• RGMII to Copper
• SGMII to Copper (88E1512/88E1514 device
only)
• RGMII to Fiber/SGMII (88E1512 device only)
• RGMII to Copper/Fiber/SGMII with Auto-Media
Detect (88E1512 device only)
• Copper to Fiber (1000BASE-X)
(88E1512/88E1514)
Four RGMII timing modes including integrated
delays - This eliminates the need for adding trace
delays on the PCB
Supports 1000BASE-X and 100BASE-FX on the
Fiber interface along with SGMII (88E1512 device
only)
Supports LVCMOS I/O Standards on the RGMII
Copyright © 2018 Marvell
February 23, 2018
Document Classification: Public
Doc. No. MV-S107146-U0 Rev. B
Page 3
Alaska 88E1510/88E1518/88E1512/88E1514
Datasheet - Public
Supports Energy Efficient Ethernet (EEE) - IEEE
802.3az-2010 compliant
• EEE Buffering
•
Incorporates EEE buffering for seamless support
of legacy MACs
Ultra Low Power
Integrated MDI termination resistors that eliminate
passive components
Integrated Switching Voltage Regulators
Supports Green Ethernet
• Active Power Save Mode
• Energy Detect and Energy Detect+ low power
modes
IEEE1588 version 2 Time Stamping
Synchronous Ethernet (SyncE) Clock Recovery
Three loopback modes for diagnostics
“Downshift” mode for two-pair cable installations
Fully integrated digital adaptive equalizers, echo
cancellers, and crosstalk cancellers
Advanced digital baseline wander correction
Automatic MDI/MDIX crossover at all speeds of
operation
Automatic polarity correction
IEEE 802.3 compliant Auto-Negotiation
Software programmable LED modes including LED
testing
Packet generation
MDC/XMDIO Management Interface
CRC checker, packet counter
Wake on LAN (WOL) event detection
Advanced Virtual Cable Tester® (VCT™)
Auto-Calibration for MAC Interface outputs
Temperature Sensor
Supports single 3.3V supply when using internal
switching regulator
I/O pads can be supplied with 1.8V, 2.5V, or 3.3V
Commercial grade, Industrial grade (88E1510 and
88E1512 only)
48-Pin QFN 7 mm x 7 mm Green package with
EPAD (88E1510 and 88E1518) and 56-Pin QFN 8
mm x 8 mm Green package with EPAD
(88E1512/88E1514 device)
88E1510/88E1518/88E1512/88E1514 Device Features
Table 1:
Features
RGMII to Copper
SGMII to Copper
RGMII to Fiber/SGMII
RGMII to Copper/Fiber/SGMII with Auto-Media Detect
Copper to Fiber
I/O Voltage (VDDO)
IEEE 802.3az-2010 Energy Efficient Ethernet (EEE)
EEE Buffering
Synchronous Ethernet (SyncE)
Precise Timing Protocol (PTP)
Auto-Media Detect
Wake on LAN (WOL)
Package
Industrial/Commercial Temperature
88E1510
88E1518
Yes
No
No
No
No
Yes
No
No
No
No
88E1512
Yes
Yes
Yes
Yes
Yes
88E1514
No
Yes
No
No
Yes
3.3V/2.5V
1.8V only
3.3V/2.5V/1.8V
3.3V/2.5V/1.8V
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
48-pin QFN
56-pin QFN
Commercial
Industrial
Commercial
Commercial
Industrial
Commercial
Doc. No. MV-S107146-U0 Rev. B
Page 4
Document Classification: Public
Copyright © 2018 Marvell
February 23, 2018
Figure 1: RGMII to Copper Device Application
10/100/1000 Mbps
Ethernet MAC
MAC Interface
- RGMII
Alaska®
88E1510/
88E1518/
88E1512
Device
Figure 2: SGMII to Copper Application
10/100/1000 Mbps
Ethernet MAC
MAC Interface –
SGMII/SERDES
Alaska®
88E1512/
88E1514
Device
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P
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Figure 3: RGMII to Fiber/SGMII Application
10/100/1000 Mbps
Ethernet MAC
MAC Interface
– RGMII
Alaska®
88E1512
Device
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Product Overview
Features
s
c
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t
e
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g
a
M
RJ-45
Media Type
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
s
c
i
t
e
n
g
a
M
RJ-45
Media Type
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
SERDES/
SGMII
Fiber
Optics
Media Type
- 1000BASE-X
- 100BASE-FX
- SFP
Figure 4: RGMII to Copper/Fiber/SGMII Auto-Media Application
10/100/1000 Mbps
Ethernet MAC
MAC Interface
– RGMII
Alaska®
88E1512
Device
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T
SERDES/SGMII
s
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Fiber
Optics
RJ-45
Media Type
- 1000BASE-X
- 100BASE-FX
- SFP
or
Media Type
- 1000BASE-T
- 100BASE-TX
- 10BASE-T
Copyright © 2018 Marvell
February 23, 2018
Document Classification: Public
Doc. No. MV-S107146-U0 Rev. B
Page 5
Alaska 88E1510/88E1518/88E1512/88E1514
Datasheet - Public
Table of Contents
1
1.1
1.2
2
2.1
2.2
2.3
2.4
2.5
Signal Description ..................................................................................................................... 17
Pin Description .............................................................................................................................................. 17
1.1.1
88E1510/88E1518 48-Pin QFN Package Pinout ............................................................................ 18
88E1512 56-Pin QFN Package Pinout ........................................................................................... 23
1.1.2
1.1.3
88E1514 56-Pin QFN Package Pinout ........................................................................................... 28
Pin Assignment List ....................................................................................................................................... 33
1.2.1
88E1510 48-Pin QFN Pin Assignment List - Alphabetical by Signal Name .................................... 33
88E1518 48-Pin QFN Pin Assignment List - Alphabetical by Signal Name .................................... 34
1.2.2
88E1512 56-Pin QFN Pin Assignment List - Alphabetical by Signal Name .................................... 35
1.2.3
1.2.4
88E1514 56-Pin QFN Pin Assignment List - Alphabetical by Signal Name .................................... 36
2.2.3
2.2.4
2.2.2
PHY Functional Specifications ................................................................................................. 37
Modes of Operation and Major Interfaces ..................................................................................................... 37
Copper Media Interface ................................................................................................................................. 39
2.2.1
Transmit Side Network Interface .................................................................................................... 39
Multi-mode TX Digital to Analog Converter ............................................................. 39
2.2.1.1
2.2.1.2
Slew Rate Control and Waveshaping ...................................................................... 40
Encoder .......................................................................................................................................... 40
1000BASE-T ............................................................................................................ 40
2.2.2.1
2.2.2.2
100BASE-TX ........................................................................................................... 40
2.2.2.3
10BASE-T ................................................................................................................ 40
Receive Side Network Interface ..................................................................................................... 40
Analog to Digital Converter ...................................................................................... 40
2.2.3.1
2.2.3.2
Active Hybrid ............................................................................................................ 40
Echo Canceller ........................................................................................................ 40
2.2.3.3
NEXT Canceller ....................................................................................................... 40
2.2.3.4
Baseline Wander Canceller ..................................................................................... 41
2.2.3.5
Digital Adaptive Equalizer ........................................................................................ 41
2.2.3.6
2.2.3.7
Digital Phase Lock Loop .......................................................................................... 41
Link Monitor ............................................................................................................. 41
2.2.3.8
2.2.3.9
Signal Detection ....................................................................................................... 41
Decoder .......................................................................................................................................... 41
1000BASE-T ............................................................................................................ 41
2.2.4.1
2.2.4.2
100BASE-TX ........................................................................................................... 42
10BASE-T ................................................................................................................ 42
2.2.4.3
1.25 GHz SERDES Interface ........................................................................................................................ 42
2.3.1
Electrical Interface .......................................................................................................................... 42
MAC Interfaces ............................................................................................................................................. 43
SGMII .............................................................................................................................................. 43
2.4.1
SGMII Speed and Link ............................................................................................. 43
2.4.1.1
2.4.1.2
SGMII TRR Blocking ................................................................................................ 43
2.4.1.3
False SERDES Link Up Prevention ......................................................................... 43
RGMII ............................................................................................................................................. 44
2.4.2
10/100 Mbps Functionality .............................................................................................................. 45
2.4.3
2.4.4
TX_ER and RX_ER Coding ............................................................................................................ 45
Loopback ....................................................................................................................................................... 45
System Interface Loopback ............................................................................................................ 45
2.5.1
Doc. No. MV-S107146-U0 Rev. B
Page 6
Document Classification: Public
Copyright © 2018 Marvell
February 23, 2018
Table of Contents
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
Line Loopback ................................................................................................................................ 47
2.5.2
2.5.3
External Loopback .......................................................................................................................... 48
Resets ........................................................................................................................................................... 49
Power Management ...................................................................................................................................... 49
Low Power Modes .......................................................................................................................... 49
2.7.1
IEEE Power Down Mode ......................................................................................... 50
2.7.1.1
2.7.1.2
Copper Energy Detect Modes ................................................................................. 50
RGMII/SGMII MAC Interface Power Down ..................................................................................... 51
2.7.2
Auto-Negotiation ........................................................................................................................................... 51
10/100/1000BASE-T Auto-Negotiation ........................................................................................... 52
2.8.1
1000BASE-X Auto-Negotiation ....................................................................................................... 53
2.8.2
SGMII Auto-Negotiation .................................................................................................................. 53
2.8.3
2.8.3.1
Serial Interface Auto-Negotiation Bypass Mode ...................................................... 54
CRC Error Counter and Frame Counter ....................................................................................................... 54
2.9.1
Enabling the CRC Error Counter and Packet Counter ................................................................... 54
Packet Generator .......................................................................................................................................... 54
1.25G PRBS Generator and Checker ........................................................................................................... 55
MDI/MDIX Crossover .................................................................................................................................... 56
Polarity Correction ......................................................................................................................................... 56
FLP Exchange Complete with No Link .......................................................................................................... 57
Duplex Mismatch Indicator ............................................................................................................................ 57
LED ............................................................................................................................................................... 58
2.16.1
LED Polarity .................................................................................................................................... 59
2.16.2 Pulse Stretching and Blinking ......................................................................................................... 59
2.16.3 Bi-Color LED Mixing ....................................................................................................................... 60
2.16.4 Modes of Operation ........................................................................................................................ 62
Compound LED Modes ........................................................................................... 63
Speed Blink .............................................................................................................. 63
Manual Override ...................................................................................................... 63
MODE 1, MODE 2, MODE 3, MODE 4 .................................................................... 64
Interrupt ......................................................................................................................................................... 64
Configuring the 88E1510/88E1518/88E1512/88E1514 Device .................................................................... 65
2.18.1 Hardware Configuration .................................................................................................................. 65
2.18.2 Software Configuration - Management Interface ............................................................................ 66
Preamble Suppression ............................................................................................ 67
Jumbo Packet Support .................................................................................................................................. 67
Temperature Sensor ..................................................................................................................................... 67
Regulators and Power Supplies .................................................................................................................... 68
2.21.1 AVDD18 .......................................................................................................................................... 68
2.21.2 AVDDC18 ....................................................................................................................................... 68
2.21.3 AVDD33 .......................................................................................................................................... 68
2.21.4 DVDD .............................................................................................................................................. 69
2.21.5 REG_IN .......................................................................................................................................... 69
2.21.6 AVDD18_OUT ................................................................................................................................ 69
2.21.7 DVDD_OUT .................................................................................................................................... 69
2.21.8 VDDO ............................................................................................................................................. 69
2.21.9 Power Supply Sequencing .............................................................................................................. 69
2.16.4.1
2.16.4.2
2.16.4.3
2.16.4.4
2.18.2.1
Copyright © 2018 Marvell
February 23, 2018
Document Classification: Public
Doc. No. MV-S107146-U0 Rev. B
Page 7
3
3.1
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
Alaska 88E1510/88E1518/88E1512/88E1514
Datasheet - Public
88E1510/88E1518/88E1512/88E1514 Register Description .................................................... 70
PHY MDIO Register Description ................................................................................................................... 70
Electrical Specifications ......................................................................................................... 118
Absolute Maximum Ratings ........................................................................................................................ 118
Recommended Operating Conditions ......................................................................................................... 119
Package Thermal Information ..................................................................................................................... 120
Thermal Conditions for 88E1510/88E1518 48-pin, QFN Package ............................................... 120
4.3.1
4.3.2
Thermal Conditions for 88E1512/88E1514 56-pin, QFN Package ............................................... 121
88E1510/88E1518 Current Consumption ................................................................................................... 122
4.4.1
Current Consumption when using External Regulators ................................................................ 122
4.4.2
Current Consumption when using Internal Regulators ................................................................. 123
88E1512 Current Consumption ................................................................................................................... 124
Current Consumption when using External Regulators ................................................................ 124
4.5.1
4.5.2
Current Consumption when using Internal Regulators ................................................................. 126
88E1514 Current Consumption ................................................................................................................... 127
Current Consumption when using External Regulators ................................................................ 127
4.6.1
4.6.2
Current Consumption when using Internal Regulators ................................................................. 128
DC Operating Conditions ............................................................................................................................ 129
4.7.1
Digital Pins .................................................................................................................................... 129
4.7.2
IEEE DC Transceiver Parameters ................................................................................................ 130
AC Electrical Specifications ........................................................................................................................ 131
Reset Timing ................................................................................................................................. 131
4.8.1
4.8.2
XTAL_IN/XTAL_OUT Timing ........................................................................................................ 132
4.8.3
LED to CONFIG Timing ................................................................................................................ 133
SGMII Timing .............................................................................................................................................. 134
4.9.1
SGMII Output AC Characteristics ................................................................................................. 134
4.9.2
SGMII Input AC Characteristics .................................................................................................... 134
RGMII Timing .............................................................................................................................................. 135
4.10.1 RGMII AC Characteristics ............................................................................................................. 135
4.10.2 RGMII Delay Timing for Different RGMII Modes ........................................................................... 136
PHY Input - TX_CLK Delay when Register 21_2.4 = 0 ......................................... 136
PHY Input - TX_CLK Delay when Register 21_2.4 = 1 ......................................... 136
PHY Output - RX_CLK Delay ................................................................................ 137
PHY Output - RX_CLK Delay ................................................................................ 137
MDC/MDIO Timing ...................................................................................................................................... 138
IEEE AC Transceiver Parameters ............................................................................................................... 139
Latency Timing ............................................................................................................................................ 140
4.13.1 RGMII to 1000BASE-T Transmit Latency Timing ......................................................................... 140
4.13.2 RGMII to 100BASE-TX Transmit Latency Timing ......................................................................... 140
4.13.3 RGMII to 10BASE-T Transmit Latency Timing ............................................................................. 140
1000BASE-T to RGMII Receive Latency Timing .......................................................................... 141
4.13.4
100BASE-TX to RGMII Receive Latency Timing .......................................................................... 141
4.13.5
4.13.6
10BASE-T to RGMII Receive Latency Timing .............................................................................. 141
4.13.7
10/100/1000BASE-T to SGMII Latency Timing ............................................................................ 141
4.13.8 SGMII to 10/100/1000BASE-T Latency Timing ............................................................................ 142
4.10.2.1
4.10.2.2
4.10.2.3
4.10.2.4
5
5.1
Package Mechanical Dimensions .......................................................................................... 143
48-Pin QFN Package .................................................................................................................................. 143
Doc. No. MV-S107146-U0 Rev. B
Page 8
Document Classification: Public
Copyright © 2018 Marvell
February 23, 2018
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