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Inside NAND Flash Memories.pdf

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    Cover
    Inside NAND Flash Memories
    ISBN 904819430X
    Preface
    Acknowledgements
    Table of contents
    1 Market and applications for NAND Flash memories
    1.1 Introduction
    1.2 Flash memory architectures
    1.3 Multi-bit per cell storage
    1.3.1 Memories scaling
    1.3.2 Multi-level cell concept
    1.3.3 NAND scaling
    1.3.4 Capacity
    1.3.5 Device characteristics
    1.4 Market and applications
    1.4.1 Removable portable storage
    1.4.2 Embedded storage
    1.4.3 Solid state drives
    1.5 Market outlook
    2 NAND overview: from memory to systems
    2.1 Introduction
    2.2 NAND memory
    2.2.1 Array
    2.2.2 Basic operations
    Read
    Program
    Erase
    2.2.3 Logic organization
    2.2.4 Pinout
    2.3 Command set
    2.3.1 Read operation
    2.3.2 Program operation
    2.3.3 Erase operation
    2.3.4 Synchronous operations
    2.4 NAND-based systems
    2.4.1 Memory controller
    Wear leveling
    Garbage collection
    Bad block management
    ECC
    2.4.2 Multi-die systems
    2.4.3 Die stacking
    2.4.4 3D memories and XLC storage
    References
    3 Program and erase of NAND memory arrays
    3.1 Floating gate cell physics
    3.1.1 The ONO IPD floating gate cell
    3.1.2 The band diagram of the floating gate cell
    3.1.3 Capacitive cell model
    3.2 Altering the stored charges
    3.2.1 Fowler–Nordheim tunneling mechanism
    3.2.2 Incremental step pulse programming ISPP
    3.2.3 Interaction between cell parameters and ISPP
    3.3 The NAND array
    3.4 The program operation and its side effects in the NAND array
    3.4.1 Self-boosted program inhibit SBPI
    3.4.2 Capacitive model of the NAND string
    3.4.3 Disturb effects
    3.4.3.1 Program disturb
    3.4.3.2 Pass disturb
    3.4.3.3 Edge disturb
    3.4.4 Advanced SBPI schemes
    3.4.4.1 Local SBPI schemes
    3.4.4.2 Asymmetric SBPI
    3.5 The erase operation and the NAND array
    3.5.1 Self-boosted erase inhibit SBEI
    3.5.2 Erase disturb
    3.6 Stochastic effects: Impact on cell distributions
    3.6.1 Process variations
    3.6.2 Floating gate cross-coupling
    3.6.3 Injection statistics
    3.6.4 Models for Cell–System Interaction
    References
    4 Reliability issues of NAND Flash memories
    4.1 Introduction
    4.2 Basic concepts
    4.3 Basic reliability effects related to tunnel oxides
    4.3.1 Endurance and intrinsic oxide degradation
    4.3.2 Hot Hole Injection oxide degradation
    4.3.3 Data retention
    4.3.4 Overprogramming
    4.3.5 General comments concerning oxide degradation
    4.4 Disturbs related to memory architecture
    4.5 Emerging reliability threats
    4.5.1 Gate Induced Drain Leakage
    4.5.2 Random Telegraph Noise
    4.5.3 Charge injection statistics
    4.5.4 Temperature instabilities
    References
    5 Charge trap NAND technologies
    5.1 Introduction
    5.2 Planar charge trap NAND
    5.2.1 Stack description
    5.2.2 Cell write mechanisms
    Program
    Erase
    5.2.3 Stack options
    5.2.4 Why charge trap memories?
    5.2.5 Planar charge trap issues
    5.3 3D charge trap memories
    Acknowledgments
    References
    6 Control logic
    6.1 Logic device view
    6.2 Command interface
    6.3 Test interface
    6.4 Datapath
    6.5 Microcontroller
    6.6 ROM
    6.7 RAM
    6.8 Meta-language
    References
    7 NAND DDR interface
    7.1 NAND Flash evolution: the need for increased bandwidth
    7.1.1 Applications driving the NAND high speed interface evolution
    7.1.2 Limitations of the asynchronous interface
    7.1.3 How to improve the performance of NAND based systems
    7.1.4 Adopting DDR protocol
    7.1.5 High density systems: density, power and performance
    7.2 Basic input output circuit design
    7.2.1 I/O circuits for asynchronous NAND
    7.2.2 Basic CMOS output buffer design
    7.2.3 Driving high capacitive loads and noise: slew rate control
    7.2.4 Simultaneous Switching Noise (SSN)
    7.3 High speed NAND I/O design
    7.3.1 High speed output buffer circuits
    7.3.2 Double data rate OCD
    7.3.3 OCD linearity: push–pull and open-drain configurations
    7.3.4 Slew rate control and bandwidth
    7.3.5 Voltage domain change: level shifting
    7.3.6 Jitter sources and duty cycle distortion
    7.3.7 ESD
    Input and output ESD protections
    7.3.8 Layout
    7.3.9 I/O capacitance problem
    References
    8 Sensing circuits
    8.1 Introduction
    8.2 Reading techniques using the bitline capacitor
    8.2.1 Interleaving architecture
    8.2.2 Interleaving architecture: page buffer core design
    8.3 Reading techniques with time-constant bitline biasing
    8.3.1 All BitLine (ABL) architecture
    8.3.2 ABL architecture: sensing design
    8.4 ABL versus interleaving architecture
    References
    9 Parasitic effects and verify circuits
    9.1 Background pattern dependency (BPD)
    9.2. Reading techniques for negative sensing
    9.2.1 Conventional negative verify
    9.2.2 Absolute negative sensing
    9.2.3 Current sensing
    9.2.4 Source line read for ABL sensing
    9.3 Source line bias error
    9.3.1 Sensing with source line bias compensation
    9.3.2 Multi-pass sensing
    References
    10 MLC storage
    10.1 MLC coding and programming algorithms
    10.1.1 Full-sequence programming
    10.1.2 Floating gate coupling reduction
    10.2 MLC sensing circuit
    10.2.1 Read
    10.2.2 Cache read
    10.2.3 MLC program/verify operations
    10.2.4 Check circuits
    10.2.5 Coarse and fine programming
    10.3 Data-load
    10.3.1 Data-load 1
    10.3.3 Data-load 3
    10.4 Moving read voltages
    References
    11 Charge pumps, voltage regulators and HV switches
    11.1 Charge pumps
    11.2 Read regulator
    11.3 Double-supply voltage regulator
    11.4 Voltage references
    11.5 Internal supply voltage regulator
    References
    12 High voltage overview
    12.1 Program algorithm
    12.2 Erase algorithm
    12.3 HV system
    12.4 Wordline decoder
    12.5 Hierarchical GWL decoder
    References
    13 Redundancy
    13.1 Redundancy concept
    13.2 NAND architecture and redundancy
    13.3 Process data failure analysis and redundancy requirements
    13.3.1 Failure analysis concept
    13.3.2 EWS substitution
    13.4 Redundancy architectures
    13.4.1 Realtime substitution
    13.4.2 Software substitution
    13.5 Fuse ROM
    13.6 NAND block as OTP for redundancy data concept
    References
    14 Error correction codes
    14.1 Introduction
    14.2 Mathematical background
    14.2.1 Block codes
    14.2.2 Convolutional codes
    14.3 BCH codes
    14.3.1 Encoding
    14.3.2 Decoding
    14.4 Reed–Solomon codes
    14.5 BCH versus Reed–Solomon
    14.6 Parallel BCH
    14.7 Low-Density Parity-Check (LDPC) code
    14.7.1 LDPC code decoding algorithm
    14.7.2 LDPC code construction and encoder/decoder design
    14.7.3 QC-LDPC code performance evaluation
    References
    15 NAND design for testability and testing
    15.1 NAND architecture and testing
    15.1.1 Array testing
    15.1.2 High voltage pumps testing
    15.1.3 Read circuitry testing
    15.2 NAND Flash memory testing introduction
    15.2.1 Test phases: first silicon, ramp-up, production
    15.2.2 NAND Flash test flow introduction
    Wafer level flow
    Back-end flow
    Burn-in
    15.2.3 Test flow and test time optimization
    15.2.4 KGD testing
    15.2.5 BAD Blocks Management
    15.3 NAND DFT
    15.3.1 Special test pads
    15.3.2 Low Pin Count Testing (LPCT)
    15.3.3 Voltage regulators and trimming
    15.3.4 Fuse ROM
    15.3.5 OTP Blocks
    15.3.6 Test interface
    15.3.7 Microcontroller as Built In Self Test (BIST) hardware
    15.3.8 Fail counter
    15.4 Fundamental NAND test modes
    15.4.1 Parallel tests
    Parallel wordline Program
    Parallel erase
    Parallel read
    Parallel program of array and redundancy
    15.4.2 Margin read
    15.4.3 Data fail compression
    15.4.4 Internal Vth search
    15.4.5 ROM, RAM, Fuse ROM testing
    15.4.6 Internal clock measurement
    15.4.7 Tests for defect detection and yield enhancement
    Shorts among bit lines detection
    Bit lines opens, string open
    Shorts between wordlines
    15.4.8 Stress modes
    References
    16 XLC storage
    16.1 Introduction
    16.2 VTH distribution width
    16.3 8LC
    16.3.1 Program sequence
    16.3.2 Program: circuits and cache operation
    16.3.3 Read: circuits and cache operation
    16.4 16LC
    16.4.1 Three rounds re-programming sequence
    16.4.2 Sequential sensing
    References
    17 Flash cards
    17.1 Introduction
    17.2 Memory card architecture and assembly
    17.3 Memory card specifications
    17.3.1 Pinout
    17.3.2 Commands and responses
    17.3.3 Registers
    17.4 Flash translation layer
    17.5 Cryptography
    17.6 Execute in place
    17.7 Managed memory
    17.7.1 Multibit and shrink technology issues
    Read disturb
    Pass disturb
    Program disturb
    Trapping and Detrapping
    Coupling
    17.7.2 Microcontroller solutions
    17.7.3 Flexible solution
    References
    18 Low power 3D-integrated SSD
    18.1 Introduction
    18.2 Analysis of SSD performance
    18.3 Selective bit-line precharge scheme
    18.4 Advanced source-line program
    18.5 Intelligent interleaving
    18.6 Sector size optimization
    18.7 Adaptive program-voltage generator for 3D-SSD
    18.8 Conclusions
    References
    19 Radiation effects on NAND Flash memories
    19.1 Introduction to radiation effects in CMOS circuits
    19.1.1 Environments
    19.1.1.1 Terrestrial environment
    19.1.1.2 Space
    19.1.2 Overview of radiation effects
    19.1.2.1 Radiation–matter interaction
    19.1.2.2 Categories of radiation effects
    19.1.3 Total ionizing dose effects
    19.1.3.1 Basic mechanisms
    19.1.3.2 Effects on MOSFETs
    19.1.3.3 Scaling
    19.1.4 Single event effects
    19.2 Radiation effects on NAND Flash memories
    19.2.1 Total ionizing dose effects
    19.2.1.1 Floating gate cells
    19.2.1.2 Charge pumps
    19.2.1.3 Decoders
    19.2.2 Single event effects
    19.2.2.1 Floating gate cells and page buffer
    19.2.2.2 Single event functional interruptions
    19.2.2.3 Power supply current spikes
    19.2.2.4 Overall cross section
    19.3 Radiation effects on floating gate cells
    19.3.1 Total ionizing dose
    19.3.2 Single event effects
    19.3.3 Long-term effects
    19.3.4 Atmospheric neutrons
    19.4 Conclusions
    References
    About the authors
    Index
    Inside NAND Flash Memories
    Rino Micheloni • Luca Crippa • Alessia Marelli Inside NAND Flash Memories
    Rino Micheloni Integrated Device Technology Agrate Brianza Italy rino.micheloni@ieee.org Luca Crippa Forward Insights North York Canada luca.crippa@ieee.org Alessia Marelli Integrated Device Technology Agrate Brianza Italy alessiamarelli@gmail.com ISBN 978-90-481-9430-8 DOI 10.1007/978-90-481-9431-5 Springer Dordrecht Heidelberg London New York e-ISBN 978-90-481-9431-5 Library of Congress Control Number: 2010931597 © Springer Science+Business Media B.V. 2010 No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. C ov er desig n eStudio Calamar S.L. : Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
    Preface In the last decade Flash cards became the most important digital storage support. It is difficult to identify a single killer application (digital photography, MP3, digital video, …) or whether the success of this media support is due to its usability in different applications. It is also difficult to state whether the recent revolution in the infotainment area has been triggered by the availability of high- performance NAND Flash memories or if the extraordinary success of Flash cards is a consequence of the establishment of new applications. In any case, independently of the cause–effect relationship linking new digital applications and Flash cards, to realize how NAND Flash memories entered in our daily life, it is sufficient to imagine as they would change our recent habits if the NAND memories disappeared suddenly. To take a picture it would be necessary to find a film (as well as a traditional camera…), disks or even magnetic tapes would be used to record a video or to listen a song, and a cellular phone would return to be a simple mean of communication rather than a console for an extended entertainment. The development of NAND Flash memories will not be set down on the mere evolution of these digital systems since a new killer application can trigger a further success for this memory support: the replacement of Hard Disk Drives (HDD) with Solid State Drives (SSD). The advantages of SSD with respect to HDD are countless (higher read/write speed, higher mechanical reliability, random access, silent operation, lower power consumption, lower weight, …). Nevertheless, the cost per gigabyte is still significantly favorable to HDD and the success of SSD will depend only on the performances that they will succeed in reaching. The present book, the fourth authored by Rino Micheloni and coworkers after VLSI-Design of Non-volatiles Memories, Memories in Wireless Systems and Error Correction Codes for Non-volatile Memories, all published by Springer, tackles all the main aspects related to NAND Flash memories, from the physical, technological, and circuit issues to their use in Flash cards and SSDs. After an extended market overview (Chap. 1), Chap. 2 has been conceived as a guide for the entire book, so that the reader can directly reach the heart of the problems that interest him. The following chapters deepen physical and technological aspects. In particular, Chaps. 3 and 4 tackle technological and reliability issues of traditional Floating- Gate NAND memories, respectively, while the state-of-the-art of charge trapping technologies is effectively summarized in Chap. 5. v
    vi Preface The central part of the book is dedicated to circuit issues: logic (Chap. 6), sensing circuits (Chaps. 8 and 9) and high voltage blocks (Chaps. 11 and 12). Other basic topics related to circuit aspects are also analyzed, such as the implementation of Double Data Rate interfaces (Chap. 7), while multilevel storage (2 bits per cell) is presented in Chap. 10. Techniques adopted to increase memory reliability and yield are discussed in Chaps. 13 and 14, the former dealing with redundancy, the latter with Error Correction Codes. The test flux used by NAND memories manufactures is described in Chap. 15. Chapter 16 focus on NAND devices storing 3 and 4 bits per cell that allow reaching the lower cost per gigabyte and that will conquer, in the next few years, the market of consumer applications. The last chapters are dedicated to the two most popular systems based on NAND memories: Flash cards (Chap. 17) and SSD (Chap. 18). The relationship between NAND memories and system performances are highlighted. Finally, Chap. 19 describes the effects of ionizing radiations on non-volatile memories, to understand whether NAND memories can be safely used in space and military applications. Prof. Piero Olivo, Dean of the Engineering Faculty, University of Ferrara, Italy
    Acknowledgements suggestions and fruitful discussions. After completing a project like a technical book, it is very hard to acknowledge all the people who have contributed directly or indirectly with their work and dedication. First of all, we wish to thank all the authors of the contributed chapters. We have to thank Mark de Jongh for giving us the possibility of publishing this work and Cindy Zitter for her continuous support. Last but not least, we keep in mind all our present and past colleagues for their Rino, Luca and Alessia vii
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