Contents
About This Book
Purpose
Audience
Book Organization
Conventions Used in This Book
Related Publications
How to Reach SpringSoft Inc.
Introduction
Overview
Technology Overview
Compilers, Interfaces and Interoperability
Databases
Analysis Engines
Visualization
User Interface
Overview
Common User Interface Features
Window Banner
Pull-down Menus
Mnemonic Keys
Bind Keys
On-line Help
Toolbars
Mouse Operation
Right Mouse Button Menus
nTrace User Interface
nTrace Hierarchy Browser Pane
nTrace Hypertext Source Code Pane
Source Code Area
Indicator Area
nTrace Message Pane
nTrace Toolbar Icons
nTrace User Interface in Interactive Mode
Interactive Mode Symbols in Indicator Area
nTrace Interactive Simulation Control Toolbar Icons
nTrace Mouse Operations
nWave User Interface
nWave Signal Pane
Signal Name
Signal Cursor
Group Name
nWave Value Pane
nWave Waveform Pane
Cursor
Marker
Zoom-scale Ruler
Full-scale Ruler
nWave Toolbar Icons
Get Signals
nWave Mouse Operations
nSchema User Interface
nSchema Toolbar Icons
nSchema Mouse Operations
nState User Interface
nState Toolbar Icons
nState Mouse Operations
Flow View User Interface
Flow View Toolbar Icons
Flow View Mouse Operations
Transaction User Interface
Detailed Transaction View in nWave
Transaction Properties
Transaction Attributes
Analyzing Transactions
nCompare User Interface
nECO User Interface
nAnalyzer User Interface
Toolbars for Other Windows
Event Sequence Window
List X Window
Before You Begin
Installation and Setup
Demo Details
Launching Techniques
Reference Source Files on Command Line
Compile Source Code into a Library
Reference Design and FSDB on the Command Line
Perform Behavior Analysis on the Command Line
Replay a File
Start Verdi without Specifying Any Source Files
Loading when Design and FSDB Hierarchies do not Match
nTrace Tutorial
Overview
Traverse the Design Hierarchy in nTrace
Access a Block’s Source Code
Find Scope
Trace Drivers and Loads
Find String
Trace Driver
Add Bookmarks
Trace Load
Trace Connectivity
Save Trace Result and Reset History
Edit Source Code
Use Active Annotation
Trace the Active Driver
nSchema Tutorial
Overview
Start nSchema
Manipulate the Schematic View
Change the Schematic View Among Instances
Enable Viewing Objects
Find an Instance or a Signal in a Schematic
Change the Color of the Selected Signal
Trace Signals
Find the Drivers of a Signal
Find the Load of a Signal
Find the Connectivity of a Signal and Generate a New Schematic from Trace Results
Show RTL Block Diagram in a More Meaningful Way
Generate Partial Schematics
Hierarchical
Flatten Window
Fan-in and Fan-out
Trace Between Two Points
Capture the Schematic View
Use Active Annotation to Show Signal Values
Change the Color or the Line Style for Annotations
nWave Tutorial
Start nWave and Open a Simulation Result File
Add Signals
Add Signals from Other Windows
Use Get Signals to Add Signals
Search for Signals to Add
Manipulate the Waveform View
Set the Cursor/Marker Positions
Zoom Cursor with Three Clicks
Fast Zoom on the Full Scale Ruler
Pan the Waveform
Use Bind Key Commands
Turn On/Off Signal Grids
Add Marker Labels
Change the Display Sequence of Signals
Search for Signal Value Transitions
Add Comments
Compress Time Ranges
Split the Waveform View
Change Signal/Group Attributes
Search for a Group
Change the Group Name
Display Hierarchical Signal Names
Modify the Display Format in the Value Window
Add Alias to Display Bus Values
Change the Spacing and Signal Height
Change Signal Color/Pattern
Create New Signals/Buses from Existing Signals
Logical Operations
Bus Creation
Expand or Collapse the Bus
Events/Complex Events
Save and Restore Signals
Save the Displayed Signals
Restore Previously Saved Signals
Create a Second Waveform Window and Restore Other Signals
nState Tutorial
Overview
Start nState
Manipulate the State Diagram View
Enable Viewing Objects
Find the Start and End States of a Transition
Create a Partial Finite State Machine View
State Animation
State Machine Analysis
Temporal Flow View Tutorial
Overview
Invoke a Temporal Flow View
Manipulate the View
Display More Information
Show Active Statements
Display Source Code
Add Signals from the Temporal Flow View to nWave
Compact Temporal Flow View
Showing Statement Flow in an nSchema Window
Temporal Register View
Debug a Design with Simulation Results Tutorial
Find the Active Driver
Generate Fan-in Cone
Debug Memory Content
Application Tutorials
Quickly Search Backward in Time for Value Causes
Invoke a Temporal Flow View
Show Active Statements
Trace This Value Automatically
Trace Another Path
Show Signals on nWave
Debug Memories
Debug Synthesizeable Memory Models
Locate the Cause of a Value on a Signal
Locate the Last Write of a Specific Address Location
Show Memory Contents
Search Values in the nMemory Window
Synchronize the nMemory Window with nWave
Change Address and Time in the nMemory Window
Customize the nMemory Window
Display Calculated Memory Contents in nWave
Debug Non-synthesizeable Memory Models
1-port Static RAM
Create a Memory Model Definition for the 1-port Static RAM
Trace the Memory Contents
Display the Memory Contents in nWave
Multiple-port Static RAM
Create a Memory Model Definition for the Multiple-port Static RAM
Debug PLI Memory Models
Create a PLI Memory Definition File
Load the PLI Memory Definition File
Trace the Content of the PLI Memory
Debug Gate vs. RTL Simulation Mismatch
Locate the Signal to Compare
Load Simulation Results and Display Waveforms
Compare the Simulation Results
Isolate the Problem
Behavior Trace for Root Cause of Simulation Mismatches
Locate the Simulation Mismatch
Behavior Trace for the Root Cause of Mismatch
Debug Unknown (X) Values
Locate the Root Cause of the “X” Value on ZFout
Visualize the Active Paths in the Temporal Flow View
Debug Finite State Machines
Display the State Register in nWave
Locate Trigger Conditions from the State Sequences
Unroll State Sequences Over Multiple Cycles
Synchronize the Temporal Register View with nState
Trace Active Control Signals for Each State Transition in nWave
Expand the Logic Cones for One of the Condition Signals
Debug with SystemVerilog
Import the Design
Load Files Directly
Use Compiled Library - Optional
Visualize SystemVerilog Source Code
Hierarchy Browser
Source Code
Schematic
View SystemVerilog Simulation Results
Waveform
Source Code
Generate Constructs
Debug with SystemVerilog Assertions (SVA)
Import the Design
Load Files Directly
Use Compiled Library - Optional
Visualize SVA Source Code
Hierarchy Browser and Source Code
Property Tools
View SVA Simulation Results
Property Tools
Waveform
Source Code
Generate Constructs
Analyze SVA Assertions
Evaluate SVA Assertions
Debug with Transactions
What is a Transaction?
Generating Transaction Data
Provided FSDB Dumpers
Transaction IP Partners
SVA Extraction
FSDB Writer API and the Open Transaction Interface (OTI)
View Transactions in nWave
View Transactions in Transaction Analyzer Window
Add/Remove Transaction Streams
Merge Transaction Streams
Manipulate the Stream View
Set the Cursor/Marker
Change the Column (Attribute) Display
Filter the Transactions
Generate Statistics
Interactive Simulation Control
Before You Begin
About the Simulators
Interactive Mode Linking with Synopsys VCS (4.2 or later)
Interactive Mode Linking MTI ModelSim (5.2 or later)
Set the Simulator Executable
Invoke Simulator and Run the Tutorial
Dump the Value Change Information to an FSDB File
Run the Simulator to Time 500
Invoke nWave
Add Signals in Watch Window
Issue Commands in the Simulator I/O Window
Set Breakpoint in Source Window
Step Through the Source Code and Annotate Simulation Values
Turn on Active Annotation
Advance the Simulation
Set Focus
Step the Simulation
Delete the Focus
Delete the Line 84 Breakpoint
Use the Breakpoints Command
Resume the Simulation
Delete the Breakpoint
Use the User-Defined Commands
Show the Data's Value
Show Variables Constantly
Collect Signals of Interest
Define User-Defined Commands
Invoke the Editing Function
Define the Save Command
Execute the Save Command
Appendix A: Supported Waveform Formats
Overview
Fast Fourier Transformers (FFT)
Introduction
Getting Data from Analog Signal
Getting Data from Synopsys HSIM FFT
Data Manipulation in FFT Window
EVCD
Analog Waveform Example
View the Analog Waveform
Manipulate the Analog Waveform
Change the Signal Height
Display the Analog Ruler
View Different Simulation Results in the Same Window
Overlap Analog Signals from Different Simulation Results
Appendix B: Supported FSM Coding Styles
Overview
One-Process (Always)
Example 1 - Verilog (one_process.v)
Example 2 - VHDL (one_process.vhd)
Two-Process (Always)
Example 1 - Verilog (two_process.v)
Example 2 - VHDL (two_process.vhd)
One-Hot Encoding
Shift Arithmetic Operation
Case-Statement vs. If-Statement
Example 1
Example 2
Gate-Like FSM
Next_State = signal
Next_State = Current_State + N
VHDL Record Type
Appendix C: Enhanced RTL Extraction
Overview
Instance Array
For Loop
Aggregate
Partial Bits Assignment
Displaying Pure Memory Blocks
Appendix D: Additional Transaction Examples
Extract Transactions Using SystemVerilog Assertions (SVA)
SVA Code
Recommended Coding Style
Unsupported Coding Style
Code Example
Analyze Transactions Using Tcl
Execute the Tcl File
Manipulate Transactions and View Statistics with Tcl
Example Tcl Script
Generate an FSDB File with Transaction Information
PLI Background
Procedures for Writing a PLI Routine
Steps for Writing FSDB
Steps to Dump Transactions to FSDB
C Files for FSDB Writer API
Use Provided C Files for PCI Transaction Dumping
Index