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    Cover
    The Art of Hardware Architecture
    ISBN 9781461403968
    Preface
    Acknowledgements
    Contents
    Chapter 1: The World of Metastability
    1.1 Introduction
    1.2 Theory of Metastability
    1.3 Metastability Window
    1.4 Calculating MTBF
    1.5 Avoiding Metastability
    1.5.1 Using a Multi-stage Synchronizer
    1.5.2 Multi-stage Synchronizer Using Clock Boost Circuitry
    1.6 Metastability Test Circuitry
    1.7 Types of Synchronizers
    1.8 Metastability/General Recommendations
    Chapter 2: Clocks and Resets
    2.1 Introduction
    2.2 Synchronous Designs
    2.2.1 Avoid Using Ripple Counters
    2.2.2 Gated Clocks
    2.2.3 Double-Edged or Mixed Edge Clocking
    2.2.4 Flip Flops Driving Asynchronous Reset of Another Flop
    2.3 Recommended Design Techniques
    2.3.1 Avoid Combinational Loops in Design
    2.3.2 Avoid Delay Chains in Digital Logic
    2.3.3 Avoid Using Asynchronous Based Pulse Generator
    2.3.4 Avoid Using Latches
    2.3.5 Avoid Using Double-Edged Clocking
    2.3.5.1 Advantages of Dual Edge Clocking
    2.4 Clocking Schemes
    2.4.1 Internally Generated Clocks
    2.4.2 Divided Clocks
    2.4.3 Ripple Counters
    2.4.4 Multiplexed Clocks
    2.4.5 Synchronous Clock Enables and Gated Clocks
    2.5 Clock Gating Methodology
    2.5.1 Latch Free Clock Gating Circuit
    2.5.2 Latch Based Clock Gating Circuit
    2.5.3 Gating Signals
    2.5.4 Data Path Re-ordering to Reduce Switching Propagation
    2.6 Reset Design Strategy
    2.6.1 Design with Synchronous Reset
    2.6.1.1 Advantages of Using Synchronous Resets
    2.6.1.2 Disadvantages of Using Synchronous Resets
    2.6.2 Design with Asynchronous Reset
    2.6.2.1 Advantages of Using Asynchronous Resets
    2.6.2.2 Disadvantages of Using Asynchronous Resets
    2.6.3 Flip Flops with Asynchronous Reset and Asynchronous Set
    2.6.4 Asynchronous Reset Removal Problem
    2.6.5 Reset Synchronizer
    2.6.6 Reset Glitch Filtering
    2.7 Controlling Clock Skew
    2.7.1 Short Path Problem
    2.7.2 Clock Skew and Short Path Analysis
    2.7.3 Minimizing Clock Skew
    2.7.3.1 Adding Delay in Data Path
    2.7.3.2 Clock Reversing
    2.7.3.3 Alternate Phase Clocking
    Clocking on Alternate Edges
    Clocking on Alternate Phases
    Ripple Clocking Structure
    2.7.3.4 Balancing Trace Length
    References
    Chapter 3: Handling Multiple Clocks
    3.1 Introduction
    3.2 Multiple Clock Domains
    3.3 Problems with Multiple Clock Domains Design
    3.3.1 Setup Time and Hold Time Violation
    3.3.2 Metastability
    3.4 Design Tips for Efficient Handling of a Design with Multiple Clocks
    3.4.1 Clock Nomenclature
    3.4.2 Design Partitioning
    3.4.3 Clock Domain Crossing
    3.4.3.1 Transfer of Control Signals (Synchronization)
    3.4.3.2 Transfer of Data Signals
    3.5 Synchronous Clock Domain Crossing
    3.5.1 Clocks with the Same Frequency and Zero Phase Difference
    3.5.2 Clocks with the Same Frequency and Constant Phase Difference
    3.5.3 Clocks with the Different Frequency and Variable Phase Difference
    3.5.3.1 Clocks with Integral Multiple Frequencies
    3.5.3.2 Clocks with Non-integral Multiple Frequencies
    3.6 Handshake Signaling Method
    3.6.1 Requirements for Handshake Signaling
    3.6.2 Disadvantages of Handshake Signaling
    3.7 Data Transfer Using Synchronous FIFO
    3.7.1 Synchronous FIFO Architecture
    3.7.2 Working of Synchronous FIFO
    3.7.2.1 FIFO Full and Empty Generation
    3.7.2.2 An Alternative Approach
    3.8 Asynchronous FIFO (or Dual Clock FIFO)
    3.8.1 Avoid Using Binary Counters for the Pointer Implementation
    3.8.2 Use Gray Coding Instead of Binary for the Counters
    3.8.2.1 Effect of Synchronization of Pointers
    3.8.3 Gray Code Implementation of FIFO Pointers
    3.8.3.1 Gray to Binary Converter
    3.8.3.2 Binary to Gray Converter
    3.8.3.3 Gray code counter implementation
    3.8.4 FIFO Full and FIFO Empty Generation
    3.8.4.1 An Alternative approach for FIFO Full and FIFO Empty Generation
    3.8.5 Dual Clock FIFO Design
    3.8.5.1 FIFO Empty Condition Generation
    3.8.5.2 FIFO Full Condition Generation
    References
    Chapter 4: Clock Dividers
    4.1 Introduction
    4.2 Synchronous Divide by Integer Value
    4.3 Odd Integer Division with 50% Duty Cycle
    4.4 Non-integer Division (with a Non 50% Duty Cycle)
    4.4.1 Divide by 1.5 with Non 50% Duty Cycle
    4.4.2 Counter Implementation for Divide by 4.5 (Non 50% Duty Cycle)
    4.5 Alternate Approach for Divide by N
    4.5.1 LUT Implementation for Divide by 1.5
    Reference
    Chapter 5: Low Power Design
    5.1 Introduction
    5.2 Sources of Power Consumption
    5.3 Power Reduction at Different Levels of Design Abstraction
    5.4 System Level Power Reduction
    5.4.1 System on Chip (SoC) Approach
    5.4.2 Hardware/Software Partitioning
    5.4.3 Low Power Software
    5.4.4 Choice of Processor
    5.5 Architecture Level Power Reduction
    5.5.1 Advanced Clock Gating
    5.5.2 Dynamic Voltage and Frequency Scaling (DVFS)
    5.5.3 Cache Based Architecture
    5.5.4 Log FFT Architecture
    5.5.5 Asynchronous (Clockless) Design
    5.5.6 Power Gating
    5.5.6.1 Fine-Grain Power Gating
    5.5.6.2 Coarse Grain Power Gating
    5.5.7 Multi-threshold Voltage
    5.5.8 Multi-supply Voltage
    5.5.9 Gate Memory Power
    5.6 Register Transfer Level (RTL) Power Reduction
    5.6.1 State Machine Encoding and Decomposition
    5.6.2 Binary Number Representation
    5.6.3 Basic Gated Clock
    5.6.4 One Hot Encoded Multiplexer
    5.6.5 Removing Redundant Transactions
    5.6.6 Resource Sharing
    5.6.7 Using Ripple Counters for Low Power
    5.6.8 Bus Inversion
    5.6.9 High Activity Nets
    5.6.10 Enabling-Disabling Logic Clouds
    5.7 Transistor Level Power Reduction
    5.7.1 Technology Level
    5.7.2 Layout Optimization
    5.7.3 Substrate Biasing
    5.7.4 Reduce Oxide Thickness
    5.7.5 Multi-oxide Devices
    5.7.6 Minimizing Capacitance by Custom Design
    References
    Chapter 6: The Art of Pipelining
    6.1 Introduction
    6.2 Factors Affecting the Maximum Frequency of Clock
    6.2.1 Clock Skew
    6.2.2 Clock Jitter
    6.3 Pipelining
    6.4 Pipelining Explained – A Real Life Example
    6.5 Performance Increase from Pipelining
    6.6 Implementation of DLX Instruction
    6.7 Effect of Pipelining on Throughput
    6.8 Pipelining Principles
    6.9 Pipelining Hazards
    6.9.1 Structural Hazards
    6.9.2 Data Hazards
    6.9.3 Control Hazards
    6.9.4 Other Hazards
    6.10 Pipelining in ADC – An Example
    References
    Chapter 7: Handling Endianness
    7.1 Introduction
    7.2 Definition
    7.3 Little-Endian or Big-Endian: Which Is Better?
    7.4 Issues Dealing with Endianess Mismatch
    7.5 Accessing 32 Bit Memory
    7.6 Dealing with Endianness Mismatch
    7.6.1 Preserve Data Integrity (Data Invariance)
    7.6.1.1 Data Flow
    7.6.2 Address Invariance
    7.6.2.1 Data Flow
    7.6.3 Software Byte Swapping
    7.6.3.1 Methods
    Swap Assembly Instructions
    Swap Library Macros
    Protocol Specific Macros
    Limitation
    7.7 Endian Neutral code
    7.8 Endian-Neutral Coding Guidelines
    References
    Chapter 8: Deboucing Techniques
    8.1 Introduction
    8.2 Behavior of a Switch
    8.3 Switch Types
    8.4 De-bouncing Techniques
    8.4.1 RC De-bouncer
    8.4.2 Hardware De-bouncers
    8.4.3 Software De-bouncing
    8.4.4 De-bouncing Guidelines
    8.4.5 De-bouncing on Multiple Inputs
    8.5 Existing Solutions
    Chapter 9: Design Guidelines for EMC Performance
    9.1 Introduction
    9.2 Definition
    9.3 EMI Theory and Relationship with Current and Frequency
    9.4 EMI Regulations, Standards and Certification
    9.5 Factors Affecting IC Immunity Performance
    9.5.1 Microcontroller as Noise Source
    9.5.2 Other Factors Affecting EMC
    9.5.3 Noise Carriers
    9.6 Techniques to Reduce EMC/EMI
    9.6.1 System Level Techniques
    9.6.1.1 Spread Spectrum Clocking
    9.6.1.2 Differential Clocking
    9.6.2 Board Level Techniques
    9.6.2.1 Power Entry Filtering
    9.6.2.2 More Filtering
    EMI Filters
    9.6.2.3 Component Placement
    9.6.2.4 Path to Ground
    9.6.2.5 Trace Routing
    9.6.2.6 Creating Zones
    9.6.2.7 Power Coupling
    9.6.2.8 PCB Power Distribution and Decoupling Capacitors
    9.6.3 Microcontroller Level Techniques
    9.6.3.1 Multiple Clocks and Grounds
    9.6.3.2 Eliminate Race Conditions
    9.6.3.3 Reduce System Speed
    9.6.3.4 Driver Sizing
    9.6.3.5 Clock Generation and Distribution
    9.6.3.6 Duty Cycle Consideration
    9.6.3.7 Reducing Noise on Data Buses
    9.6.4 Software Level Techniques
    9.6.4.1 General I/O Pin Protection
    9.6.4.2 Digital Input Pins
    9.6.4.3 Digital Output and Critical Registers
    9.6.4.4 Reset Pin Protection
    9.6.4.5 Oscillator and Other Sensitive Pins
    9.6.4.6 Watchdog Timer
    9.6.4.7 Illegal Instruction and Illegal Address Resets
    9.6.4.8 Low Voltage Detect (LVD)/Low Voltage Warning (LVW)
    9.6.5 Other Techniques
    9.6.5.1 Multiple Power and Grounds Pins
    9.6.5.2 Use Slowest Technology
    9.7 Summary
    References
    References
    Index
    The Art of Hardware Architecture
    wwwwwwwwwwwwwwwwwwww
    Mohit AroraDesign Methods and Techniques for Digital Circuits
    Mohit AroraFreescale Semiconductor Faridabad Indiamohit.arora@me.com
    This book is dedicated to my wife Pooja and my daughter Prisha.
    wwwwwwwwwwwwwwwwwwww
    viiPrefaceI started my Industry career in year 2000 in the field of Chip Design. My work involved lot of research that gave me opportunity to write technical papers, partici-pate in various conferences and share practical experiences. During this journey I got lot of positive feedback on my publications. Readers have often asked me forc-ing me to think if I should write a book compiling all the practical experiences. The book’s aim is to highlight all the complex issues, tasks and skills that must be mas-tered by an IP designer to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies prescribed in the book, if properly employed, can significantly reduce the time it takes to convert initial ideas and con-cepts into right-first-time silicon.The book is intended for a wide audience. Though it may be used in an under-graduate or graduate course, book is mainly intended for those in semiconductor industries who are directly involved with chip design and requires deeper understand of the subject.This book is distinguished from others by its primary focus on real problems rather than theoretical concepts with its emphasis on design techniques across various aspects of chip-design.The book covers aspects of chip design in a consistent way, starting with basic concepts in Chap. 1 and gradually increasing the depth to reach advanced concepts, such as EMC design techniques or sophisticated low power techniques like DVFS (Dynamic Voltage and Frequency scaling).Chapter 1 covers “metastability” to help user understand more clearly the issues related to metastability, how it can be quantified and necessary techniques to mini-mize its effort.Chapter 2 covers general set of recommendations around “clocks and resets” intended for use by designers while designing a block or Intellectual Property (IP). The guidelines are independent of any CAD tool or silicon process and are appli-cable to any ASIC designs.
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