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RT5350 Datasheet.pdf

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    Introduction
    1 Pin Description
    1.1 196-Pin BGA Package Diagram
    1.2 Pin Description
    1.3 Pin Sharing Scheme
    1.4 Boot strapping description
    2 Maximum Ratings and Operating Conditions (TBD)
    2.1 Absolute Maximum Ratings
    2.2 Thermal Information
    2.3 Operating Conditions
    2.4 Storage Condition
    2.5 External Xtal Specfications
    2.6 DC Electrical Characteristics
    2.7 AC Electrical Characteristics
    2.7.1 SDRAM Interface
    2.7.2 Power On Sequence
    3 Function Description
    3.1 Overview
    3.2 Memory Map Summary
    3.3 MIPS 24 Kbps Processor
    3.3.1 Features
    3.3.2 Block Diagram
    3.3.3 Clock Plan
    3.4 System Control
    3.4.1 Features
    3.4.2 Block Diagram
    3.4.3 Register Description (base: 0x1000_0000)
    3.4.4 Timer (TBD)
    3.4.5 Features
    3.4.6 Block Diagram
    3.4.7 Register Description (base: 0x1000_0100)
    3.5 Interrupt Controller
    3.5.1 Features
    3.5.2 Block Diagram
    3.5.3 Register Description (base: 0x1000_0200)
    3.6 System Tick Counter
    3.6.1 Register Description (base: 0x1000_0d00)
    3.7 UART
    3.7.1 Features
    3.7.2 Block Diagram
    3.7.3 Register Description (base: 0x1000_0500)
    3.8 UART Lite
    3.8.1 Features
    3.8.2 Block Diagram
    3.8.3 Register Description (base: 0x1000_0c00)
    3.9 Programmable I/O
    3.9.1 Features
    3.9.2 Block Diagram
    3.9.3 Register Description (base: 0x1000_0600)
    3.10 I2C Controller
    3.10.1 Features
    3.10.2 Block Diagram
    3.10.3 Register Description (base: 0x1000_0900)
    3.10.4 Programming Description
    3.11 PCM Controller
    3.11.1 Features
    3.11.2 Block Diagram
    3.11.3 Register Description (base: 0x1000_2000)
    3.11.4 An Example of PCM Configuration
    3.12 Generic DMA Controller
    3.12.1 Features
    3.12.2 Block Diagram
    3.12.3 Peripheral Channel Connection
    3.12.4 Register Description (base: 0x1000_2800)
    3.13 SPI Controller
    3.13.1 Features
    3.13.2 Block Diagram
    3.13.3 Register Description (base: 0x1000_0b00)
    3.14 I2S Controller
    3.14.1 Features
    3.14.2 Block Diagram
    3.14.3 I2S Signal Timing for I2S Data Format
    3.14.4 Register Description of I2S (base: 0x1000_0a00)
    3.15 Memory Controller
    3.15.1 Features
    3.15.2 Block Diagram
    3.15.3 SDRAM Initialization Sequence
    3.15.4 Register Description (base: 0x1000_0300)
    3.16 USB Host Controller & PHY
    3.16.1 Features
    3.16.2 Block Diagram
    3.16.3 Register Description (base: 0x101c_0000)
    3.16.4 EHCI Operation register (base: 0x101c_0000)
    3.16.5 OHCI Operation register (base: 0x101c_1000)
    3.17 USB Device Controller
    3.17.1 Features
    3.17.1.1 PDMA Descriptor Format
    3.17.1.2 Bulk-out Aggregation Format
    3.17.2 Register Description (base: 0x1012_0000)
    3.17.2.1 USB Control Registers
    3.17.2.2 UDMA Registers
    3.17.2.3 PDMA Registers
    3.18 Frame Engine
    3.18.1 Features
    3.18.2 Block Diagram
    3.18.2.1 PDMA FIFO-like Ring Concept
    3.18.2.2 PDMA Descriptor Format
    3.18.3 PDMA Register Description (base: 0x1010_0800)
    3.18.4 SDM Register Description (base: 0x1010_0c00)
    3.19 Ethernet Switch
    3.19.1 Features
    3.19.2 Block Diagram
    3.19.3 Frame Classification
    3.19.4 Register Description (base: 0x1011_0000)
    3.19.5 MII Control Register
    3.19.6 Function Description
    3.19.6.1 Flow Control Settings
    3.19.6.2 VID and Tagging
    3.19.6.3 VID and VLAN Member Set
    3.19.6.3.1 Tag and Untag
    3.19.6.3.2 Port VID
    3.19.6.3.3 Double Tag
    3.19.6.3.4 Special Tag
    3.19.6.4 Packet Classification, QoS, Scheduling and Buffer Control
    3.19.6.5 Spanning Tree Protocol
    3.20 802.11n 1T1R MAC/BBP
    3.20.1 Features
    3.20.2 Block Diagram
    3.20.3 Register Description - SCH/WPDMA (base: 0x1018_0000)
    3.20.3.1 Register Description - PBF (base: 0x1018_0000)
    3.20.3.2 Register Description – RF TEST (base: 0x1018_0000)
    3.20.3.3 Register Description - MAC (base: 0x1018_0000)
    3.20.3.4 MAC Tx Configuration Registers (offset: 0x1300)
    3.20.3.5 MAC Rx Configuration Registers
    3.20.3.6 MAC Security Configuration Registers
    3.20.3.7 MAC HCCA/PSMP CSR
    3.20.3.8 MAC Statistics Counters
    3.20.3.9 MAC Search Table (base: 0x1018_0000, offset: 0x1800)
    3.20.3.10 Security table/CIS/Beacon/NULL frame (base : 1018_0000, offset: 0x4000)
    3.20.4 Security Key Format (8DW)
    3.20.5 IV/EIV Format (2 DW)
    3.20.6 WCID Attribute Entry Format (1DW)
    3.20.7 Shared Key Mode Entry Format (1DW)
    3.20.7.1 Security Tables
    3.20.8 Descriptor and Wireless information
    3.20.8.1 Tx Frame Information
    3.20.8.2 Tx Descriptor Format
    3.20.8.3 TXWI Format
    3.20.8.4 Rx Descriptor Ring
    3.20.8.5 RX Descriptor Format
    3.20.8.6 RXWI Format
    3.20.8.7 Brief PHY Rate Format and Definition
    3.20.9 Driver Implementation Note
    3.20.9.1 Instructions for Downloading 8051 Firmware
    3.20.9.2 Instructions for Initializing DMA
    3.20.9.3 Instructions for Clock Control
    3.20.9.3.1 Clock Turn-off Sequence
    3.20.9.3.2 Clock Turn-on Sequence
    3.20.9.4 Instructions for Tx/Rx Control
    3.20.9.4.1 Freeze Tx and Rx Sequence
    3.20.9.4.2 Recover Tx and Rx Sequence
    3.20.9.5 Instructions for RF Power on/off Sequence
    3.20.9.5.1 Power down RF components sequence:
    3.20.9.5.2 Enable RF components sequence:
    3.20.9.6 Power Saving Procedure
    3.20.9.7 Power Recovery Procedure
    3.20.9.8 Parameters
    4 Packaging Physical Dimensions
    3
    4.1 TFBGA 196B（12×12×0.94 mm）
    5 Revision History
    RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 Introduction The RT5350 SoC combines Ralink’s IEEE 802.11n draft compliant 1T1R MAC/BBP/PA/RF, a high performance 360 MHz MIPS24KEc CPU core, a 5-port integrated 10/100 Ethernet switch/PHY and a USB host/device. With the RT5350, there are very few external components required for 2.4 GHz 802.11n wireless products. The RT5350 employs Ralink’s 2nd generation 802.11n technologies for longer range and better throughput. The embedded, high performance CPU can easily manage advanced applications such as Wi-Fi data processing without overloading the host processor. In addition, the RT5350 offers a variety of hardware interfaces (SPI/I2S/I2C/PCM/UART/USB) to support a range of possible applications. KB D cache Supports 16-bit SDR SDRAM (up to 64 MB) Supports boot from ROM, FLASH  AP/Router  MIPS 24KEc 360 Mhz with 32 KB I cache/16    USB 2.0 HOST/Device dual mode x1  Embedded 5-port 10/100 Mbps Ethernet switch and 5-port UTP PHY Supports 5 10/100 UTP ports Slow speed I/O : GPIO, SPI, I2C, I2S, PCM, UART, and JTAG Applications  iNIC Features   Embedded 1T1R 2.4G CMOS RF Embedded 802.11n 1T1R MAC/BBP with MLD enhancement Embedded PA/LNA Legacy and high throughout modes   150 Mbps PHY data rate  20 Mhz/40 MHz channel width   Compressed block ACK  Bluetooth Co-existence  Multiple BSSID (up to 16)  WEP64/128, WPA, WPA2, WAPI engines  QOS - WMM, WMM Power Save  Hardware frame aggregation  Supports 802.11h TPC    Packaging and I/O voltage  12 mm x 12 mm TFBGA-196 package  I/O: 3.3 V I/O 1T2R Diversity 40/20 MHz Crystall 802.11n 1T1R 2.4 GHz RF Functional Block Diagram Order Information Ralink Technology Corp. (USA) Suite 200 20833 Stevens Creek Blvd. Cupertino, CA95014 Tel: 408-725-8070 Fax: 408-725-8069 FE Router Transform er Clock/Timer/Reset/PLL 802.11n 1T1R MAC BBP MIPS 24KEc (360 MHz) 32K I - Cache 16K D - Cache Fast Ethernet Switch 4 1 2 3 0 SDRAM/ Controller UART Full+Lite USB 2.0 Host/Device PHY I2C I2S SPI PCM 16bit SDRAM UART Interface USB 2.0 Interface EEPROM/Control Audio Interface SLIC Codec External Interface GPIO/LED Ralink Technology Corp. (Taiwan) 5F. 36 Taiyuan St, Jhubei City, Hsin-Chu Taiwan, R.O.C Tel: 886-3-560-0868 Fax: 886-3-560-0818 Part Temp Number Range RT5350F -10~ 55 0C Packaging Green/RoHS Compliant TFBGA 196 ball (12 mm x 12 mm) DSRT5350_V1.0_112510 Form No.：QS-073-F02 Rev.：1 Kept by： DCC -1- Ret. Time： 5 Years Draft
    RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 Table of Contents INTRODUCTION ....................................................................................................................................................... 1 1 PIN DESCRIPTION .......................................................................................................................................... 6 1.1 196-PIN BGA PACKAGE DIAGRAM .................................................................................................................. 6 1.2 PIN DESCRIPTION .......................................................................................................................................... 6 1.3 PIN SHARING SCHEME .................................................................................................................................. 12 1.4 BOOT STRAPPING DESCRIPTION ...................................................................................................................... 14 2 MAXIMUM RATINGS AND OPERATING CONDITIONS (TBD) ........................................................................ 15 2.1 ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 15 2.2 THERMAL INFORMATION .............................................................................................................................. 15 2.3 OPERATING CONDITIONS .............................................................................................................................. 15 2.4 STORAGE CONDITION ................................................................................................................................... 15 2.5 EXTERNAL XTAL SPECFICATIONS ..................................................................................................................... 15 2.6 DC ELECTRICAL CHARACTERISTICS .................................................................................................................. 15 2.7 AC ELECTRICAL CHARACTERISTICS ................................................................................................................... 15 SDRAM Interface ........................................................................................................................... 16 Power On Sequence ...................................................................................................................... 17 2.7.1 2.7.2 3 FUNCTION DESCRIPTION ............................................................................................................................. 18 3.4.4 3.5 3.4.1 3.4.2 3.4.3 3.4.5 3.4.6 3.4.7 3.3.1 3.3.2 3.3.3 3.1 OVERVIEW ................................................................................................................................................. 18 3.2 MEMORY MAP SUMMARY ............................................................................................................................ 19 3.3 MIPS 24 KBPS PROCESSOR .......................................................................................................................... 20 Features ........................................................................................................................................ 20 Block Diagram ............................................................................................................................... 21 Clock Plan ...................................................................................................................................... 21 3.4 SYSTEM CONTROL ....................................................................................................................................... 22 Features ........................................................................................................................................ 22 Block Diagram ............................................................................................................................... 22 Register Description (base: 0x1000_0000) ................................................................................... 22 TIMER (TBD)......................................................................................................................................... 31 Features ........................................................................................................................................ 31 Block Diagram ............................................................................................................................... 33 Register Description (base: 0x1000_0100) .................................................................................. 33 INTERRUPT CONTROLLER ............................................................................................................................... 37 Features ........................................................................................................................................ 37 Block Diagram ............................................................................................................................... 37 Register Description (base: 0x1000_0200) ................................................................................... 37 3.6 SYSTEM TICK COUNTER ................................................................................................................................ 42 Register Description (base: 0x1000_0d00) ................................................................................... 42 3.7 UART ....................................................................................................................................................... 43 Features ........................................................................................................................................ 43 Block Diagram ............................................................................................................................... 43 Register Description (base: 0x1000_0500) ................................................................................... 43 3.8 UART LITE ................................................................................................................................................ 50 Features ........................................................................................................................................ 50 Block Diagram ............................................................................................................................... 50 Register Description (base: 0x1000_0c00) .................................................................................... 50 3.9 PROGRAMMABLE I/O .................................................................................................................................. 56 Features ........................................................................................................................................ 56 Block Diagram ............................................................................................................................... 56 Register Description (base: 0x1000_0600) ................................................................................... 56 I2C CONTROLLER .................................................................................................................................... 62 Features ................................................................................................................................... 62 Block Diagram .......................................................................................................................... 62 3.9.1 3.9.2 3.9.3 3.5.1 3.5.2 3.5.3 3.6.1 3.7.1 3.7.2 3.7.3 3.8.1 3.8.2 3.8.3 3.10 3.10.1 3.10.2 DSRT5350_V1.0_112510 Form No.：QS-073-F02 Rev.：1 Kept by： DCC -2- Ret. Time： 5 Years Draft
    RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 3.12 3.13 3.14 3.16 3.10.3 3.10.4 3.11 3.13.1 3.13.2 3.13.3 3.14.1 3.14.2 3.14.3 3.14.4 3.15.1 3.15.2 3.15.3 3.15.4 3.11.1 3.11.2 3.11.3 3.11.4 3.12.1 3.12.2 3.12.3 3.12.4 Register Description (base: 0x1000_0900) ............................................................................... 62 Programming Description ........................................................................................................ 66 PCM CONTROLLER ................................................................................................................................. 68 Features ................................................................................................................................... 68 Block Diagram .......................................................................................................................... 68 Register Description (base: 0x1000_2000) ............................................................................... 69 An Example of PCM Configuration ........................................................................................... 75 GENERIC DMA CONTROLLER .................................................................................................................... 77 Features ................................................................................................................................... 77 Block Diagram .......................................................................................................................... 77 Peripheral Channel Connection ................................................................................................ 77 Register Description (base: 0x1000_2800) ............................................................................... 78 SPI CONTROLLER .................................................................................................................................... 82 Features ................................................................................................................................... 82 Block Diagram .......................................................................................................................... 82 Register Description (base: 0x1000_0b00) ............................................................................... 82 I2S CONTROLLER .................................................................................................................................... 88 Features ................................................................................................................................... 88 Block Diagram .......................................................................................................................... 88 I2S Signal Timing for I2S Data Format ....................................................................................... 88 Register Description of I2S (base: 0x1000_0a00) ..................................................................... 89 3.15 MEMORY CONTROLLER ............................................................................................................................ 92 Features ................................................................................................................................... 92 Block Diagram .......................................................................................................................... 92 SDRAM Initialization Sequence ................................................................................................ 92 Register Description (base: 0x1000_0300) ............................................................................... 93 USB HOST CONTROLLER & PHY ............................................................................................................... 97 Features ................................................................................................................................... 97 Block Diagram .......................................................................................................................... 97 Register Description (base: 0x101c_0000) ............................................................................... 97 EHCI Operation register (base: 0x101c_0000) ......................................................................... 97 OHCI Operation register (base: 0x101c_1000) ......................................................................... 99 USB DEVICE CONTROLLER...................................................................................................................... 100 Features ................................................................................................................................. 100 PDMA Descriptor Format .................................................................................................................. 100 Bulk-out Aggregation Format ............................................................................................................ 101 Register Description (base: 0x1012_0000) ............................................................................. 102 USB Control Registers ....................................................................................................................... 102 UDMA Registers ................................................................................................................................ 102 PDMA Registers ................................................................................................................................ 102 FRAME ENGINE .................................................................................................................................... 108 Features ................................................................................................................................. 108 Block Diagram ........................................................................................................................ 108 PDMA FIFO-like Ring Concept ........................................................................................................... 109 PDMA Descriptor Format .................................................................................................................. 110 PDMA Register Description (base: 0x1010_0800) .................................................................. 110 SDM Register Description (base: 0x1010_0c00) .................................................................... 115 ETHERNET SWITCH ................................................................................................................................ 120 Features ................................................................................................................................. 120 Block Diagram ........................................................................................................................ 121 Frame Classification ............................................................................................................... 121 Register Description (base: 0x1011_0000) ............................................................................. 122 MII Control Register ............................................................................................................... 156 Function Description .............................................................................................................. 160 Flow Control Settings ........................................................................................................................ 160 VID and Tagging ................................................................................................................................ 160 VID and VLAN Member Set ............................................................................................................... 160 3.19.1 3.19.2 3.19.3 3.19.4 3.19.5 3.19.6 3.16.1 3.16.2 3.16.3 3.16.4 3.16.5 3.17.2.1 3.17.2.2 3.17.2.3 3.19.6.1 3.19.6.2 3.19.6.3 3.17.1.1 3.17.1.2 3.17.2 3.18.3 3.18.4 3.19 3.18 3.18.1 3.18.2 3.17 3.17.1 3.18.2.1 3.18.2.2 DSRT5350_V1.0_112510 Form No.：QS-073-F02 Rev.：1 Kept by： DCC -3- Ret. Time： 5 Years Draft
    RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 3.19.6.4 3.19.6.5 3.20 3.20.1 3.20.2 3.20.3 3.20.3.1 3.20.3.2 3.20.3.3 3.20.3.4 3.20.3.5 3.20.3.6 3.20.3.7 3.20.3.8 3.20.3.9 3.20.3.10 Packet Classification, QoS, Scheduling and Buffer Control ............................................................... 162 Spanning Tree Protocol ..................................................................................................................... 163 802.11N 1T1R MAC/BBP ................................................................................................................... 165 Features ................................................................................................................................. 165 Block Diagram ........................................................................................................................ 165 Register Description - SCH/WPDMA (base: 0x1018_0000) .................................................... 166 Register Description - PBF (base: 0x1018_0000) .............................................................................. 172 Register Description – RF TEST (base: 0x1018_0000) ....................................................................... 177 Register Description - MAC (base: 0x1018_0000) ............................................................................. 178 MAC Tx Configuration Registers (offset: 0x1300) ............................................................................. 186 MAC Rx Configuration Registers ....................................................................................................... 197 MAC Security Configuration Registers .............................................................................................. 199 MAC HCCA/PSMP CSR ....................................................................................................................... 199 MAC Statistics Counters .................................................................................................................... 201 MAC Search Table (base: 0x1018_0000, offset: 0x1800) .................................................................. 203 Security table/CIS/Beacon/NULL frame (base : 1018_0000, offset: 0x4000) .................................... 204 Security Key Format (8DW) .................................................................................................... 204 IV/EIV Format (2 DW) ............................................................................................................. 204 WCID Attribute Entry Format (1DW) ...................................................................................... 204 Shared Key Mode Entry Format (1DW) .................................................................................. 205 Security Tables .................................................................................................................................. 205 Descriptor and Wireless information ..................................................................................... 207 Tx Frame Information ....................................................................................................................... 207 Tx Descriptor Format ........................................................................................................................ 207 TXWI Format ..................................................................................................................................... 209 Rx Descriptor Ring ............................................................................................................................. 210 RX Descriptor Format ........................................................................................................................ 211 RXWI Format ..................................................................................................................................... 212 Brief PHY Rate Format and Definition ............................................................................................... 212 Driver Implementation Note .................................................................................................. 214 Instructions for Downloading 8051 Firmware .................................................................................. 214 Instructions for Initializing DMA ....................................................................................................... 214 Instructions for Clock Control ........................................................................................................... 214 Instructions for Tx/Rx Control ........................................................................................................... 215 Instructions for RF Power on/off Sequence ...................................................................................... 215 Power Saving Procedure ................................................................................................................... 216 Power Recovery Procedure ............................................................................................................... 216 Parameters ........................................................................................................................................ 216 3.20.7.1 3.20.8.1 3.20.8.2 3.20.8.3 3.20.8.4 3.20.8.5 3.20.8.6 3.20.8.7 3.20.9.1 3.20.9.2 3.20.9.3 3.20.9.4 3.20.9.5 3.20.9.6 3.20.9.7 3.20.9.8 3.20.4 3.20.5 3.20.6 3.20.7 3.20.8 3.20.9 4 PACKAGING PHYSICAL DIMENSIONS ......................................................................................................... 217 4.1 TFBGA 196B（12×12×0.94 MM） ......................................................................................................... 217 5 REVISION HISTORY .................................................................................................................................... 219 DSRT5350_V1.0_112510 Form No.：QS-073-F02 Rev.：1 Kept by： DCC -4- Ret. Time： 5 Years Draft
    RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 Table of Figures FIGURE 2-1 SDRAM INTERFACE .................................................................................................................................. 16 FIGURE 2-2 POWER-ON SEQUENCE .............................................................................................................................. 17 FIGURE 3-1 RT5350 BLOCK DIAGRAM ......................................................................................................................... 18 FIGURE 3-2 MIPS 24KEC PROCESSOR DIAGRAM ............................................................................................................ 21 FIGURE 3-3 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 22 FIGURE 3-4 TIMER BLOCK DIAGRAM ............................................................................................................................. 33 FIGURE 3-5 INTERRUPT CONTROLLER BLOCK DIAGRAM .................................................................................................... 37 FIGURE 3-6 UART BLOCK DIAGRAM ............................................................................................................................. 43 FIGURE 3-7 UART LITE BLOCK DIAGRAM ...................................................................................................................... 50 FIGURE 3-8 PROGRAM I/O BLOCK DIAGRAM .................................................................................................................. 56 FIGURE 3-9 1 I2C CONTROLLER BLOCK DIAGRAM ............................................................................................................ 62 FIGURE 3-10 PCM CONFIGURATION EXAMPLE 1 ............................................................................................................ 75 FIGURE 3-11 PCM CONFIGURATION EXAMPLE 2 ............................................................................................................ 76 FIGURE 3-12 PCM CONFIGURATION EXAMPLE 3 ............................................................................................................ 76 FIGURE 3-13 GENERIC DMA CONTROLLER BLOCK DIAGRAM ............................................................................................. 77 FIGURE 3-14 SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................ 82 FIGURE 3-15 WAVEFORM OF SPI INTERFACE .................................................................................................................. 87 FIGURE 3-16 I2S TRANSMITTER BLOCK DIAGRAM ............................................................................................................ 88 FIGURE 3-17 I2S TRANSMITTER/RECEIVER ..................................................................................................................... 88 FIGURE 3-18 SRAM/SDRAM CONTROLLER BLOCK DIAGRAM .......................................................................................... 92 FIGURE 3-19 USB HOST CONTROLLER & PHY BLOCK DIAGRAM ........................................................................................ 97 FIGURE 3-20 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 100 FIGURE 3-21 PDMA RX DESCRIPTOR FORMAT ............................................................................................................. 101 FIGURE 3-22 BULK-OUT AGGREGATION FORMAT .......................................................................................................... 101 FIGURE 3-23 FRAME ENGINE BLOCK DIAGRAM ............................................................................................................. 108 FIGURE 3-24 PDMA FIFO-LIKE RING CONCEPT ........................................................................................................... 109 FIGURE 3-25 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 110 FIGURE 3-26 PDMA RX DESCRIPTOR FORMAT ............................................................................................................. 110 FIGURE 3-27 ETHERNET SWITCH BLOCK DIAGRAM ........................................................................................................ 121 FIGURE 3-28 DOUBLE TAG ........................................................................................................................................ 161 FIGURE 3-29 SPECIAL TAG ........................................................................................................................................ 161 FIGURE 3-30 PACKET CLASSIFICATION, QOS, SCHEDULING, AND BUFFER CONTROL ............................................................. 163 FIGURE 3-31 802.11N 1T1R MAC/BBP BLOCK DIAGRAM ........................................................................................... 165 FIGURE 3-32 802.11N 3T3R MAC/BBP REGISTER MAP ............................................................................................. 166 FIGURE 3-33 TX FRAME INFORMATION ....................................................................................................................... 207 FIGURE 3-34 TX DESCRIPTOR FORMAT ........................................................................................................................ 208 FIGURE 3-35 TXWI FORMAT .................................................................................................................................... 209 FIGURE 3-36 RX DESCRIPTOR RING ............................................................................................................................ 210 FIGURE 3-37 RX DESCRIPTOR FORMAT ........................................................................................................................ 211 FIGURE 3-38 RXWI FORMAT .................................................................................................................................... 212 DSRT5350_V1.0_112510 Form No.：QS-073-F02 Rev.：1 Kept by： DCC -5- Ret. Time： 5 Years Draft
    RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 1 Pin Description 1.1 196-Pin BGA Package Diagram Table 1-1 196-Pin BGA Package Diagram Top View (left portion) Table 1-2 196-Pin BGA Package Diagram Top View (right portion) 1.2 Pin Description Table 1-3 Pin Description Pin JTAG interfaces: 5 pins A11 A12 A13 A14 B11 UART Lite interface: 2 pins P3 N2 UART Full interface: 8 pins N3 M3 K4 L3 DSRT5350_V1.0_112510 Form No.：QS-073-F02 Name I/O/IPU/IPD Driving Description JTAG_TRST_N JTAG_TCLK JTAG_TMS JTAG_TDI JTAG_TDO RXD2 TXD2 RXD RIN CTS_N DSR_N I, IPU I, IPD I, IPD I, IPD O, IPD I, IPD O, IPD I, IPD I, IPD I, IPD I, IPD 4 mA 4 mA 4 mA 4 mA 4 mA JTAG TRST (active low) JTAG TCLK JTAG TMS JTAG TDI JTAG TDO 4 mA 4 mA UART Lite RXD UART Lite TXD 4 mA 4 mA 4 mA 4 mA UART RXD. UART RIN. UART CTS_N. UART DSR_N. Rev.：1 Kept by： DCC -6- Ret. Time： 5 Years Draft
    Name DCD_N TXD DTR_N RTS_N SPI_MISO SPI_MOSI SPI_CLK SPI_CS0 SPI_CS1 I2C_SCLK I2C_SD RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 I/O/IPU/IPD Driving I, IPD O, IPD O, IPD O, IPD 4 mA 4 mA 4 mA 4 mA Description UART DCD_N. UART TXD. UART DTR. UART RTS. I, IPD O, IPD O, IPD O, IPD O, IPD I/O, IPU O, IPU 4 mA 4 mA 4 mA 4 mA 4 mA 8 mA 8 mA SPI Master In Slave Out SPI Master Out Slave In SPI Clock SPI Chip Select 0 SPI Chip Select 1 I2C Clock I2C Data GPIO0 I/O, IPD 8 mA GPIO0 Pin J4 K2 N4 P2 SPI/EEPROM interface: 5 pins M2 J3 N1 P1 L2 I2C interface: 2 pins B14 B13 GPIO interface: 1 pins B12 5-Port PHY: 26 pins K3 L1 L4 M1 M4 P4 L5 M5 N5 P5 L6 M6 N6 P6 N7 P7 M7 L7 M8 L8 N8 P8 N9 EPHY_LED0_N O, IPD EPHY_LED1_N O, IPD EPHY_LED2_N O, IPD EPHY_LED3_N O, IPD EPHY_LED4_N O, IPD 4 mA 4 mA 4 mA 4 mA 4 mA EPHY_REF_RES EPHY_RXN_P0 EPHY_RXP_P0 EPHY_TXN_P0 EPHY_TXP_P0 EPHY_RXN_P1 EPHY_RXP_P1 EPHY_TXN_P1 EPHY_TXP_P1 EPHY_RXN_P2 EPHY_RXP_P2 EPHY_TXN_P2 EPHY_TXP_P2 EPHY_RXN_P3 EPHY_RXP_P3 EPHY_TXN_P3 EPHY_TXP_P3 EPHY_RXN_P4 A I I O O I I O O I I O O I I O O I 10/100 Phy Port #0 Activity Led 10/100 PHY Port #1 Activity LED 10/100 PHY Port #2 Activity LED 10/100 PHY Port #3 Activity LED 10/100 PHY Port #4 Activity LED Connects to an external resistor to provide accurate bias current. 10/100 PHY Port #0 RXN 10/100 PHY Port #0 RXP 10/100 PHY Port #0 TXN 10/100 PHY Port #0 TXP 10/100 PHY Port #1 RXN 10/100 PHY Port #1 RXP 10/100 PHY Port #1 TXN 10/100 PHY Port #1 TXP 10/100 PHY Port #2 RXN 10/100 PHY Port #2 RXP 10/100 PHY Port #2 TXN 10/100 PHY Port #2 TXP 10/100 PHY Port #3 RXN 10/100 PHY Port #3 RXP 10/100 PHY Port #3 TXN 10/100 PHY Port #3 TXP 10/100 PHY Port #4 RXN DSRT5350_V1.0_112510 Form No.：QS-073-F02 Rev.：1 Kept by： DCC -7- Ret. Time： 5 Years Draft
    RT5350 Preliminary Datasheet PreliminaryDatNovember 25, 2010 Name EPHY_RXP_P4 EPHY_TXN_P4 EPHY_TXP_P4 I/O/IPU/IPD Driving I O O Description 10/100 PHY Port #4 RXP 10/100 PHY Port #4 TXN 10/100 PHY Port #4 TXP PORST_N WLAN_LED_N I, IPU O, IPD 2 mA 4 mA Power On Reset WLAN Activity LED UPHY0_VDDA_V33 A UPHY0_VDDL_V12 D P P UPHY0_VRES UPHY0_PADM UPHY0_PADP MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 4/8 mA 3.3 V USB PHY analog power supply 1.2 V USB PHY digital power supply Connects to an external 8.2K Ohm resistor for band-gap reference circuit. USB data pin Data- USB data pin Data+ SDRAM Data bit #15 SDRAM Data bit #14 SDRAM Data bit #13 SDRAM Data bit #12 SDRAM Data bit #11 SDRAM Data bit #10 SDRAM Data bit #9 SDRAM Data bit #8 SDRAM Data bit #7 SDRAM Data bit #6 SDRAM Data bit #5 SDRAM Data bit #4 SDRAM Data bit #3 SDRAM Data bit #2 SDRAM Data B bit it #1 SDRAM Data bit #0 SDRAM Address bit #12 SDRAM Address bit #11 SDRAM Address bit #10 SDRAM Address bit #9 SDRAM Address bit #8 SDRAM Address bit #7 SDRAM Address bit #6 SDRAM Address bit #5 SDRAM Address bit #4 SDRAM Address bit #3 SDRAM Address bit #2 SDRAM Address bit #1 Rev.：1 Kept by： DCC -8- Ret. Time： 5 Years Pin P9 M9 L9 Misc signals: 2 pins C10 K1 USB PHY interface: 5 pins N11 P13 P11 N12 P12 SDRAM Interface: 40 pins F14 G13 F13 G12 G11 E14 E13 F12 E12 F11 E11 D14 D13 D12 D11 E10 L13 K12 L14 J11 K13 K14 J12 J13 J14 H11 H12 H13 DSRT5350_V1.0_112510 Form No.：QS-073-F02 Draft
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