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DDR3 JEDEC标准.pdf
JEDEC
STANDARD
DDR3 SDRAM Specification
JESD79-3E
(Revision of JESD79-3D, August 2009)
July 2010
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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JEDEC Standard No. 79-3E
Contents
1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
2.2 DDR3 SDRAM x8 Ballout using MO-207........................................................................4
2.3 DDR3 SDRAM x16 Ballout using MO-207......................................................................5
2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207..........................................6
2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207..........................................7
2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207........................................8
2.7 Quad-stacked / Quad-die DDR3 SDRAM x4 Ballout using MO-207...............................9
2.8 Quad-stacked / Quad-die DDR3 SDRAM x8 Ballout using MO-207.............................10
2.9 Quad-stacked / Quad-die DDR3 SDRAM x16 Ballout using MO-207...........................11
2.10 Pinout Description..........................................................................................................13
2.11 DDR3 SDRAM Addressing...........................................................................................15
2.11.1 512Mb ....................................................................................................................15
2.11.2 1Gb..........................................................................................................................15
2.11.3 2Gb .........................................................................................................................15
2.11.4 4Gb .........................................................................................................................15
2.11.5 8Gb .........................................................................................................................16
3 Functional Description.............................................................................................................17
3.1 Simplified State Diagram.................................................................................................17
3.2 Basic Functionality ..........................................................................................................18
3.3 RESET and Initialization Procedure................................................................................19
3.3.1 Power-up Initialization Sequence .............................................................................19
3.3.2 Reset Initialization with Stable Power......................................................................21
3.4 Register Definition...........................................................................................................22
3.4.1 Programming the Mode Registers ............................................................................22
3.4.2 Mode Register MR0..................................................................................................23
3.4.3 Mode Register MR1..................................................................................................27
3.4.4 Mode Register MR2..................................................................................................30
3.4.5 Mode Register MR3..................................................................................................32
4 DDR3 SDRAM Command Description and Operation...........................................................33
4.1 Command Truth Table.....................................................................................................33
4.2 CKE Truth Table..............................................................................................................35
4.3 No OPeration (NOP) Command ......................................................................................36
4.4 Deselect Command ..........................................................................................................36
4.5 DLL-off Mode..................................................................................................................37
4.6 DLL on/off switching procedure......................................................................................38
4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
4.7 Input clock frequency change ..........................................................................................40
4.8 Write Leveling .................................................................................................................42
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
4.8.2 Procedure Description...............................................................................................43
4.8.3 Write Leveling Mode Exit ........................................................................................45
i
JEDEC Standard No. 79-3E
Contents
4.9 Extended Temperature Usage ..........................................................................................46
4.9.1 Self-Refresh Temperature Range - SRT...................................................................46
4.10 Multi Purpose Register...................................................................................................48
4.10.1 MPR Functional Description ..................................................................................49
4.10.2 MPR Register Address Definition ..........................................................................50
4.10.3 Relevant Timing Parameters...................................................................................50
4.10.4 Protocol Example....................................................................................................50
4.11 ACTIVE Command .......................................................................................................55
4.12 PRECHARGE Command ..............................................................................................55
4.13 READ Operation............................................................................................................56
4.13.1 READ Burst Operation...........................................................................................56
4.13.2 READ Timing Definitions
57
4.13.3 Burst Read Operation followed by a Precharge......................................................66
4.14 WRITE Operation..........................................................................................................68
4.14.1 DDR3 Burst Operation ...........................................................................................68
4.14.2 WRITE Timing Violations .....................................................................................68
4.14.3 Write Data Mask.....................................................................................................69
4.14.4 tWPRE Calculation.................................................................................................70
4.14.5 tWPST Calculation .................................................................................................70
4.15 Refresh Command..........................................................................................................77
4.16 Self-Refresh Operation ..................................................................................................79
4.17 Power-Down Modes ......................................................................................................81
4.17.1 Power-Down Entry and Exit...................................................................................81
4.17.2 Power-Down clarifications - Case 1 .......................................................................86
4.17.3 Power-Down clarifications - Case 2 .......................................................................87
4.17.4 Power-Down clarifications - Case 3 .......................................................................88
4.18 ZQ Calibration Commands ............................................................................................89
4.18.1 ZQ Calibration Description.....................................................................................89
4.18.2 ZQ Calibration Timing ...........................................................................................90
4.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading ...........................90
5 On-Die Termination (ODT).....................................................................................................91
5.1 ODT Mode Register and ODT Truth Table.....................................................................91
5.2 Synchronous ODT Mode .................................................................................................92
5.2.1 ODT Latency and Posted ODT.................................................................................92
5.2.2 Timing Parameters....................................................................................................92
5.2.3 ODT during Reads ....................................................................................................94
5.3 Dynamic ODT..................................................................................................................96
5.3.1 Functional Description:.............................................................................................96
5.3.2 ODT Timing Diagrams.............................................................................................97
5.4 Asynchronous ODT Mode.............................................................................................102
5.4.1 Synchronous to Asynchronous ODT Mode Transitions.........................................103
5.4.2 Synchronous to Asynchronous ODT Mode Transition during
Power-Down Entry .................................................................................................103
5.4.3 Asynchronous to Synchronous ODT Mode Transition during
Power-Down Exit ...................................................................................................106
ii
JEDEC Standard No. 79-3E
Contents
5.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and
short CKE low periods............................................................................................107
6 Absolute Maximum Ratings ..................................................................................................109
6.1 Absolute Maximum DC Ratings....................................................................................109
6.2 DRAM Component Operating Temperature Range ......................................................109
7 AC & DC Operating Conditions............................................................................................111
7.1 Recommended DC Operating Conditions......................................................................111
8 AC and DC Input Measurement Levels.................................................................................113
8.1 AC and DC Logic Input Levels for Single-Ended Signals ............................................113
8.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals.........113
114
8.1.2 AC and DC Input Levels for Single-Ended Data Signals
8.2 Vref Tolerances..............................................................................................................115
8.3 AC and DC Logic Input Levels for Differential Signals ...............................................116
8.3.1 Differential signal definition...................................................................................116
8.3.2 Differential swing requirements for clock (CK - CK#) and strobe
(DQS - DQS#) ........................................................................................................116
8.3.3 Single-ended requirements for differential signals.................................................117
8.4 Differential Input Cross Point Voltage ..........................................................................118
8.5 Slew Rate Definitions for Single-Ended Input Signals..................................................120
8.6 Slew Rate Definitions for Differential Input Signals.....................................................120
9 AC and DC Output Measurement Levels ..............................................................................122
9.1 Single Ended AC and DC Output Levels.......................................................................122
9.2 Differential AC and DC Output Levels .........................................................................122
9.3 Single Ended Output Slew Rate.....................................................................................123
9.4 Differential Output Slew Rate........................................................................................124
9.5 Reference Load for AC Timing and Output Slew Rate .................................................125
9.6 Overshoot and Undershoot Specifications.....................................................................126
9.6.1 Address and Control Overshoot and Undershoot Specifications............................126
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications.............127
9.7 34 ohm Output Driver DC Electrical Characteristics ....................................................128
9.7.1 Output Driver Temperature and Voltage sensitivity...............................................129
9.8 On-Die Termination (ODT) Levels and I-V Characteristics .........................................131
9.8.1 On-Die Termination (ODT) Levels and I-V Characteristics ..................................131
9.8.2 ODT DC Electrical Characteristics.........................................................................132
9.8.3 ODT Temperature and Voltage sensitivity.............................................................135
9.9 ODT Timing Definitions................................................................................................135
9.9.1 Test Load for ODT Timings ...................................................................................135
9.9.2 ODT Timing Definitions.........................................................................................136
10 IDD and IDDQ Specification Parameters and Test Conditions...........................................140
10.1 IDD and IDDQ Measurement Conditions ...................................................................140
10.2 IDD Specifications.......................................................................................................151
11 Input/Output Capacitance ....................................................................................................154
11.1 Input/Output Capacitance ............................................................................................154
iii
JEDEC Standard No. 79-3E
Contents
12 Electrical Characteristics & AC Timing for DDR3-800 to DDR3-2133.............................157
12.1 Clock Specification......................................................................................................157
12.1.1 Definition for tCK(avg) ........................................................................................157
12.1.2 Definition for tCK(abs).........................................................................................157
12.1.3 Definition for tCH(avg) and tCL(avg)..................................................................157
12.1.4 Definition for tJIT(per) and tJIT(per,lck) .............................................................157
12.1.5 Definition for tJIT(cc) and tJIT(cc,lck) ................................................................158
12.1.6 Definition for tERR(nper).....................................................................................158
12.2 Refresh parameters by device density..........................................................................158
12.3 Standard Speed Bins ....................................................................................................159
167
13 Electrical Characteristics and AC Timing ...........................................................................169
13.1 Timing Parameters for DDR3-800, DDR3-1067, DDR3-1333, and DDR3-1600.......169
13.2 Timing Paramters for DDR3-1866 and DDR3-2133 Speed Bins................................176
13.3 Jitter Notes ...................................................................................................................181
13.4 Timing Parameter Notes ..............................................................................................182
13.5 Address / Command Setup, Hold and Derating...........................................................184
13.6 Data Setup, Hold and Slew Rate Derating...................................................................192
12.3.1 Speed Bin Table Notes
iv
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