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CCIX_Base_Specification_Revision1.1_Version1.0.pdf
Chapter 1. Document Overview
1.1 Specification Objective
1.2 Terms and Acronyms
1.3 Reference Documents
Chapter 2. CCIX Overview
2.1 Introduction
2.2 Topologies
2.3 CCIX Architecture Model
2.3.1 Components of the CCIX Architecture
2.3.2 Port Aggregation
2.3.3 CCIX Extended Data Rate Physical Layer
2.4 CCIX Management Framework
2.5 RAS Architecture
2.6 Address Translation Service
2.7 Signaling Hosts from Accelerators
2.8 Establishing Trust with a CCIX Accelerator
Chapter 3. Protocol Layer
3.1 Introduction
3.1.1 CCIX Agents
3.1.2 Discovery and Enumeration
3.1.3 Topologies
3.1.3.1 Fully Connected
3.1.3.2 Tree
3.1.3.3 Multi-Dimensional Array
3.2 Message Fields
3.2.1 Request Message
3.2.2 Snoop Message
3.2.3 Response Message
3.2.4 Field Descriptions
3.3 Coherence protocol
3.3.1 Cache States
3.3.2 Request Types
3.3.2.1 Read Transactions
3.3.2.2 Dataless Transactions
3.3.2.3 Write Transactions
3.3.2.4 Atomic Transactions
3.3.2.5 ReqOp Encoding
3.3.3 Request Responses
3.3.3.1 ReqRespOp Encoding
3.3.4 Snoop Requests
3.3.4.1 Snoop Data Return
3.3.4.2 SnpOp Encoding
3.3.5 Snoop Responses
3.3.5.1 SnpRespOp encoding
3.3.5.2 Snoop Response for Unique Clean and Unique Dirty states
3.3.6 MiscOp Encoding
3.3.7 Protocol Error Report
3.3.8 Request Cache State Transitions
3.3.9 State Transitions at Snoopee
3.3.10 Silent Cache State Transitions
3.3.11 Controlling the use of Evict and WriteEvictFull transactions
3.3.12 Simultaneous Outstanding Requests
3.3.13 Request to Snoop Hazard
3.3.13.1 At the Port Interface Labeled CCIX-R
3.3.13.2 At the Port Interface labeled CCIX-H
3.3.13.3 WriteBackPtlUD Request Hazard
3.4 Transaction Structure
3.4.1 Request Transactions
3.4.1.1 Fully Coherent Read Transactions
3.4.1.2 Non-coherent and IO Coherent Read Transactions
3.4.1.3 Dataless Transactions without CompAck
3.4.1.4 Dataless Transactions with CompAck
3.4.1.5 Write Transactions
3.4.1.6 Atomic Transactions
3.4.2 Snoop Transactions
3.4.2.1 Snoop without Data response
3.4.2.2 Snoop with Data Response
3.4.2.3 Misc Transactions
3.5 Address, Control, and Data
3.5.1 Address and Data Alignment
3.5.2 Request Attributes
3.5.2.1 Device
3.5.2.2 Normal Memory
3.5.3 Permitted Memory Type for Requests
3.5.4 Data and Byte Enables
3.5.4.1 Data Fields
3.5.4.2 Normal Memory
3.5.4.3 Device
3.5.4.4 Data Location Examples
3.5.4.5 Byte Enables
3.6 Ordering
3.6.1 Multi-copy Atomicity
3.6.2 Completion Response and Ordering
3.6.3 CompAck
3.6.4 Comp and Outstanding CompAck Dependency
3.7 Flow control and protocol credits
3.7.1 Protocol Credits
3.7.2 Credit Exchange
3.7.2.1 Independent Credit Exchange
3.7.2.2 Packet Header Credit Grant
3.7.2.3 Credit Exchange Rules
3.7.2.4 Agent IDs in Credit Exchange Messages
3.8 Miscellaneous Messages
3.8.1 Uncredited Misc Messages
3.8.2 Credited Misc Messages
3.8.3 ID Namespace
3.8.4 Extension Fields in Misc Message
3.9 Error Handling
3.9.1 Error Classification
3.10 Packet Header
3.10.1 Packet Header
3.10.1.1 PCIe Compatible Header
3.10.1.2 Optimized Header
3.10.1.3 Packet Header Length field
3.10.2 Message Packing
3.10.2.1 Message Packing Enable
3.10.2.2 Maximum Packet Size
3.10.2.3 Combining Properties for Multiple Interfaces
3.11 Message Formats
3.11.1 Read Request
3.11.2 Write Request
3.11.3 Response without Data
3.11.4 Response with Data
3.11.5 Snoop
3.11.6 Miscellaneous Message type
3.11.6.1 Credited Misc message
3.11.6.2 Uncredited Misc message
3.11.6.3 Credit Exchange
3.11.6.4 NOP Message
3.11.6.5 PER Message
3.11.7 Request Chaining
3.11.8 Snoop Chaining
3.11.9 Extension fields
3.11.9.1 Extension Type 0 – Additional Information
3.12 Optional Features and Parameters
3.12.1 CompAck Removal
3.12.2 Partial Cache States
3.12.3 Cache Line Size
3.12.4 Address Width
3.12.5 Packet Header
3.12.6 Message Packing Enable
3.12.7 Maximum Packet Size
3.12.8 Summary of Properties
3.13 Message Routing and Agent ID Assignment
3.13.1 Message Routing
3.13.1.1 Address Routed Messages
3.13.1.2 TgtID Assignment
3.13.1.3 ID Routed Messages
3.13.2 Broadcast Snoop Routing
3.13.2.1 Broadcast Snoop Forwarding
3.13.3 TxnID Assignment
3.13.4 Agent ID
3.13.5 Target ID Determination
3.13.6 Agent ID assignment Summary
3.14 Memory Expansion
3.14.1 Concurrent Memory Expansion
3.15 Port Aggregation
3.15.1 Port Aggregation Routing
3.16 Terminology
3.17 Transaction Flow Examples
3.17.1 Read Request with End-to-End CompAck
3.17.2 Read Request with an Early CompAck
3.17.3 Write Request
Chapter 4. CCIX Transport Layer
4.1 Introduction
4.1.1 CCIX Transaction Layer
4.1.2 PCIe Transaction Layer
4.1.3 PCIe Data Link Layer
4.1.4 CCIX Physical Layer
4.2 Transaction Layer
4.2.1 CCIX Transaction Layer Architecture
4.2.2 Transaction Layer Protocol - Packet Definition
4.2.2.1 CCIX Transaction Layer Packets
4.2.2.1.1 PCIe Compatible TLP Format
4.2.2.1.2 Optimized TLP format
4.2.2.2 Support for Multiple Protocol Messages in one CCIX TLP
4.2.2.3 Use of PCIe Compatible or Optimized TLP formats
4.2.3 CCIX Virtual Channel
4.2.4 Handling of Received TLPs
4.2.5 Transaction Ordering Rules
4.2.6 Virtual Channel (VC) Mechanism
4.2.7 Transaction Layer Flow Control
4.2.8 Data Integrity
4.2.9 Completion Timeout Mechanism
4.2.10 Link Status Dependencies
4.3 CCIX Data Link Layer
4.3.1 REPLAY_TIMER Limits for 20.0 GT/s and 25.0 GT/s
4.3.2 AckNak_LATENCY_TIMER Limits for 20.0 GT/s and 25.0 GT/s
4.4 CCIX Physical Layer Logical Block
4.4.1 Introduction
4.4.2 CCIX Logical Sub-block
4.4.2.1 CCIX Extended Speed Mode (ESM)
4.4.2.2 CCIX PHY Types
4.4.2.3 ESM Operation
4.4.2.3.1 ESM Operational Mechanisms
4.4.2.3.2 ESM Operation Example
4.4.2.3.2.1 Initial Link-Up to 25.0 GT/s ESM Operation
4.4.3 Retimers
Chapter 5. Electrical PHY Layer
5.1 Introduction
5.2 EDR25-SR Electrical Specification
5.2.1 General Specification
5.2.1.1 Line Rate
5.2.1.2 Line Coding
5.2.1.3 Crosstalk
5.2.1.4 Baud Rate Tolerance
5.2.1.5 AC Coupling Capacitor
5.2.1.6 Target Bit Error Rate
5.2.1.7 Reference Model
5.2.2 Transmitter Specification
5.2.2.1 Driver Termination
5.2.2.2 Differential Return Loss of Transmitter
5.2.2.3 Common Mode Output Return Loss
5.2.2.4 Transmitter PLL Bandwidth and Peaking
5.2.2.5 TX Voltage Parameters
5.2.2.5.1 Signal Definition
5.2.2.5.2 Transmitter AC Specification
5.2.2.5.3 Transmitter Equalization
5.2.2.5.4 TX Equalization Presets
5.2.2.5.5 Measuring Presets at EDR25-SR PHY
5.2.2.5.6 EIEOS and VTX-EIEOS-FS and VTX-EIEOS-RS Limit
5.2.2.6 TX Timing Parameters
5.2.2.6.1 Jitter Parameters
5.2.2.6.2 De-Embedding the Breakout Channel for TX Jitter Measurement
5.2.2.6.3 Behavioral CDR Characteristics
5.2.3 Receiver Specification
5.2.3.1 Receiver Termination
5.2.3.2 Differential Return Loss of Receiver
5.2.3.3 Common Return Loss of Receiver
5.2.3.4 Common Receiver Parameters
5.2.3.5 Jitter Tolerance
5.2.3.6 Receiver Stressed Eye Specification
5.2.3.6.1 Breakout and Replica Channels
5.2.3.6.2 Calibration Channel Insertion Loss Characteristics
5.2.3.6.3 Post Processing Procedures
5.2.3.6.4 Behavioral Rx Package Models
5.2.3.6.5 Behavioral CDR Model
5.2.3.6.6 Behavioral CTLE
5.2.3.6.7 Behavioral DFE
5.2.3.7 Calibration Stress Eye for Jitter Tolerance
5.2.3.7.1 Procedure to Calibrate Stressed Eye
5.2.3.7.2 Procedure for Testing Rx DUT
5.2.3.7.3 Waveform Post Processing Tool Requirements
5.2.3.8 Receiver Refclk Modes
5.2.4 PCIe-Specific Specifications
5.2.4.1 Electrical Idle
5.2.4.2 Receiver Detection
5.2.4.3 Receiver Margining
5.2.4.4 Link Training for TX EQ with Back Channel
5.2.5 Reference Clock Specification
5.2.5.1 Reference Clock Electrical Specification
5.2.5.2 Reference Clock Compliance Measurement
5.2.5.3 CDR and PLL Bandwidth and Peaking for Reference Clock Compliance
5.2.6 Channel Compliance
5.2.6.1 Channel Compliance Methodology
5.2.6.1.1 Using Internal EW/EH with reference receiver
5.2.6.1.2 Behavioral CTLE
5.2.6.1.3 Behavioral Transmitter and Receiver Package Models (Informative)
5.2.6.1.4 Behavior Transmitter Parameters
5.2.6.2 Frequency Domain Response for Channel Compliance (Informative)
5.2.6.2.1 Insertion Loss Between Reference Point Tdie and Rdie (Informative)
5.2.6.2.2 Differential Return Loss of Channel (Informative)
5.2.6.2.3 Insertion Loss Deviation (Informative)
5.2.6.2.4 Integrated Crosstalk Noise (Informative)
5.3 EDR25-LR Electrical Specification
5.3.1 General Specification
5.3.1.1 Line Rate
5.3.1.2 Line Coding
5.3.1.3 Crosstalk
5.3.1.4 Baud Rate Tolerance
5.3.1.5 AC Coupling Capacitor
5.3.1.6 Target Bit Error Rate
5.3.1.7 Reference Model
5.3.2 Transmitter Specification
5.3.2.1 Driver Termination
5.3.2.2 Differential Return Loss of Transmitter
5.3.2.3 Common Mode Output Return Loss
5.3.2.4 Transmitter PLL Bandwidth and Peaking
5.3.2.5 TX Voltage Parameters
5.3.2.5.1 Signal Definition
5.3.2.5.2 Transmitter AC Specification
5.3.2.5.3 Transmitter Equalization
5.3.2.5.4 TX Equalization Presets
5.3.2.5.5 Measuring Presets at EDR25-LR PHY
5.3.2.5.6 EIEOS and VTX-EIEOS-FS and VTX-EIEOS-RS Limit
5.3.2.6 TX Timing Parameters
5.3.2.6.1 Jitter Parameters
5.3.2.6.2 De-Embedding the Breakout Channel for TX Jitter Measurement
5.3.2.6.3 Behavioral CDR Characteristics
5.3.3 Receiver Specification
5.3.3.1 Receiver Termination
5.3.3.2 Differential Return Loss of Receiver
5.3.3.3 Common Return Loss of Receiver
5.3.3.4 Common Receiver Parameters
5.3.3.5 Jitter Tolerance
5.3.3.6 Receiver Stressed Eye Specification
5.3.3.6.1 Breakout and Replica Channels
5.3.3.6.2 Calibration Channel Insertion Loss Characteristics
5.3.3.6.3 Post Processing Procedures
5.3.3.6.4 Behavioral Rx Package Models
5.3.3.6.5 Behavioral CDR Model
5.3.3.6.6 Behavioral CTLE
5.3.3.6.7 Behavioral DFE
5.3.3.7 Calibration Stress Eye for Jitter Tolerance
5.3.3.7.1 Procedure to Calibrate Stressed Eye
5.3.3.7.2 Procedure for Testing Rx DUT
5.3.3.7.3 Waveform Post Processing Tool Requirements
5.3.3.8 Receiver Refclk Modes
5.3.4 PCIe-Specific Specifications
5.3.4.1 Electrical Idle
5.3.4.2 Receiver Detection
5.3.4.3 Receiver Margining
5.3.4.4 Link Training for TX EQ with back channel
5.3.5 Reference Clock Specification
5.3.5.1 Reference Clock Electrical Specification
5.3.5.2 Reference Clock Compliance measurement
5.3.5.3 CDR and PLL Bandwidth and Peaking for Reference Clock Compliance
5.3.6 Channel Compliance
5.3.6.1 Channel Compliance Methodology
5.3.6.1.1 Using Internal EW/EH with reference receiver
5.3.6.1.2 Behavioral CTLE
5.3.6.1.3 Behavioral Transmitter and Receiver Package Models For LR (Informative)
5.3.6.1.4 Behavior Transmitter Parameters
5.3.6.2 Frequency Domain Response for Channel Compliance (Informative)
5.3.6.2.1 Insertion Loss between reference point Tdie and Rdie (Informative)
5.3.6.2.2 Differential Return Loss of Channel (Informative)
5.3.6.2.3 Insertion Loss Deviation (Informative)
5.3.6.2.4 Integrated Crosstalk Noise (Informative)
5.4 EDR32 Electrical Specification
Chapter 6. Protocol Layer and Transport Layer DVSEC
6.1 Overview
6.2 Protocol Layer DVSEC
6.2.1 Introduction to CCIX Protocol Layer DVSEC
6.2.1.1 Location of CCIX Protocol Layer DVSEC
6.2.1.2 PCIe Function Level Reset (FLR)
6.2.1.3 PCIe ARI and SR-IOV
6.2.1.4 CCIX Protocol Layer DVSEC Header
6.2.1.5 Sequence for Capabilities & Status and Control Structures
6.2.1.5.1 Sequence for Multiport CCIX Devices
6.2.1.6 Capabilities & Status Structure and Control Structure
6.2.1.7 Version Numbers and their impact on data structure definition
6.2.1.8 CCIX Topology creation via Address Space and CCIX AgentID name space allocation
6.2.1.8.1 Global ID Map (G-IDM)
6.2.1.8.2 Global RA-to-HA System Address Map (G-RSAM)
6.2.1.8.3 Global HA-to-SA System Address Map (G-HSAM)
6.2.1.8.4 CCIX Device view of G-IDM, G-RSAM, and G-HSAM
6.2.1.9 CCIX Component Address and ID based routing tables
6.2.2 CCIX Component Structures
6.2.2.1 Common Structures
6.2.2.1.1 Common Capabilities & Status Data Structures
6.2.2.1.2 Common Control Data Structures
6.2.2.1.2.1 Snoop Request Hash Mask
6.2.2.1.2.2 CCIX Software Services Portal
6.2.2.2 IDM Table Structure
6.2.2.2.1 IDM Table Usage by CCIX Components
6.2.2.2.2 Routing of Responses for CCIX AgentIDs with CCIX Port Aggregation
6.2.2.2.3 Routing of Snoop Requests for CCIX Devices with CCIX Port Aggregation
6.2.2.2.4 Routing of Snoop Responses for CCIX Devices that support Mesh Topologies
6.2.2.3 SAM Table Structure
6.2.2.3.1 Common SAM Entry
6.2.2.3.2 Hash Mask
6.2.2.3.3 Aggregated Port Selection Function
6.2.2.3.4 SAM Table Usage and Restrictions for CCIX Components
6.2.2.4 Memory Pool and BAT Structures
6.2.2.4.1 Memory Pool Capabilities & Status Structure
6.2.2.4.2 BAT Control Structure
6.2.2.4.2.1 BAT Base Address Type Control Entry
6.2.2.4.2.2 BAT Fixed Offset Type Control Entry
6.2.2.4.3 Relation between HA Memory Pool Structures and HBAT Entry Structures
6.2.2.5 CCIX Port Structures
6.2.2.5.1 CCIX Port Capabilities & Status Register
6.2.2.5.2 CCIX Port Control Register
6.2.2.5.3 PSAM Entry
6.2.2.6 CCIX Link Structures
6.2.2.6.1 CCIX Link Capabilities & Status Structure
6.2.2.6.2 CCIX Link Control Structure
6.2.2.6.2.1 CCIX Link Attribute Control Structure
6.2.2.6.2.1.1 Broadcast Forward Control Vector
6.2.2.6.2.2 CCIX Link TransportID Map Entry
6.2.2.7 Home Agent Structures
6.2.2.7.1 Home Agent Capabilities & Status Structure
6.2.2.7.2 Home Agent Control Structure
6.2.2.8 Request Agent Structures
6.2.2.8.1 Request Agent Capabilities & Status Structure
6.2.2.8.2 Request Agent Control Structure
6.2.2.9 Slave Agent Structures
6.2.2.9.1 Slave Agent Capabilities & Status Structure
6.2.2.9.2 Slave Agent Control Structure
6.2.2.10 AF Properties Stuctures
6.2.2.10.1 AF Properties Capabilities & Status Structure
6.2.2.10.1.1 RA Reference Index Structure
6.2.2.10.1.2 AF Reference Index Structure
6.2.2.10.1.3 AF to RA Binding Capability Structure
6.2.2.10.2 AF to RA Properties Control Structure
6.2.2.10.2.1 AF to RA Binding Control Entries
6.3 Transport DVSEC
6.3.1 CCIXTransportCapabilities Register
6.3.2 ESMMandatoryDataRateCapability Register
6.3.3 ESMOptionalDataRateCapability Register
6.3.4 ESMStatus Register
6.3.5 ESMControl Register
6.3.5.1 Rules for Programming ESM Fields
6.3.6 ESMLaneEqualizationControl Registers
6.3.7 TransportLayerCapabilities Register
6.3.8 TransportLayerControl Register
6.4 DVSEC Discovery and Configuration
6.5 CCIX Switch Referenced Data Structures
6.6 Examples to Illustrate Protocol Layer DVSEC Usage
6.6.1 Simple CCIX Topology and Relevant Data Structures
6.6.1.1 Simple CCIX Topology and Associated SAM and BAT Data Structures
6.6.2 Complex CCIX Topology and Relevant Data Structures
6.6.2.1 Complex Topology and Associated Number of SAM Entries
Chapter 7. CCIX RAS Overview
7.1 Classification of Hardware Faults
7.2 Hardware Error Propagation
7.3 CCIX Protocol Error Reporting (PER)
7.3.1 CCIX PER Message Format
7.3.2 CCIX PER Log Structures
7.3.2.1 CCIX PER Log Header
7.3.2.2 Overwrite / Overflow Rules in Multiple Error Scenarios
7.3.3 Memory Error Type Structure
7.3.4 Cache Error Type Structure
7.3.5 ATC Error Type Structure
7.3.6 Port Error Type Structure
7.3.7 CCIX Link Error Type Structure
7.3.8 Agent Internal Error Type Structure
7.3.9 Vendor-Specific Log Info
7.4 CCIX Error Control & Status Structures
7.4.1 Error Control Register Definitions
7.4.2 Device Error Control Flows
7.4.2.1 Error Masking Rules
7.4.2.2 Recommended Flow for Enabling Errors at Boot
7.4.2.3 Guidelines for Dynamic Error Mask Updates
Chapter 8. CCIX ATS Specification
8.1 Introduction
8.2 Address Translation Services
8.3 Invalidation Semantics
8.4 Memory Type Information
8.4.1 Memory Type
Cache Coherent Interconnect
for Accelerators
CCIX® Base Specification
Revision 1.1 Version 1.0
September 6, 2019
September 6, 2019 © 2016-2019 CCIX Consortium, Inc. ALL RIGHTS RESERVED. CONFIDENTIAL
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LEGAL NOTICE
© 2016-2019 CCIX CONSORTIUM, INC. ALL RIGHTS RESERVED.
This CCIX Base Specification Revision 1.1 Version 1.0 (this “document”) is proprietary to CCIX Consortium, Inc. (sometimes also
referred to as “Company”) and/or its successors and assigns.
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NOTICE TO USERS WHO ARE CCIX CONSORTIUM, INC. MEMBERS:
Members of CCIX Consortium, Inc. (“CCIX Member(s)”) may use and/or implement this CCIX Base Specification Revision 1.1
Version 1.0 subject, however, to the CCIX Member’s compliance with all of the terms and condition of the Company’s Intellectual
Property Policy, Bylaws, and all other Company policies and procedures (“CCIX Governing Documents”) and the CCIX Member’s
Participation Agreement.
Each CCIX Member hereby agrees that its use and/or implementation of this CCIX Base Specification Revision 1.1 Version 1.0 and/or
any of the specifications described herein are subject to the following additional terms and conditions:
(i) The Company takes no position regarding, and each CCIX Member is solely responsible for determining on its own, the existence,
validity, and/or scope of any intellectual property rights or any other rights (including without limitation any “Essential Claims”
under the Company’s Intellectual Property Policy) that any third party (including without limitation any other CCIX Member) may
own or otherwise hold which may (or may not) pertain to or cover any implementation or other use of this CCIX Base
Specification Revision 1.1 Version 1.0 or any specifications described herein.
(ii) Each CCIX Member is solely responsible for:
(a) determining whether any license or other consent (including without limitation any “FRAND License” under the Company’s
Intellectual Property Policy) from any third party (including without limitation from any other CCIX Member) is needed to
implement or otherwise use this CCIX Base Specification Revision 1.1 Version 1.0 or any of the specifications described
herein; and
(b) Negotiating and obtaining, for itself, any such license or other consent (including without limitation any “FRAND License”
under the Company’s Intellectual Property Policy) from any and all such third parties (including without limitation from other
CCIX Members).
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NOTICE TO NON-MEMBERS OF CCIX CONSORTIUM, INC.:
If you are not a CCIX Member and you have obtained a copy of this document, you only have a right to review this document or make
reference to or cite this document. Any such references or citations to this document must acknowledge CCIX Consortium’s Inc.’s
copyright ownership of this document. The proper copyright citation or reference is as follows: “©2016-2019 CCIX CONSORTIUM,
INC. ALL RIGHTS RESERVED.” When making any such citation or reference to this document you are not permitted to revise, alter,
modify, make any derivatives of, or otherwise amend the referenced portion of this document in any way without the prior express written
permission of CCIX Consortium, Inc. Nothing contained in this document shall be deemed as granting (either expressly or impliedly) to
any party that is not a CCIX Member: (ii) any kind of license to implement or use this document or any specifications described therein or
any of its contents, or any kind of license in or to any other intellectual property owned or controlled by CCIX Consortium, Inc., including
without limitation any trademarks of CCIX Consortium, Inc.; or (ii) any benefits and/or rights as a CCIX Member under any CCIX
Governing Documents.
If you are not a CCIX Member but still elect to implement this document or any of the specifications described herein, you are hereby
given further notice that your election to do so does not give you any of the rights and/or protections of CCIX Members, including without
limitation any of the rights and/or protections of CCIX Members under the Company’s Intellectual Property Policy or other CCIX
Governing Documents.
LEGAL DISCLAIMERS FOR ALL PARTIES:
THIS DOCUMENT AND ALL SPECIFICATIONS AND/OR OTHER CONTENT PROVIDED HEREIN IS PROVIDED ON AN “AS
IS” BASIS. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CCIX CONSORTIUM, INC. (ALONG WITH THE
CONTRIBUTORS TO THIS DOCUMENT) HEREBY DISCLAIM ALL REPRESENTATIONS, WARRANTIES AND/OR
COVENANTS, EITHER EXPRESS OR IMPLIED, STATUTORY OR AT COMMON LAW, INCLUDING, BUT NOT LIMITED TO,
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September 6, 2019 © 2016-2019 CCIX Consortium, Inc. ALL RIGHTS RESERVED. CONFIDENTIAL
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Table of Contents
Chapter 1.
Chapter 2.
Chapter 3.
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Document Overview ................................................................................................................ 18
1.1 SPECIFICATION OBJECTIVE ......................................................................................................................... 18
1.2 TERMS AND ACRONYMS ........................................................................................................................... 18
1.3 REFERENCE DOCUMENTS .......................................................................................................................... 21
CCIX Overview .......................................................................................................................... 22
2.1 INTRODUCTION ....................................................................................................................................... 22
2.2 TOPOLOGIES ........................................................................................................................................... 23
2.3 CCIX ARCHITECTURE MODEL ..................................................................................................................... 24
Components of the CCIX Architecture ........................................................................................ 25
Port Aggregation ......................................................................................................................... 27
CCIX Extended Data Rate Physical Layer ..................................................................................... 28
2.4 CCIX MANAGEMENT FRAMEWORK ............................................................................................................ 28
2.5 RAS ARCHITECTURE ................................................................................................................................. 28
2.6 ADDRESS TRANSLATION SERVICE ................................................................................................................ 28
2.7 SIGNALING HOSTS FROM ACCELERATORS ..................................................................................................... 29
2.8 ESTABLISHING TRUST WITH A CCIX ACCELERATOR ........................................................................................ 29
Protocol Layer .......................................................................................................................... 30
3.1 INTRODUCTION ....................................................................................................................................... 30
CCIX Agents ................................................................................................................................. 30
Discovery and Enumeration ........................................................................................................ 32
Topologies ................................................................................................................................... 33
3.2 MESSAGE FIELDS ..................................................................................................................................... 34
Request Message ........................................................................................................................ 34
Snoop Message ........................................................................................................................... 36
Response Message ...................................................................................................................... 37
Field Descriptions ........................................................................................................................ 37
3.3 COHERENCE PROTOCOL ............................................................................................................................ 41
Cache States ................................................................................................................................ 41
Request Types ............................................................................................................................. 44
Request Responses ..................................................................................................................... 52
Snoop Requests ........................................................................................................................... 53
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Table of Contents
Snoop Responses ........................................................................................................................ 58
MiscOp Encoding ........................................................................................................................ 61
Protocol Error Report .................................................................................................................. 61
Request Cache State Transitions................................................................................................. 61
State Transitions at Snoopee ...................................................................................................... 64
Silent Cache State Transitions ................................................................................................... 66
Controlling the use of Evict and WriteEvictFull transactions .................................................... 67
Simultaneous Outstanding Requests ........................................................................................ 68
Request to Snoop Hazard ......................................................................................................... 68
3.4 TRANSACTION STRUCTURE ........................................................................................................................ 71
Request Transactions .................................................................................................................. 71
Snoop Transactions ..................................................................................................................... 75
3.5 ADDRESS, CONTROL, AND DATA ................................................................................................................. 77
Address and Data Alignment ...................................................................................................... 77
Request Attributes ...................................................................................................................... 77
Permitted Memory Type for Requests ....................................................................................... 79
Data and Byte Enables ................................................................................................................ 80
3.6 ORDERING .............................................................................................................................................. 84
Multi-copy Atomicity .................................................................................................................. 84
Completion Response and Ordering ........................................................................................... 84
CompAck ..................................................................................................................................... 85
Comp and Outstanding CompAck Dependency .......................................................................... 85
3.7 FLOW CONTROL AND PROTOCOL CREDITS ..................................................................................................... 85
Protocol Credits .......................................................................................................................... 85
Credit Exchange .......................................................................................................................... 87
3.8 MISCELLANEOUS MESSAGES ...................................................................................................................... 89
Uncredited Misc Messages ......................................................................................................... 90
Credited Misc Messages ............................................................................................................. 90
ID Namespace ............................................................................................................................. 90
Extension Fields in Misc Message ............................................................................................... 90
3.9 ERROR HANDLING .................................................................................................................................... 90
Error Classification ...................................................................................................................... 90
3.10 PACKET HEADER .................................................................................................................................... 91
Packet Header ........................................................................................................................... 91
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Message Packing ....................................................................................................................... 94
3.11 MESSAGE FORMATS ............................................................................................................................... 95
Read Request ............................................................................................................................ 95
Write Request ........................................................................................................................... 95
Response without Data ............................................................................................................. 96
Response with Data .................................................................................................................. 97
Snoop ........................................................................................................................................ 97
Miscellaneous Message type .................................................................................................... 98
Request Chaining .................................................................................................................... 100
Snoop Chaining ....................................................................................................................... 100
Extension fields ....................................................................................................................... 101
3.12 OPTIONAL FEATURES AND PARAMETERS .................................................................................................. 103
CompAck Removal .................................................................................................................. 103
Partial Cache States ................................................................................................................ 104
Cache Line Size ........................................................................................................................ 104
Address Width......................................................................................................................... 104
Packet Header ......................................................................................................................... 104
Message Packing Enable ......................................................................................................... 104
Maximum Packet Size ............................................................................................................. 105
Summary of Properties ........................................................................................................... 105
3.13 MESSAGE ROUTING AND AGENT ID ASSIGNMENT ..................................................................................... 105
Message Routing ..................................................................................................................... 105
Broadcast Snoop Routing ........................................................................................................ 108
TxnID Assignment ................................................................................................................... 109
Agent ID .................................................................................................................................. 110
Target ID Determination ......................................................................................................... 110
Agent ID assignment Summary ............................................................................................... 110
3.14 MEMORY EXPANSION ........................................................................................................................... 111
Concurrent Memory Expansion .............................................................................................. 112
3.15 PORT AGGREGATION ............................................................................................................................ 113
Port Aggregation Routing ....................................................................................................... 114
3.16 TERMINOLOGY .................................................................................................................................... 114
3.17 TRANSACTION FLOW EXAMPLES ............................................................................................................. 117
Read Request with End-to-End CompAck ............................................................................... 118
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Read Request with an Early CompAck .................................................................................... 118
Write Request ......................................................................................................................... 119
CCIX Transport Layer .............................................................................................................. 120
4.1 INTRODUCTION ..................................................................................................................................... 120
CCIX Transaction Layer .............................................................................................................. 122
PCIe Transaction Layer .............................................................................................................. 123
PCIe Data Link Layer .................................................................................................................. 123
CCIX Physical Layer .................................................................................................................... 123
4.2 TRANSACTION LAYER .............................................................................................................................. 124
CCIX Transaction Layer Architecture......................................................................................... 124
Transaction Layer Protocol - Packet Definition......................................................................... 125
CCIX Virtual Channel ................................................................................................................. 128
Handling of Received TLPs ........................................................................................................ 129
Transaction Ordering Rules ....................................................................................................... 133
Virtual Channel (VC) Mechanism .............................................................................................. 133
Transaction Layer Flow Control ................................................................................................ 134
Data Integrity ............................................................................................................................ 134
Completion Timeout Mechanism ............................................................................................. 135
Link Status Dependencies ....................................................................................................... 135
4.3 CCIX DATA LINK LAYER .......................................................................................................................... 135
REPLAY_TIMER Limits for 20.0 GT/s and 25.0 GT/s .................................................................. 135
AckNak_LATENCY_TIMER Limits for 20.0 GT/s and 25.0 GT/s ................................................. 135
4.4 CCIX PHYSICAL LAYER LOGICAL BLOCK ...................................................................................................... 135
Introduction .............................................................................................................................. 135
CCIX Logical Sub-block .............................................................................................................. 136
Retimers .................................................................................................................................... 146
Electrical PHY Layer ................................................................................................................ 147
5.1 INTRODUCTION ..................................................................................................................................... 147
5.2 EDR25-SR ELECTRICAL SPECIFICATION ..................................................................................................... 148
General Specification ................................................................................................................ 148
Transmitter Specification .......................................................................................................... 150
Receiver Specification ............................................................................................................... 154
PCIe-Specific Specifications ....................................................................................................... 164
Reference Clock Specification ................................................................................................... 165
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Channel Compliance ................................................................................................................. 166
5.3 EDR25-LR ELECTRICAL SPECIFICATION ..................................................................................................... 174
General Specification ................................................................................................................ 174
Transmitter Specification .......................................................................................................... 176
Receiver Specification ............................................................................................................... 180
PCIe-Specific Specifications ....................................................................................................... 191
Reference Clock Specification ................................................................................................... 191
Channel Compliance ................................................................................................................. 193
5.4 EDR32 ELECTRICAL SPECIFICATION .......................................................................................................... 201
Protocol Layer and Transport Layer DVSEC ........................................................................... 202
6.1 OVERVIEW ........................................................................................................................................... 202
6.2 PROTOCOL LAYER DVSEC ....................................................................................................................... 203
Introduction to CCIX Protocol Layer DVSEC .............................................................................. 203
CCIX Component Structures ..................................................................................................... 224
6.3 TRANSPORT DVSEC ............................................................................................................................... 337
CCIXTransportCapabilities Register........................................................................................... 339
ESMMandatoryDataRateCapability Register ............................................................................ 341
ESMOptionalDataRateCapability Register ................................................................................ 342
ESMStatus Register ................................................................................................................... 342
ESMControl Register ................................................................................................................. 343
ESMLaneEqualizationControl Registers .................................................................................... 350
TransportLayerCapabilities Register ......................................................................................... 352
TransportLayerControl Register ................................................................................................ 353
6.4 DVSEC DISCOVERY AND CONFIGURATION ................................................................................................. 354
6.5 CCIX SWITCH REFERENCED DATA STRUCTURES .......................................................................................... 355
6.6 EXAMPLES TO ILLUSTRATE PROTOCOL LAYER DVSEC USAGE ........................................................................ 356
Simple CCIX Topology and Relevant Data Structures ............................................................... 357
Complex CCIX Topology and Relevant Data Structures ............................................................ 364
CCIX RAS Overview ................................................................................................................. 368
7.1 CLASSIFICATION OF HARDWARE FAULTS .................................................................................................... 368
7.2 HARDWARE ERROR PROPAGATION ........................................................................................................... 368
7.3 CCIX PROTOCOL ERROR REPORTING (PER) ............................................................................................... 369
CCIX PER Message Format ........................................................................................................ 371
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CCIX PER Log Structures ............................................................................................................ 377
Memory Error Type Structure ................................................................................................... 381
Cache Error Type Structure ....................................................................................................... 384
ATC Error Type Structure .......................................................................................................... 387
Port Error Type Structure .......................................................................................................... 388
CCIX Link Error Type Structure .................................................................................................. 390
Agent Internal Error Type Structure ......................................................................................... 391
Vendor-Specific Log Info ........................................................................................................... 392
7.4 CCIX ERROR CONTROL & STATUS STRUCTURES .......................................................................................... 393
Error Control Register Definitions ............................................................................................. 394
Device Error Control Flows ....................................................................................................... 399
CCIX ATS Specification ........................................................................................................... 401
8.1 INTRODUCTION ..................................................................................................................................... 401
8.2 ADDRESS TRANSLATION SERVICES ............................................................................................................. 401
8.3 INVALIDATION SEMANTICS ...................................................................................................................... 402
8.4 MEMORY TYPE INFORMATION ................................................................................................................. 402
Memory Type ............................................................................................................................ 402
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