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CMOS有源像素图像传感器的成像原理分析.pdf
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Radiation Effects on CMOS Active Pixel Image Sensors
Chapter · November 2015
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Radiation Effects on CMOS Active Pixel Image Sensors
Vincent Goiffon
Institut Supérieur de l’Aéronautique et de l’Espace (ISAE-SUPAERO)
Université de Toulouse, France
To cite this version : V. Goiffon, “Radiation effects on CMOS active pixel image sensors,” in
Ionizing Radiation Effects in Electronics: From Memories to Imagers.
Boca Raton, FL, USA: CRC Press, 2015, pp. 295–332.
Table of Content
1
Introduction ..............................................................................................................................................2
1.1 Context .................................................................................................................................................2
1.2 APS, CIS and MAPS ............................................................................................................................2
1.3 Basic knowledge on radiation effects ...................................................................................................2
2
Introduction to CMOS image sensors ......................................................................................................3
2.1 Overview of CIS technology ................................................................................................................3
2.2
Selected important CIS concepts for radiation effect discussions ........................................................6
2.2.1
2.2.2
2.2.3
Full well capacity and pinning voltage .........................................................................................6
Dark current sources .....................................................................................................................8
Random telegraph signal noises: DC-RTS and SF-RTS ............................................................10
Single event effects .................................................................................................................................12
Cumulative radiation effects on peripheral circuits ................................................................................12
Cumulative radiation effects on pixel performances ..............................................................................13
5.1 Total ionizing dose effects ..................................................................................................................13
5.1.1
5.1.2
5.1.3
Degradation mechanism overview and common effects ............................................................13
Pinned photodiode specific effects .............................................................................................17
Radiation-hardening of CIS pixels .............................................................................................19
5.2 Displacement damage effects .............................................................................................................20
5.2.1
5.2.2
Overview ....................................................................................................................................20
Dark current, DCNU and RTS ...................................................................................................20
Conclusion ..............................................................................................................................................23
References and further reading ...............................................................................................................23
3
4
5
6
7
This is an Accepted Manuscript of a book chapter published by CRC Press in Ionizing Radiation Effects in
Electronics: From Memories to Imagers on 2015, available online: https://www.crcpress.com/Ionizing-
Radiation-Effects-in-Electronics-From-Memories-to-Imagers/Bagatin-Gerardin/9781498722605
1
1 Introduction
1.1 Context
Today, Complementary-Metal-Oxide-Semiconductor (CMOS) Image Sensors (CIS) [1]–[4], also called
Active Pixel Sensors (APS), are the most popular imager technology with several billions manufactured every
year [5], [6]. They represent about 90% of the imager market and should exceed 95% in a couple of years [5].
Compared to the main alternative imager technology, the Charge Coupled Device (CCD), CISs have several
major benefits such as low-power consumption, high-integration, high speed and the capacity to integrate
advanced CMOS functions on-chip (and even inside the pixel). Thanks to the latest technology innovations,
CISs are now matching the performances of CCDs in terms of image quality and sensitivity placing them at the
forefront even in high-end applications such as digital single-lens reflex, scientific instruments, and machine
vision. Thanks to these advantages, CISs are also used in harsh radiation environment for applications such as:
space applications, X-ray medical imaging, electron microscopy, nuclear facility monitoring and remote
handling (nuclear power plants, nuclear waste repositories, nuclear physics facilities…), particle detection and
imaging, military applications etc.. Designing, hardening and testing a sensor for such applications require the
understanding of the CIS behavior when exposed to radiation sources. Understanding and improving further the
intrinsically good radiation hardness of APS has been a topic of interest since its invention [7]–[13]. This
interest has been recently growing with the coming of new behaviors brought by the profound evolution of CIS
technologies (as discussed throughout this manuscript) compared to the older generation mainstream CMOS
processes used in early work.
The aim of this chapter is to give an overview of the parasitic effects that can undergo a modern CIS when it
is exposed to a high energy particle radiation field.
1.2 APS, CIS and MAPS
APS, CIS and Monolithic-Active-Pixel-Sensors (MAPS)[14][15] designate the same type of CMOS
Integrated Circuit (IC): a pixel array with a photodetector and an amplifier inside each pixel[1][2]. Depending
on the community, one of these names may be used preferentially. APS is the generic term, CIS is mainly used
for imaging applications whereas MAPS is the main term used in the particle detection community to emphasize
the monolithic nature of the device compared to hybrid detectors. In most of the cases, a CIS is an APS
manufactured using a CMOS process optimized for imaging applications (called CIS process) whereas MAPS
are generally manufactured using standard, or high voltage CMOS processes and their main purpose is not
optical imaging but high energy particle detection (and imaging). From the radiation effect point of view, there
is qualitatively no major difference between MAPS and CIS if the photodetector technology is the same. It
means that, despite the fact this chapter focuses on CIS, most of the discussions developed here apply to both
families of sensors.
1.3 Basic knowledge on radiation effects
The following radiation effect concepts are used in this chapter to describe the influence of high energy
particles on CIS. The reader is invited to look at the first chapter of this book or at the references given in this
section to have the details of the origin and limitations of these definitions, mechanisms and properties.
When passing through the layers of the materials that constitute an IC, ionizing particles (such as high
energy photons (X and rays) and charged particles (electrons, protons, heavy ions…)) lose most of their
energy by generating electron-hole pairs. This excess of charge carriers can disturb or damage ICs by inducing
Single Event Effects (SEE) [16](and references therein) or Total Ionizing Dose (TID) effects. SEE occurs when
the electron-hole pairs generated by a single particle are sufficient to disturb or damage the IC whereas TID
effects are the result of the cumulative exposure to ionizing radiation.
2
The TID (or absorbed dose) represents the mean energy imparted to matter per unit mass by ionizing
interaction and it is expressed here in Gy(SiO2) (i.e. 1J or energy per kg of SiO2)1,2. The ionizing radiation dose
absorbed by electronic circuits in medical and space applications are generally below 100Gy-1kGy whereas the
MGy range can be reached in electron microscopes or nuclear and particle physics experiments. Through this
chapter the reader should keep in mind that the absorbed TID leads to the buildup of trapped positive charge in
the dielectrics, to the buildup of interface states at the Si/oxide interfaces and that these defect densities increase
with TID. Detailed review of TID effects can be found in [17]–[22].
High energy particles can also lose their energy in matter through non-ionizing interactions. These
interactions can be summarized as direct interactions with atomic nucleus and they generally result in the
displacement of this nucleus. Contrary to TID effects that are mainly a concern in dielectrics, atomic
displacement is mainly an issue in the crystalline silicon part of the circuit. The effects linked to radiation
induced atomic displacements are called displacement damage effects and the mean energy imparted to matter
per unit mass by non-ionizing interaction is called Displacement Damage Dose (Dd) (generally expressed in
eV/g(Si)). It is important to note that the Dd leads to the creation of defects in silicon lattice that can act as
Shockley-Read-Hall (SRH) generation/recombination centers or SRH carrier traps. These defects can take the
form of point defects in the lattice or to clusters of defects (also called amorphous inclusions). Reviews of
Displacement Damage Effects that discuss the origin and the limitation of the Dd concept (and especially the
Non-Ionizing-Energy-Loss(NIEL) concept) can be found in [23]–[26].
2 Introduction to CMOS image sensors
2.1 Overview of CIS technology
The basic working principle of CMOS Active Pixel Image Sensors can be found in [2], [3], [27]–[30]. As
any APS, CIS are constituted by [2] a pixel array, addressing circuits to access the pixels (the address decoders)
and an analog signal processing circuit (often called readout circuit). This basic architecture common to nearly
every APS IC (including MAPS) is presented in Figure 1a. In addition to these necessary building blocks,
modern CIS products [29]–[32] often integrate on-chip one or more of the following functions: one Analog-to-
Digital Converter (ADC) per column (see [32]–[34] and references therein for ADC architectures used in CISs),
a sequencer, a digital image processing unit, high speed I/O interfaces, configuration registers and so on.
Unlike MAPS that are generally manufactured using standard commercial CMOS processes[35] (standard
mixed-mode or high voltage processes, sometimes slightly customized), most of CIS ICs are produced thanks to
dedicated CIS processes optimized for visible light detection. Figure 1b and c present simplified cross sectional
views of typical modern CIS technologies [36]–[39]. The base of a CIS process is similar to a standard Deep
Sub-Micron (DSM) CMOS technology[40]: outside the pixel array, Metal-Oxide-Semiconductor Field-Effect-
Transistors (MOSFET) are most often the same as the ones used in the mixed-mode version of the process (i.e.
non CIS) with the use of classical Source/Drain implants, N and P wells, Shallow Trench Isolation (STI),
polysilicon gates and the typical dielectric stack (constituted by the Inter-Layer Dielectrics (ILD)) on top of the
semiconductor devices to insure the isolation between the interconnect layers. The first ILD between the first
level of metal and the active silicon or the polysilicon layer is often called the Pre-Metal Dielectric (PMD).
Compared to mainstream CMOS ICs, CISs have however several unique features to improve the light
collection:
a reduced number of interconnection metal levels
dedicated dielectrics such as Anti-Reflection (AR) Coatings
microlenses and light guides[41][42]
…
filters for color imaging
1 Gy(SiO2) is used here instead of Gy(Si) because TID effects are due to the absorbed dose in the dielectrics (mainly
constituted by SiO2) not to the absorbed dose in the silicon.
2 1 Gy = 100 rad
3
Figure 1 : Overview of CIS technology: (a) Typical CMOS Image Sensor Integrated Circuit architecture (the dashed blocks
are optional and usually, only one type of output is available in a CIS (digital or analog)). Example of FSI (b) and BSI(c) CIS
cross sectional views (inspired from the cross sectional view shown in [36]).
Several improvements are also made at the device level to optimize the photo-generated charge collection while
reducing the dark signal and the noise:
dedicated photodiode and in-pixel isolation doping profiles (P-wells, trench sidewall passivation…)
dedicated pixel devices (optimized in-pixel MOSFETs with specific threshold voltages, dedicated
MOSFET devices for in-pixel charge transfer…)
a lightly doped epitaxial layer with a thickness optimized for the targeted wavelength range
dedicated in-pixel trench isolations to minimize crosstalk [43], such as Deep Trench Isolation (DTI)
…
In addition to these special features, CIS can be Front-Side Illuminated (FSI) or Back-Side Illuminated
(BSI), as illustrated in Figure 1b and c. BSI technologies allow to collect more light (leading to higher External
Quantum Efficiency (EQE)[31]) for a given fill factor but they require the thinning of the sensitive layer down
to a few micrometers and the use of backside passivation techniques to reduce signal charge recombination and
dark current generation at the back interface[39], [44]–[46].
4
Figure 2 : Typical schematic, layout and cross sectional views of (a) a typical 3T-Pixel and of (b) a typical 4T-PPD-Pixel.
Cross sectional views of (c) a 3T Partially Pinned Photodiode pixel and (d) a 5T Pinned Photodiode Pixel are also presented
in this figure. SCR = Space Charge Region. ATP= Anti Punch Through implant. Vth = threshold voltage implant.
Several active pixel architectures have been proposed[2] but the vast majority of modern device pixels are
based on these two basic designs: the 3T-pixel based on a conventional photodiode (Figure 2a) and the 4T-pixel
based on a dedicated buried photodiode (Figure 2b), called Pinned PhotoDiode(PPD) [47]–[50]. Because of its
low noise, high quantum efficiency and low dark current[50] the pinned photodiode is used in almost all
consumer applications. However, this photodetector is only available in CIS processes and the conventional
photodiode used in 3T-pixel may exhibit some advantages in niche applications (e.g. where large pixel pitches
or high full well capacity are required). Therefore conventional photodiodes are still used in most of MAPS, in
some specific CIS that do not require the use of PPD and in other APS not manufactured with CIS processes. As
shown in Figure 2, both basic pixel architectures share the same three transistors:
the reset (RST) MOSFET used to reset the Floating Diffusion (FD) (also called Sense Node (SN)) which
performs the charge to voltage conversion thanks to its intrinsic capacitance. In the case of 3T pixel, the
photodiode is the FD.
the Source Follower (SF) MOSFET used to perform the in-pixel amplification
the Row Select switch (RS) MOSFET used to connect the pixel to the column sample-and-hold stage
In PPD based pixels, another MOSFET is necessary to transfer the charge collected during integration to the FD
(and also to empty the PPD potential well), this additional transistor is called the Transfer Gate (TG).
The cross sectional view in Figure 2a shows that the conventional CIS photodiode used in 3T-pixels is
typically a deep N-CIS implant (similar to N-well implants but optimized for photodetection) on P-epitaxial
layer and surrounded by a P-well. Depending on the design, the STI can cover the whole N-CIS implant or be
recessed from the N-CIS region. In any case, the depletion region in conventional photodiodes reaches an oxide
interface (generally the STI-bottom as illustrated in Figure 2a, or the PMD/Si interface if the STI is recessed) all
5
over its perimeter. In other type of APS (such as MAPS), this conventional photodiode can be made using the
N-MOSFET Source/Drain N+ implant or the P-MOSFET N-well implant. Some APS even use triple or
quadruple well technologies to realize deeper photodiodes[35][51][52]. It is also possible to reverse the doping
types and to use P on N substrate photodiodes.
Contrary to the conventional CIS photodiode, the PPD is a buried N-PPD implant surrounded by a P-well (or
STI passivation P doping) and protected from the PMD interface by a P+ pinning implant on top of it. This
pinning layer is also used to insure the full depletion of the PPD N region after a complete charge transfer. If the
TG is completely turned OFF (i.e. biased in accumulation regime, generally with the use of negative gate
voltage), the PPD depletion region does not reach any oxide interface because it is protected from the STI by the
P-well (or P-STI) doping, from the PMD by the pinning layer and from the TG channel by the TG accumulation
layer (as illustrated in Figure 2b).
For discussing the radiation effects on CIS, two variations have to be presented: the partially-pinned-
photodiode (Figure 2c) and the 5T-PPD pixel (Figure 2d). The first is similar to the 3T pixel conventional
photodiode except it is covered by a P+ pinning implant. In the case of partially-pinned-photodiode, the pinning
implant sole purpose is to reduce the dark current by reducing the contact area between the photodiode depletion
region and the surrounding oxides (STI and PMD). In order to connect this photodiode to the SF and RST
MOSFETs, the P+ pinning layer has to be opened somewhere to let the N region reach the surface. Therefore,
contrary to PPDs, partially pinned photodiode depletion region is in contact with oxide interfaces, in the vicinity
of the SF/RST contacts. This is illustrated in Figure 2c where one can see that the contact between the Space
Charge Region (SCR) and the oxide interface (PMD here) is near the RST MOSFET. The total area of this
depleted oxide interface is smaller than in a 3T-pixel conventional diode design where the depleted interface
runs all along the photodiode perimeter (indeed the contact between the SCR and the oxide is located below the
peripheral STI in Figure 2a). Since the dark current rises with the total depleted oxide interface area in the
photodiode (as explained in the next section), the dark current in partially pinned photodiode is much higher
than in a PPD but it is lower than in a conventional photodiode.
The other interesting variation from the radiation effect point of view is the 5T-PPD pixel (Figure 2d) in
which an additional TG is added in a PPD based pixel to perform an Anti-Blooming(AB) or Global Shutter(GS)
function (or both)[53]. Any more complex pixel with even more transistors (such as the one that can be found in
so-called smart sensors[54][55][29][56]) will be based on one of this building block (the 3T pixel, the 4T PPD
pixel, the 3T partially pinned photodiode pixel or the 5T PPD pixel) and thus, to understand the radiation effect
on any CIS, the first step is to understand the radiation effects on these elementary pixel structures. The
discussions presented in this chapter can easily be transposed to more integrated pixel architecture.
2.2 Selected important CIS concepts for radiation effect discussions
This section provides some details about a few selected CIS concepts that are necessary to discuss the
radiation effects. More information about generic solid-state imager parameter definitions, such as External
Quantum Efficiency (EQE), Charge to Voltage conversion Factor (CVF), Charge Transfer Efficiency (CTE),
Charge Transfer Inefficiency (CTI), Maximum Output Voltage Swing (MOVS) and Dynamic Range (DR), can
be found in the previously given references [2], [3], [27]–[30] or in [57]–[59].
2.2.1 Full well capacity and pinning voltage
In 3T active pixels the saturation level is given by the saturation of the readout chain (or the ADC) and it is
thus not related to the photodiode maximum charge (called the Full Well Capacity (FWC)[58]). In a 4T-pixel
during integration (Figure 3a), the photo generated electrons are collected in the PPD potential well which is
isolated from the FD by turning the TG OFF (here, this TG OFF voltage is referred to as VLOTG). At the end of
the integration time tint, the TG is turned ON (Figure 3b) and the collected charge is transferred to the FD for
being readout. Since the collecting well (i.e. the PPD) is separated from the readout node (the FD), the
saturation charge of the PPD (the FWC) can be lower than the saturation charge of the FD. In this case, the
output saturation level is given by the photodiode FWC.
An important parameter specific to PPD pixels is the pinning voltage Vpin of the buried photodiode. The
pinning voltage represents the “bottom” of the PPD potential well (as illustrated in Figure 3). More precisely,
6
Figure 3 : PPD-TG structure operation and Vpin measurement illustrations. (a) During integration, the TG is OFF and the
photo-generated electrons are collected in the PPD potential well. (b) To readout the collected charge, the TG is turned ON
and the electrons are transferred to the Floating Diffusion (FD). (c) Pinning voltage characteristic with the PPD-TG physical
parameters that can be extracted [60] : Equilibrium Full Well Capacity (EFWC), PPD capacitance (CPPD), Pinning Voltage
(Vpin) and TG threshold voltage (Vth).
this potential corresponds to the maximum PPD channel potential[50], [60], [61]. The higher is Vpin, the higher
is the FWC (but the pinning potential must stay low enough to ensure a good transfer). It is possible to measure
the pinning voltage at the sensor output[62] from the pinning voltage characteristic presented in Figure 3c. This
technique can also be used to extract several important physical parameters of the PPD-TG structure[60]. Its
basic principle (presented in Figure 3c) is detailed in[60][62]. It consists in injecting electrons (charge Qinj) in
the PPD during the integration phase by applying the injection voltage Vinj on the FD (with TG and RST
MOSFETs turned ON).
As explained in detail in[60], the pinning voltage corresponds to the boundary voltage between the injection
and partial injection regime of Figure 3c, the Y-intersect of the characteristic provides the Equilibrium Full Well
Capacity (EFWC)3, the slope in the injection regime gives de PPD capacitance (CPPD) and the step
corresponding to the beginning of the partial injection regime allows to estimate the TG threshold voltage.
At a given temperature, the saturation charge of a PPD depends on the photon flux and on the TG bias (as
shown in Figure 4a). As a consequence, several Full Well Capacities can be defined in a PPD CIS[63][64].
These different saturation levels can be explained by the TG-PPD electrical schematic presented in Figure 4b
[63][65]. The saturation charge of the PPD capacitance is reached during integration when the current flowing
through the diode (the photonic current Iphot and the dark current Idark) is compensated by the TG subthreshold
current (Isubth). A graphical representation of this model is presented in Figure 4c. It shows a part of the classical
PN junction I-V characteristic [66] without illumination (Idark curve) and with illumination (Iphot+Idark curve). The
PPD charge is directly related to the PPD potential (through the PPD capacitance CPPD). Hence, the voltage X-
axis can be graduated in stored charge values (QPPD). The FWC corresponds then to the maximum QPPD for each
case presented in Figure 4c. The saturation charge reached in the dark at steady state (for an infinitely long
integration time) is called FWCdark in Figure 4a and c whereas the saturation charge reached under illumination
is called FWC.
For negligible TG subthreshold current (negative TG OFF voltage VLOTG), the FWC is reached when the
photodiode current intersect the x-axis. In this particular case, FWCdark EFWC and FWC = FWCmax (case 1
in Figure 4c). For higher VLOTG values, Isubth becomes significant and the FWC values are determined as the
intersection between the photodiode current curve and the Isubth curve (case 2 in Figure 4c). This graphical
representation illustrates that:
3 The EFWC is the charge stored in the PPD at equilibrium[63][64], which corresponds to a PPD potential equal to 0V.
7
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