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ITE 8516 DataSheet.pdf
1. Features
2. General Description
3. System Block Diagram
3.1 Block Diagram
3.2 Host/EC Mapped Memory Space
3.3 EC Mapped Memory Space
3.4 Register Abbreviation
4. Pin Configuration
4.1 Top View
5. Pin Descriptions
5.1 Pin Descriptions
5.2 Chip Power Planes and Power States
5.3 Pin Power Planes and States
5.4 PWRFAIL# Interrupt to INTC
5.5 Reset Sources and Types
5.5.1 Related Interrupts to INTC
5.6 Chip Power Mode and Clock Domain
5.7 Pins with Pull, Schmitt-Trigger or Open-Drain Function
5.8 Power Consumption Consideration
6. Host Domain Functions
6.1 Low Pin Count Interface
6.1.1 Overview
6.1.2 Features
6.1.3 Accepted LPC Cycle Type
6.1.4 Debug Port Function
6.1.5 Serialized IRQ (SERIRQ)
6.1.6 Related Interrupts to WUC
6.1.7 LPCPD# and CLKRUN#
6.1.8 Check Items
6.2 Plug and Play Configuration (PNPCFG)
6.2.1 Logical Device Assignment
6.2.2 Super I/O Configuration Registers
6.2.2.1 Logical Device Number (LDN)
6.2.2.2 Chip ID Byte 1 (CHIPID1)
6.2.2.3 Chip ID Byte 2 (CHIPID2)
6.2.2.4 Chip Version (CHIPVER)
6.2.2.5 Super I/O Control Register (SIOCTRL)
6.2.2.6 Super I/O IRQ Configuration Register (SIOIRQ)
6.2.2.7 Super I/O General Purpose Register (SIOGP)
6.2.2.8 Super I/O Power Mode Register (SIOPWR)
6.2.3 Standard Logical Device Configuration Registers
6.2.3.1 Logical Device Activate Register (LDA)
6.2.3.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.3.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.3.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.3.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.3.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.3.7 Interrupt Request Type Select (IRQTP)
6.2.3.8 DMA Channel Select 0 (DMAS0)
6.2.3.9 DMA Channel Select 1 (DMAS1)
6.2.4 Serial Port 1 (UART1) Configuration Registers
6.2.4.1 Logical Device Activate Register (LDA)
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.4.7 Interrupt Request Type Select (IRQTP)
6.2.4.8 High Speed Baud Rate Select (HHS)
6.2.5 Serial Port 2 (UART2) Configuration Registers
6.2.5.1 Logical Device Activate Register (LDA)
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.5.7 Interrupt Request Type Select (IRQTP)
6.2.5.8 High Speed Baud Rate Select (HHS)
6.2.6 System Wake-Up Control (SWUC) Configuration Registers
6.2.6.1 Logical Device Activate Register (LDA)
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.6.7 Interrupt Request Type Select (IRQTP)
6.2.7 KBC / Mouse Interface Configuration Registers
6.2.7.1 Logical Device Activate Register (LDA)
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.7.7 Interrupt Request Type Select (IRQTP)
6.2.8 KBC / Keyboard Interface Configuration Registers
6.2.8.1 Logical Device Activate Register (LDA)
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.8.7 Interrupt Request Type Select (IRQTP)
6.2.9 Consumer IR Configuration Registers
6.2.9.1 Logical Device Activate Register (LDA)
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.9.4 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.9.5 Interrupt Request Type Select (IRQTP)
6.2.10 Shared Memory/Flash Interface (SMFI) Configuration Registers
6.2.10.1 Logical Device Activate Register (LDA)
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.10.7 Interrupt Request Type Select (IRQTP)
6.2.10.8 Shared Memory Configuration Register (SHMC)
6.2.10.9 H2RAM-HLPC Base Address [15:12] (HLPCRAMBA[15:12])
6.2.10.10 H2RAM-HLPC Base Address [23:16] (HLPCRAMBA[23:16])
6.2.11 Real Time Clock (RTC) Configuration Registers
6.2.11.1 Logical Device Activate Register (LDA)
6.2.11.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.11.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.11.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.11.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.11.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.11.7 Interrupt Request Type Select (IRQTP)
6.2.11.8 RAM Lock Register (RLR)
6.2.11.9 Date of Month Alarm Register Offset (DOMAO)
6.2.11.10 Month Alarm Register Offset (MONAO)
6.2.11.11 P80L Begin Index (P80LB)
6.2.11.12 P80L End Index (P80LE)
6.2.11.13 P80L Current Index (P80LC)
6.2.12 Power Management I/F Channel 1 Configuration Registers
6.2.12.1 Logical Device Activate Register (LDA)
6.2.12.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.12.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.12.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.12.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.12.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.12.7 Interrupt Request Type Select (IRQTP)
6.2.13 Power Management I/F Channel 2 Configuration Registers
6.2.13.1 Logical Device Activate Register (LDA)
6.2.13.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.13.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.13.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.13.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.13.6 I/O Port Base Address Bits [15:8] for Descriptor 2 (IOBAD2[15:8])
6.2.13.7 I/O Port Base Address Bits [7:0] for Descriptor 2 (IOBAD2[7:0])
6.2.13.8 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.13.9 Interrupt Request Type Select (IRQTP)
6.2.13.10 General Purpose Interrupt (GPINTR)
6.2.14 Power Management I/F Channel 3 Configuration Registers
6.2.14.1 Logical Device Activate Register (LDA)
6.2.14.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.14.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.14.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.14.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.14.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.14.7 Interrupt Request Type Select (IRQTP)
6.2.15 Serial Peripheral Interface (SSPI) Configuration Registers
6.2.15.1 Logical Device Activate Register (LDA)
6.2.15.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.2.15.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.2.15.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.2.15.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.2.15.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.2.15.7 Interrupt Request Type Select (IRQTP)
6.2.16 Programming Guide
6.3 Shared Memory Flash Interface Bridge (SMFI)
6.3.1 Overview
6.3.2 Features
6.3.3 Function Description
6.3.3.1 Supported Interface
6.3.3.2 Supported Flash
6.3.3.3 HLPC: Host Translation
6.3.3.4 HLPC: Memory Mapping
6.3.3.5 HLPC: Host-Indirect Memory Read/Write Transaction
6.3.3.6 EC-Indirect Memory Read/Write Transaction
6.3.3.7 HSPI: Host Translation
6.3.3.8 Flash Shared between Host and EC Domains
6.3.3.9 Host Access Protection
6.3.3.10 Serial Flash Performance Consideration
6.3.3.11 Response to a Forbidden Access
6.3.3.12 Scratch SRAM
6.3.3.13 DMA for Scratch SRAM
6.3.3.14 HLPC: Flash Programming via Host LPC Interface with Scratch SRAM
6.3.3.15 Force 8032 to Code Fetch from Internal SRAM
6.3.3.16 Force 8032 to Clear Dynamic Caches
6.3.3.17 HLPC: Serial Flash Programming
6.3.3.18 Host Side to EC Scratch RAM (H2RAM)
6.3.3.18.1 HLPC to EC Scratch RAM (H2RAM-HLPC)
6.3.3.18.2 HSPI to EC Scratch RAM (H2RAM-HSPI)
6.3.3.19 SPI Flash Power-on Detection
6.3.3.19.1 16B-signature and Implicit EC Code Base Address
6.3.3.19.2 Detection Sequence
6.3.4 EC Interface Registers
6.3.4.1 FBIU Configuration Register (FBCFG)
6.3.4.2 Flash Programming Configuration Register (FPCFG)
6.3.4.3 Flash EC Code Banking Select Register (FECBSR)
6.3.4.4 Flash Memory Size Select Register (FMSSR)
6.3.4.5 Shared Memory EC Control and Status Register (SMECCS)
6.3.4.6 Shared Memory Host Semaphore Register (SMHSR)
6.3.4.7 Flash Control 1 Register (FLHCTRL1R)
6.3.4.8 Flash Control 2 Register (FLHCTRL2R)
6.3.4.9 uC Control Register (UCCTRLR)
6.3.4.10 Host Control 2 Register (HCTRL2R)
6.3.4.11 HSPI Control Register 3 (HSPICTRL3R)
6.3.4.12 EC-Indirect Memory Address Register 0 (ECINDAR0)
6.3.4.13 EC-Indirect Memory Address Register 1 (ECINDAR1)
6.3.4.14 EC-Indirect Memory Address Register 2 (ECINDAR2)
6.3.4.15 EC-Indirect Memory Address Register 3 (ECINDAR3)
6.3.4.16 EC-Indirect Memory Data Register (ECINDDR)
6.3.4.17 Scratch SRAM 0 Address Low Byte Register (SCAR0L)
6.3.4.18 Scratch SRAM 0 Address Middle Byte Register (SCAR0M)
6.3.4.19 Scratch SRAM 0 Address High Byte Register (SCAR0H)
6.3.4.20 Scratch SRAM 1 Address Low Byte Register (SCAR1L)
6.3.4.21 Scratch SRAM 1 Address Middle Byte Register (SCAR1M)
6.3.4.22 Scratch SRAM 1 Address High Byte Register (SCAR1H)
6.3.4.23 Scratch SRAM 2 Address Low Byte Register (SCAR2L)
6.3.4.24 Scratch SRAM 2 Address Middle Byte Register (SCAR2M)
6.3.4.25 Scratch SRAM 2 Address High Byte Register (SCAR2H)
6.3.4.26 Scratch SRAM 3 Address Low Byte Register (SCAR3L)
6.3.4.27 Scratch SRAM 3 Address Middle Byte Register (SCAR3M)
6.3.4.28 Scratch SRAM 3 Address High Byte Register (SCAR3H)
6.3.4.29 Scratch SRAM 4 Address Low Byte Register (SCAR4L)
6.3.4.30 Scratch SRAM 4 Address Middle Byte Register (SCAR4M)
6.3.4.31 Scratch SRAM 4 Address High Byte Register (SCAR4H)
6.3.4.32 Protect 0 Base Addr Register 0 (P0BA0R)
6.3.4.33 Protect 0 Base Addr Register 1 (P0BA1R)
6.3.4.34 Protect 0 Size Register (P0ZR)
6.3.4.35 Protect 1 Base Addr Register 0 (P1BA0R)
6.3.4.36 Protect 1 Base Addr Register 1 (P1BA1R)
6.3.4.37 Protect 1 Size Register (P1ZR)
6.3.4.38 Deferred SPI Instruction (DSINST)
6.3.4.39 Deferred SPI Address 15-12 (DSADR1)
6.3.4.40 Deferred SPI Address 23-16 (DSADR2)
6.3.4.41 Host Instruction Control 1 (HINSTC1)
6.3.4.42 Host Instruction Control 2 (HINSTC2)
6.3.4.43 Host RAM Window Control (HRAMWC)
6.3.4.44 Host RAM Winodw 0 Base Address [11:4] (HRAMW0BA[11:4])
6.3.4.45 Host RAM Window 1 Base Address [11:4] (HRAMW1BA[11:4])
6.3.4.46 Host RAM Window 0 Access Allow Size (HRAMW0AAS)
6.3.4.47 Host RAM Window 1 Access Allow Size (HRAMW1AAS)
6.3.5 Host Interface Registers
6.3.5.1 Shared Memory Indirect Memory Address Register 0 (SMIMAR0)
6.3.5.2 Shared Memory Indirect Memory Address Register 1 (SMIMAR1)
6.3.5.3 Shared Memory Indirect Memory Address Register 2 (SMIMAR2)
6.3.5.4 Shared Memory Indirect Memory Address Register 3 (SMIMAR3)
6.3.5.5 Shared Memory Indirect Memory Data Register (SMIMDR)
6.3.5.6 Shared Memory Host Semaphore Register (SMHSR)
6.3.5.7 M-Bus Control Register (MBCTRL)
6.4 System Wake-Up Control (SWUC)
6.4.1 Overview
6.4.2 Features
6.4.3 Functional Description
6.4.3.1 Wake-Up Status
6.4.3.2 Wake-Up Events
6.4.3.3 Wake-Up Output Events
6.4.3.4 Other SWUC Controlled Options
6.4.4 Host Interface Registers
6.4.4.1 Wake-Up Event Status Register (WKSTR)
6.4.4.2 Wake-Up Event Enable Register (WKER)
6.4.4.3 Wake-Up Signals Monitor Register (WKSMR)
6.4.4.4 Wake-Up ACPI Status Register (WKACPIR)
6.4.4.5 Wake-Up SMI# Enable Register (WKSMIER)
6.4.4.6 Wake-Up IRQ Enable Register (WKIRQER)
6.4.5 EC Interface Registers
6.4.5.1 SWUC Control Status 1 Register (SWCTL1)
6.4.5.2 SWUC Control Status 2 Register (SWCTL2)
6.4.5.3 SWUC Control Status 3 Register (SWCTL3)
6.4.5.4 SWUC Host Configuration Base Address Low Byte Register (SWCBALR)
6.4.5.5 SWUC Host Configuration Base Address High Byte Register (SWCBAHR)
6.4.5.6 SWUC Interrupt Enable Register (SWCIER)
6.4.5.7 SWUC Host Event Status Register (SWCHSTR)
6.4.5.8 SWUC Host Event Interrupt Enable Register (SWCHIER)
6.5 Keyboard Controller (KBC)
6.5.1 Overview
6.5.2 Features
6.5.3 Functional Description
6.5.4 Host Interface Registers
6.5.4.1 KBC Data Input Register (KBDIR)
6.5.4.2 KBC Data Output Register (KBDOR)
6.5.4.3 KBC Command Register (KBCMDR)
6.5.4.4 KBC Status Register (KBSTR)
6.5.5 EC Interface Registers
6.5.5.1 KBC Host Interface Control Register (KBHICR)
6.5.5.2 KBC Interrupt Control Register (KBIRQR)
6.5.5.3 KBC Host Interface Keyboard/Mouse Status Register (KBHISR)
6.5.5.4 KBC Host Interface Keyboard Data Output Register (KBHIKDOR)
6.5.5.5 KBC Host Interface Mouse Data Output Register (KBHIMDOR)
6.5.5.6 KBC Host Interface Keyboard/Mouse Data Input Register (KBHIDIR)
6.6 Power Management Channel (PMC)
6.6.1 Overview
6.6.2 Features
6.6.3 Functional Description
6.6.3.1 General Description
6.6.3.2 Compatible Mode
6.6.3.3 Enhanced PM mode
6.6.3.4 PMC2EX
6.6.3.5 PMC3
6.6.4 Host Interface Registers
6.6.4.1 PMC Data Input Register (PMDIR)
6.6.4.2 PMC Data Output Register (PMDOR)
6.6.4.3 PMC Command Register (PMCMDR)
6.6.4.4 Status Register (PMSTR)
6.6.5 EC Interface Registers
6.6.5.1 PM Status Register (PMSTS)
6.6.5.2 PM Data Out Port (PMDO)
6.6.5.3 PM Data Out Port with SCI# (PMDOSCI)
6.6.5.4 PM Data Out Port with SMI# (PMDOSMI)
6.6.5.5 PM Data In Port (PMDI)
6.6.5.6 PM Data In Port with SCI# (PMDISCI)
6.6.5.7 PM Control (PMCTL)
6.6.5.8 PM Interrupt Control (PMIC)
6.6.5.9 PM Interrupt Enable (PMIE)
6.6.5.10 Mailbox Control (MBXCTRL)
6.6.5.11 PMC3 Status Register (PM3STS)
6.6.5.12 PMC3 Data Out Port (PM3DO)
6.6.5.13 PMC3 Data In Port (PM3DI)
6.6.5.14 PMC3 Control (PM3CTL)
6.6.5.15 PMC3 Interrupt Control (PM3IC)
6.6.5.16 PMC3 Interrupt Enable (PM3IE)
6.6.5.17 16-byte PMC2EX Mailbox 0-15 (MBXEC0-15)
6.7 Real-Time Clock (RTC)
6.7.1 Overview
6.7.2 Feature
6.7.3 Functional Description
6.7.3.1 Timekeeping
6.7.3.2 Update Cycles
6.7.3.3 Interrupts
6.7.4 Host Interface Registers
6.7.4.1 RTC Bank 0 Register
6.7.4.1.1 Seconds Register (SECREG)
6.7.4.1.2 Seconds Alarm 1 Register (SECA1REG)
6.7.4.1.3 Minutes Register (MINREG)
6.7.4.1.4 Minutes Alarm 1 Register (MINA1REG)
6.7.4.1.5 Hours Register (HRREG)
6.7.4.1.6 Hours Alarm 1 Register (HRA1REG)
6.7.4.1.7 Day Of Week Register (DOWREG)
6.7.4.1.8 Date Of Month Register (DOMREG)
6.7.4.1.9 Month Register (MONREG)
6.7.4.1.10 Year Register (YRREG)
6.7.4.1.11 RTC Control Register A (CTLREGA)
6.7.4.1.12 RTC Control Register B (CTLREGB)
6.7.4.1.13 RTC Control Register C (CTLREGC)
6.7.4.1.14 RTC Control Register D (CTLREGD)
6.7.4.1.15 Date of Month Alarm 1 Register (DOMA1REG)
6.7.4.1.16 Month Alarm 1 Register (MONA1REG)
6.7.4.2 RTC Bank 1 Register
6.7.4.2.1 Seconds Alarm 2 Register (SECA2REG)
6.7.4.2.2 Minutes Alarm 2 Register (MINA2REG)
6.7.4.2.3 Hours Alarm 2 Register (HRA2REG)
6.7.4.2.4 Date of Month Alarm 2 Register (DOMA2REG)
6.7.4.2.5 Month Alarm 2 Register (MONA2REG)
6.7.4.3 RTC I/O Register
6.7.4.3.1 RTC Index Register of Bank 0 (RIRB0)
6.7.4.3.2 RTC Data Register of Bank 0 (RDRB0)
6.7.4.3.3 RTC Index Register of Bank 1 (RIRB1)
6.7.4.3.4 RTC Data Register of Bank 1 (RDRB1)
6.8 Consumer IR (CIR) in Host Domain
6.8.1 Overview
6.9 Serial Peripheral Interface (SSPI) in Host Domain
6.9.1 Overview
6.10 Serial Port 1/2 (UART1/UART2) in Host Domain
6.10.1 Overview
7. EC Domain Functions
7.1 8032 Embedded Controller (EC)
7.1.1 Overview
7.1.2 Features
7.1.3 General Description
7.1.4 Functional Description
7.1.5 Memory Organization
7.1.6 On-Chip Peripherals
7.1.7 Timer / Counter
7.1.8 Idle and Doze/Sleep Mode
7.1.9 EC Internal Register Description
7.1.9.1 Port 0 Register (P0R)
7.1.9.2 Stack Pointer Register (SPR)
7.1.9.3 Data Pointer Low Register (DPLR)
7.1.9.4 Data Pointer High Register (DPHR)
7.1.9.5 Data Pointer 1 Low Register (DP1LR)
7.1.9.6 Data Pointer 1 High Register (DP1HR)
7.1.9.7 Data Pointer Select Register (DPSR)
7.1.9.8 Power Control Register (PCON)
7.1.9.9 Timer Control Register (TCON)
7.1.9.10 Timer Mode Register (TMOD)
7.1.9.11 Timer 0 Low Byte Register (TL0R)
7.1.9.12 Timer 1 Low Byte Register (TL1R)
7.1.9.13 Timer 0 High Byte Register (TH0R)
7.1.9.14 Timer 1 Low Byte Register (TH1R)
7.1.9.15 Clock Control Register (CKCON)
7.1.9.16 Port 1 Register (P1R)
7.1.9.17 Serial Port Control Register (SCON)
7.1.9.18 Serial Port Buffer Register (SBUFR)
7.1.9.19 Port 2 Register (P2R)
7.1.9.20 Interrupt Enable Register (IE)
7.1.9.21 Port 3 Register (P3R)
7.1.9.22 Interrupt Priority Register (IP)
7.1.9.23 Status Register (STATUS)
7.1.9.24 Timer 2 Control Register (T2CON)
7.1.9.25 Timer Mode Register (T2MOD)
7.1.9.26 Timer 2 Capture Low Byte Register (RCAP2LR)
7.1.9.27 Timer 2 Capture High Byte Register (RCAP2HR)
7.1.9.28 Timer 2 Low Byte Register (TL2R)
7.1.9.29 Timer 2 High Byte Register (TH2R)
7.1.9.30 Program Status Word Register (PSW)
7.1.9.31 Watch Dog Timer Control Register (WDTCON)
7.1.9.32 Accumulator Register (ACC)
7.1.9.33 B Register (BR)
7.1.9.34 Manual Prefetch Register (MPREFC)
7.1.10 Programming Guide
7.1.10.1 IT8516 Coding Consideration
7.1.10.2 Code Snippet of Entering Idle/Doze/Sleep Mode
7.1.10.3 Code snippet of Copying Flash Content to Scratch ROM 0 (PIO)
7.1.10.4 Code snippet of Copying Flash Content to Scratch ROM (DMA)
7.1.10.5 Code snippet of Changing PLL Frequency
7.1.10.6 Code snippet of Clearing Dynamic Caches
7.1.10.7 Code snippet of EC Base Signature
7.1.10.8 Code snippet of Sending EWSR+WRSR during HSPI Init
7.1.10.9 Code snippet of Sending WREN within ISR of INT59
7.2 Interrupt Controller (INTC)
7.2.1 Overview
7.2.2 Features
7.2.3 Functional Description
7.2.3.1 Power Fail Interrupt
7.2.3.2 ROM Match Interrupt
7.2.3.3 Programmable Interrupts
7.2.4 EC Interface Registers
7.2.4.1 Interrupt Status Register 0 (ISR0)
7.2.4.2 Interrupt Status Register 1 (ISR1)
7.2.4.3 Interrupt Status Register 2 (ISR2)
7.2.4.4 Interrupt Status Register 3 (ISR3)
7.2.4.5 Interrupt Status Register 4 (ISR4)
7.2.4.6 Interrupt Status Register 6 (ISR6)
7.2.4.7 Interrupt Status Register 7 (ISR7)
7.2.4.8 Interrupt Status Register 8 (ISR8)
7.2.4.9 Interrupt Status Register 9 (ISR9)
7.2.4.10 Interrupt Enable Register 0 (IER0)
7.2.4.11 Interrupt Enable Register 1 (IER1)
7.2.4.12 Interrupt Enable Register 2 (IER2)
7.2.4.13 Interrupt Enable Register 3 (IER3)
7.2.4.14 Interrupt Enable Register 4 (IER4)
7.2.4.15 Interrupt Enable Register 6 (IER6)
7.2.4.16 Interrupt Enable Register 7 (IER7)
7.2.4.17 Interrupt Enable Register 8 (IER8)
7.2.4.18 Interrupt Enable Register 9 (IER9)
7.2.4.19 Interrupt Edge/Level-Triggered Mode Register 0 (IELMR0)
7.2.4.20 Interrupt Edge/Level-Triggered Mode Register 1 (IELMR1)
7.2.4.21 Interrupt Edge/Level-Triggered Mode Register 2 (IELMR2)
7.2.4.22 Interrupt Edge/Level-Triggered Mode Register 3 (IELMR3)
7.2.4.23 Interrupt Edge/Level-Triggered Mode Register 4 (IELMR4)
7.2.4.24 Interrupt Edge/Level-Triggered Mode Register 6 (IELMR6)
7.2.4.25 Interrupt Edge/Level-Triggered Mode Register 7 (IELMR7)
7.2.4.26 Interrupt Edge/Level-Triggered Mode Register 8 (IELMR8)
7.2.4.27 Interrupt Edge/Level-Triggered Mode Register 9 (IELMR9)
7.2.4.28 Interrupt Polarity Register 0 (IPOLR0)
7.2.4.29 Interrupt Polarity Register 1 (IPOLR1)
7.2.4.30 Interrupt Polarity Register 2 (IPOLR2)
7.2.4.31 Interrupt Polarity Register 3 (IPOLR3)
7.2.4.32 Interrupt Polarity Register 4 (IPOLR4)
7.2.4.33 Interrupt Polarity Register 6 (IPOLR6)
7.2.4.34 Interrupt Polarity Register 7 (IPOLR7)
7.2.4.35 Interrupt Polarity Register 8 (IPOLR8)
7.2.4.36 Interrupt Polarity Register 9 (IPOLR9)
7.2.4.37 Interrupt Vector Register (IVCT)
7.2.4.38 8032 INT0# Status (INT0ST)
7.2.4.39 Power Fail Register (PFAILR)
7.2.5 INTC Interrupt Assignments
7.2.6 Programming Guide
7.3 Wake-Up Control (WUC)
7.3.1 Overview
7.3.2 Features
7.3.3 Functional Description
7.3.4 EC Interface Registers
7.3.4.1 Wake-Up Edge Mode Register 1 (WUEMR1)
7.3.4.2 Wake-Up Edge Mode Register 2 (WUEMR2)
7.3.4.3 Wake-Up Edge Mode Register 3 (WUEMR3)
7.3.4.4 Wake-Up Edge Mode Register 4 (WUEMR4)
7.3.4.5 Wake-Up Edge Mode Register 6 (WUEMR6)
7.3.4.6 Wake-Up Edge Mode Register 7 (WUEMR7)
7.3.4.7 Wake-Up Edge Sense Register 1 (WUESR1)
7.3.4.8 Wake-Up Edge Sense Register 2 (WUESR2)
7.3.4.9 Wake-Up Edge Sense Register 3 (WUESR3)
7.3.4.10 Wake-Up Edge Sense Register 4 (WUESR4)
7.3.4.11 Wake-Up Edge Sense Register 6 (WUESR6)
7.3.4.12 Wake-Up Edge Sense Register 7 (WUESR7)
7.3.4.13 Wake-Up Enable Register 1 (WUENR1)
7.3.4.14 Wake-Up Enable Register 2 (WUENR2)
7.3.4.15 Wake-Up Enable Register 3 (WUENR3)
7.3.4.16 Wake-Up Enable Register 4 (WUENR4)
7.3.4.17 Wake-Up Enable Register 6 (WUENR6)
7.3.4.18 Wake-Up Enable Register 7 (WUENR7)
7.3.5 WUC Input Assignments
7.3.6 Programming Guide
7.4 Keyboard Matrix Scan Controller
7.4.1 Overview
7.4.2 Features
7.4.3 Functional Description
7.4.4 EC Interface Registers
7.4.4.1 Keyboard Scan Out Low Byte Data Register (KSOL)
7.4.4.2 Keyboard Scan Out High Byte Data 1 Register (KSOH1)
7.4.4.3 Keyboard Scan Out Control Register (KSOCTRL)
7.4.4.4 Keyboard Scan Out High Byte Data 2 Register (KSOH2)
7.4.4.5 Keyboard Scan In Data Register (KSIR)
7.4.4.6 Keyboard Scan In Control Register (KSICTRLR)
7.4.4.7 Keyboard Scan In GPIO Control Register (KSIGCTRLR)
7.4.4.8 Keyboard Scan In GPIO Output Enable Register (KSIGOENR)
7.4.4.9 Keyboard Scan In GPIO Data Register (KSIGDATR)
7.4.4.10 Keyboard Scan In GPIO Data Mirror Register (KSIGDMRRR)
7.4.4.11 Keyboard Scan Out GPIO Control Register (KSOGCTRLR)
7.4.4.12 Keyboard Scan Out GPIO Output Enable Register (KSOGOENR)
7.4.4.13 Keyboard Scan Out GPIO Data Mirror Register (KSOGDMRRR)
7.5 General Purpose I/O Port (GPIO)
7.5.1 Overview
7.5.2 Features
7.5.3 EC Interface Registers
7.5.3.1 General Control Register (GCR)
7.5.3.2 General Control 1 Register (GCR1)
7.5.3.3 General Control 2 Register (GCR2)
7.5.3.4 General Control 3 Register (GCR3)
7.5.3.5 General Control 4 Register (GCR4)
7.5.3.6 Port Data Registers A-J (GPDRA-GPDRJ)
7.5.3.7 Port Data Mirror Registers A-J (GPDMRA-GPDMRJ)
7.5.3.8 Port Control n Registers (GPCRn, n = A0-I7)
7.5.3.9 Output Type Registers B/D/H (GPOTB/D/H)
7.5.4 Alternate Function Selection
7.5.5 Programming Guide
7.6 EC Clock and Power Management Controller (ECPM)
7.6.1 Overview
7.6.2 Features
7.6.3 EC Interface Registers
7.6.3.1 Clock Gating Control 1 Register (CGCTRL1R)
7.6.3.2 Clock Gating Control 2 Register (CGCTRL2R)
7.6.3.3 Clock Gating Control 3 Register (CGCTRL3R)
7.6.3.4 PLL Control (PLLCTRL)
7.6.3.5 Auto Clock Gating (AUTOCG)
7.6.3.6 PLL Frequency (PLLFREQR)
7.7 SMBus Interface (SMB)
7.7.1 Overview
7.7.2 Features
7.7.3 Functional Description
7.7.3.1 SMBus Master Interface
7.7.3.2 SMBus Slave Interface
7.7.3.3 SMBus Porting Guide
7.7.3.4 SMBus Master Programming Guide
7.7.3.5 Description of SMCLK and SMDAT Line Control in Software Mode
7.7.3.6 Description of SMBus Slave Interface Select
7.7.3.7 SMBus Waveform
7.7.4 EC Interface Registers
7.7.4.1 Host Status Register (HOSTA)
7.7.4.2 Host Control Register (HOCTL)
7.7.4.3 Host Command Register (HOCMD)
7.7.4.4 Transmit Slave Address Register (TRASLA)
7.7.4.5 Data 0 Register (D0REG)
7.7.4.6 Data 1 Register (D1REG)
7.7.4.7 Host Block Data Byte Register (HOBDB)
7.7.4.8 Packet Error Check Register (PECERC)
7.7.4.9 Receive Slave Address Register (RESLADR)
7.7.4.10 Slave Data Register (SLDA)
7.7.4.11 SMBus Pin Control Register (SMBPCTL)
7.7.4.12 Slave Status Register (SLSTA)
7.7.4.13 Slave Interrupt Control Register (SICR)
7.7.4.14 Notify Device Address Register (NDADR)
7.7.4.15 Notify Data Low Byte Register (NDLB)
7.7.4.16 Notify Data High Byte Register (NDHB)
7.7.4.17 Host Control Register 2 (HOCTL2)
7.7.4.18 Slave Interface Select Register (SLVISELR)
7.7.4.19 4.7 (s Low Register (4P7USL)
7.7.4.20 4.0 (s Low Register (4P0USL)
7.7.4.21 300 ns Register (300NSREG)
7.7.4.22 250 ns Register (250NSREG)
7.7.4.23 25 ms Register (25MSREG)
7.7.4.24 45.3 (s Low Register (45P3USLREG)
7.7.4.25 45.3 (s High Register (45P3USHREG)
7.7.4.26 4.7 (s And 4.0 (s High Register (4p7A4P0H)
7.8 Platform Environment Control Interface (PECI)
7.8.1 Overview
7.8.2 Features
7.8.3 Functional Description
7.8.3.1 PECI Porting Guide
7.8.3.2 PECI Programming Guide
7.8.4 EC Interface Registers
7.8.4.1 Host Status Register (HOSTAR)
7.8.4.2 Host Control Register (HOCTLR)
7.8.4.3 Host Command (Write Data 1) Register (HOCMDR)
7.8.4.4 Host Target Address Register (HOTRADDR)
7.8.4.5 Host Write Length Register (HOWRLR)
7.8.4.6 Host Read Length Register (HORDLR)
7.8.4.7 Host Write Data (2-16) Register (HOWRDR)
7.8.4.8 Host Read Data (1-16) Register (HORDDR)
7.9 PS/2 Interface
7.9.1 Overview
7.9.2 Features
7.9.3 Functional Description
7.9.3.1 Hardware Mode Selected
7.9.3.2 Software Mode Selected
7.9.4 EC Interface Registers
7.9.4.1 PS/2 Control Register 1-3 (PSCTL1-3)
7.9.4.2 PS/2 Interrupt Control Register 1-3 (PSINT1-3)
7.9.4.3 PS/2 Status Register 1-3 (PSSTS1-3)
7.9.4.4 PS/2 Data Register 1-3 (PSDAT1-3)
7.10 Digital To Analog Converter (DAC)
7.10.1 Overview
7.10.2 Feature
7.10.3 Functional Description
7.10.4 EC Interface Registers
7.10.4.1 DAC Power Down Register (DACPDREG)
7.10.4.2 DAC Data Channel 0~5 Register (DACDAT0~5)
7.11 Analog to Digital Converter (ADC)
7.11.1 Overview
7.11.2 Features
7.11.3 Functional Description
7.11.3.1 ADC General Description
7.11.3.2 Voltage Measurement and Automatic Hardware Calibration
7.11.3.3 ADC Operation
7.11.4 EC Interface Registers
7.11.4.1 ADC Status Register (ADCSTS)
7.11.4.2 ADC Configuration Register (ADCCFG)
7.11.4.3 ADC Clock Control Register (ADCCTL)
7.11.4.4 Voltage Channel 0 Control Register (VCH0CTL)
7.11.4.5 Calibration Data Control Register (KDCTL)
7.11.4.6 Voltage Channel 1 Control Register (VCH1CTL)
7.11.4.7 Volt Channel 1 Data Buffer LSB (VCH1DATL)
7.11.4.8 Volt Channel 1 Data Buffer MSB (VCH1DATM)
7.11.4.9 Voltage Channel 2 Control Register (VCH2CTL)
7.11.4.10 Volt Channel 2 Data Buffer LSB (VCH2DATL)
7.11.4.11 Volt Channel 2 Data Buffer MSB (VCH2DATM)
7.11.4.12 Voltage Channel 3 Control Register (VCH3CTL)
7.11.4.13 Volt Channel 3 Data Buffer LSB (VCH3DATL)
7.11.4.14 Volt Channel 3 Data Buffer MSB (VCH3DATM)
7.11.4.15 Volt High Scale Calibration Data Buffer LSB (VHSCDBL)
7.11.4.16 Volt High Scale Calibration Data Buffer MSB (VHSCDBM)
7.11.4.17 Voltage Channel 0 Data Buffer LSB (VCH0DATL)
7.11.4.18 Voltage Channel 0 Data Buffer MSB (VCH0DATM)
7.11.4.19 Volt High Scale Gain-Error Calibration Data Buffer LSB (VHSGCDBL)
7.11.4.20 Volt High Scale Gain-Error Calibration Data Buffer MSB (VHSGCDBM)
7.11.5 ADC Programming Guide
7.12 PWM
7.12.1 Overview
7.12.2 Features
7.12.3 Functional Description
7.12.3.1 General Description
7.12.3.2 Manual Fan Control Mode
7.12.4 EC Interface Registers
7.12.4.1 Channel 0 Clock Prescaler Register (C0CPRS)
7.12.4.2 Cycle Time Register 0 (CTR0)
7.12.4.3 Cycle Time Register 1 (CTR1)
7.12.4.4 Cycle Time Register 2 (CTR2)
7.12.4.5 Cycle Time Register 3 (CTR3)
7.12.4.6 PWM Duty Cycle Register 0 to 7(DCRi)
7.12.4.7 PWM Polarity Register (PWMPOL)
7.12.4.8 Prescaler Clock Frequency Select Register (PCFSR)
7.12.4.9 Prescaler Clock Source Select Group Low (PCSSGL)
7.12.4.10 Prescaler Clock Source Select Group High (PCSSGH)
7.12.4.11 Prescaler Clock Source Gating Register (PCSGR)
7.12.4.12 Fan 1 Tachometer LSB Reading Register (F1TLRR)
7.12.4.13 Fan 1 Tachometer MSB Reading Register (F1TMRR)
7.12.4.14 Fan 2 Tachometer LSB Reading Register (F2TLRR)
7.12.4.15 Fan 2 Tachometer MSB Reading Register (F2TMRR)
7.12.4.16 Zone Interrupt Status Control Register (ZINTSCR)
7.12.4.17 PWM Clock Control Register (ZTIER)
7.12.4.18 Channel 4 Clock Prescaler Register (C4CPRS)
7.12.4.19 Channel 4 Clock Prescaler MSB Register (C4MCPRS)
7.12.4.20 Channel 6 Clock Prescaler Register (C6CPRS)
7.12.4.21 Channel 6 Clock Prescaler MSB Register (C6MCPRS)
7.12.4.22 Channel 7 Clock Prescaler Register (C7CPRS)
7.12.4.23 Channel 7 Clock Prescaler MSB Register (C7MCPRS)
7.12.4.24 PWM Clock 6MHz Select Register (CLK6MSEL)
7.12.5 PWM Programming Guide
7.13 8-bit Timer (TMR)
7.13.1 Overview
7.13.2 Features
7.13.3 Functional Description
7.13.3.1 General Description
7.13.3.2 TMR Counter (CNT)
7.13.3.3 TMR Duty Cycle (DCR)
7.13.3.4 TMR Cycle Time (CTR)
7.13.3.5 TMR Mode
7.13.3.6 TMR Interrupt
7.13.4 EC Interface Registers
7.13.4.1 TMR Prescaler Register (PRSC)
7.13.4.2 Group Clock Source and Mode Select Register (GCSMS)
7.13.4.3 A0 Cycle Time Register (CTR_A0)
7.13.4.4 A1 Cycle Time Register (CTR_A1)
7.13.4.5 B0 Cycle Time Register (CTR_B0)
7.13.4.6 B1 Cycle Time Register (CTR_B1)
7.13.4.7 A0 Duty Cycle Register (DCR_A0)
7.13.4.8 A1 Duty Cycle Register (DCR_A1)
7.13.4.9 B0 Duty Cycle Register (DCR_B0)
7.13.4.10 B1 Duty Cycle Register (DCR_B1)
7.13.4.11 Channel Clock Group Select Register (CCGSR)
7.13.4.12 TMR Clock Enable Register (TMRCE)
7.13.4.13 TMR Interrupt Enable Register (TMRIE)
7.13.5 TMR Programming Guide
7.14 EC Access to Host Controlled Modules (EC2I Bridge)
7.14.1 Overview
7.14.2 Features
7.14.3 Functional Description
7.14.4 EC Interface Registers
7.14.4.1 Indirect Host I/O Address Register (IHIOA)
7.14.4.2 Indirect Host Data Register (IHD)
7.14.4.3 Lock Super I/O Host Access Register (LSIOHA)
7.14.4.4 Super I/O Access Lock Violation Register (SIOLV)
7.14.4.5 EC to I-Bus Modules Access Enable Register (IBMAE)
7.14.4.6 I-Bus Control Register (IBCTL)
7.14.5 EC2I Programming Guide
7.15 External Timer and External Watchdog (ETWD)
7.15.1 Overview
7.15.2 Features
7.15.3 Functional Description
7.15.3.1 External Timer Operation
7.15.3.2 External WDT Operation
7.15.4 EC Interface Registers
7.15.4.1 External Timer 1/WDT Configuration Register (ETWCFG)
7.15.4.2 External Timer 1 Prescaler Register (ET1PSR)
7.15.4.3 External Timer 1 Counter High Byte (ET1CNTLHR)
7.15.4.4 External Timer 1 Counter Low Byte (ET1CNTLLR)
7.15.4.5 External Timer 2 Prescaler Register (ET2PSR)
7.15.4.6 External Timer 2 Counter High Byte (ET2CNTLHR)
7.15.4.7 External Timer 2 Counter Low Byte (ET2CNTLLR)
7.15.4.8 External Timer 2 Counter High Byte 2 (ET2CNTLH2R)
7.15.4.9 External Timer/WDT Control Register (ETWCTRL)
7.15.4.10 External WDT Counter High Byte (EWDCNTLHR)
7.15.4.11 External WDT Counter Low Byte (EWDCNTLLR)
7.15.4.12 External WDT Key Register (EWDKEYR)
7.16 General Control (GCTRL)
7.16.1 Overview
7.16.2 Features
7.16.3 Functional Description
7.16.4 EC Interface Registers
7.16.4.1 Chip ID Byte 1 (ECHIPID1)
7.16.4.2 Chip ID Byte 2 (ECHIPID2)
7.16.4.3 Chip Version (ECHIPVER)
7.16.4.4 Identify Input Register (IDR)
7.16.4.5 Reset Status (RSTS)
7.16.4.6 Reset Control 1 (RSTC1)
7.16.4.7 Reset Control 2 (RSTC2)
7.16.4.8 Reset Control 3 (RSTC3)
7.16.4.9 Reset Control 4 (RSTC4)
7.16.4.10 Reset Control DMM (RSTDMMC)
7.16.4.11 Base Address Select (BADRSEL)
7.16.4.12 Wait Next Clock Rising (WNCKR)
7.16.4.13 Oscillator Control Register (OSCTRL)
7.16.4.14 Special Control 1 (SPCTRL1)
7.16.4.15 Reset Control Host Side (RSTCH)
7.16.4.16 Generate IRQ (GENIRQ)
7.17 External GPIO Controller (EGPC)
7.17.1 Overview
7.17.2 Features
7.17.3 Functional Description
7.17.4 EC Interface Registers
7.17.4.1 External GPIO Address Register (EADDR)
7.17.4.2 External GPIO Data Register (EDAT).
7.17.4.3 External GPIO Control Register (ECNT).
7.17.4.4 External GPIO Status Register (ESTS).
7.18 Battery-backed SRAM (BRAM)
7.18.1 Overview
7.18.2 Features
7.18.3 Functional Description
7.18.3.1 P80L
7.18.4 EC Interface Registers
7.18.4.1 SRAM Byte n Registers (SBTn, n= 0-191).
7.19 Consumer IR (CIR)
7.19.1 Overview
7.19.2 Features
7.19.3 Functional Description
7.19.3.1 Transmit Operation
7.19.3.2 Receive Operation
7.19.3.3 Wakeup (Power On) Controller Programming Sequence
7.19.4 Host Interface Registers
7.19.5 EC Interface Registers
7.19.5.1 CIR Data Register (C0DR)
7.19.5.2 CIR Master Control Register (C0MSTCR)
7.19.5.3 CIR Interrupt Enable Register (C0IER)
7.19.5.4 CIR Interrupt Identification Register (C0IIR)
7.19.5.5 CIR Carrier Frequency Register (C0CFR)
7.19.5.6 CIR Receiver Control Register (C0RCR)
7.19.5.7 CIR Transmitter Control Register (C0TCR)
7.19.5.8 CIR Slow Clock Control Register (C0SCK)
7.19.5.9 CIR Baud Rate Divisor Low Byte Register (C0BDLR)
7.19.5.10 CIR Baud Rate Divisor High Byte Register (C0BDHR)
7.19.5.11 CIR Transmitter FIFO Status Register (C0TFSR)
7.19.5.12 CIR Receiver FIFO Status Register (C0RFSR)
7.19.5.13 CIR Wake-Code Set Select Register (C0WCSSR)
7.19.5.14 CIR Wakeup Code Length Register (C0WCL)
7.19.5.15 CIR Wakeup Code Read/Write Register (C0WCR)
7.19.5.16 CIR Wakeup Power Control/Status Register (C0WPS)
7.19.5.17 CIR Scratch Register (CSCRR)
7.19.5.18 CIR General Purpose Interrupt (CGPINTR)
7.20 Serial Peripheral Interface (SSPI)
7.20.1 Overview
7.20.2 Features
7.20.3 Functional Description
7.20.3.1 Data Transmissions
7.20.3.2 SPI Mode
7.20.3.3 Blocking and Non-blocking mode
7.20.4 Host Interface Registers
7.20.5 EC Interface Registers
7.20.5.1 SPI Data Register (SPIDATA)
7.20.5.2 SPI Control Register 1 (SPICTRL1)
7.20.5.3 SPI Control Register 2 (SPICTRL2)
7.20.5.4 SPI Start and End Status Register (SPISTS)
7.20.5.5 SPI Control Register 3 (SPICTRL3)
7.20.6 Programming Guide
7.21 Serial Port (UART)
7.21.1 Overview
7.21.2 Features
7.21.3 Functional Description
7.21.4 Host Interface Registers
7.21.5 EC Interface Registers
7.21.5.1 Receiver Buffer Register (RBR)
7.21.5.2 Transmitter Holding Register (THR)
7.21.5.3 Interrupt Enable Register (IER)
7.21.5.4 Interrupt Identification Register (IIR)
7.21.5.5 FIFO Control Register (FCR)
7.21.5.6 Divisor Latch LSB (DLL)
7.21.5.7 Divisor Latch MSB (DLM)
7.21.5.8 Scratch Pad Register (SCR)
7.21.5.9 Line Control Register (LCR)
7.21.5.10 Modem Control Register (MCR)
7.21.5.11 Line Status Register (LSR)
7.21.5.12 Modem Status Register (MSR)
7.21.5.13 EC Serial Port Mode Register (ECSPMR)
7.21.6 Programming Guide
7.21.6.1 Programming Sequence
7.21.7 Software Reset
7.21.8 Clock Input Operation
7.21.9 FIFO Interrupt Mode Operation
7.21.10 High Speed Baud Rate Activation
7.22 Debugger (DBGR)
7.22.1 Overview
7.22.2 Features
7.22.3 Functional Description
7.22.3.1 ROM Address Match Interrupt
7.22.3.2 EC Memory Snoop (ECMS)
7.22.4 EC Interface Registers
7.22.4.1 Trigger 1 Address Low Byte Register (BKA1L)
7.22.4.2 Trigger 1 Address Middle Byte Register (BKA1M)
7.22.4.3 Trigger 1 Address High Byte Register (BKA1H)
7.22.4.4 Trigger 2 Address Low Byte Register (BKA2L)
7.22.4.5 Trigger 2 Address Middle Byte Register (BKA2M)
7.22.4.6 Trigger 2 Address High Byte Register (BKA2H)
7.22.4.7 Trigger 3 Address Low Byte Register (BKA3L)
7.22.4.8 Trigger 3 Address Middle Byte Register (BKA3M)
7.22.4.9 Trigger 3 Address High Byte Register (BKA3H)
7.23 Parallel Port (PP)
7.23.1 Overview
7.23.2 Features
7.23.3 Functional Description
7.23.3.1 KBS Connection with Parallel Port Connector
7.23.3.2 In-System Programming Operation
8. Register List
9. DC Characteristics
10. AC Characteristics
11. Analog Device Characteristics
12. Package Information
13. Ordering Information
14. Top Marking Information
IT8516E/F/G
Preliminary Specification V0.5.3
Embedded Controller
(For F Version)
ITE TECH. INC.
This specification is subject to Change without notice. It is provided “AS IS” and for reference only. For
purchasing information, please contact the nearest sales representatives.
Please note that the IT8516E/F/G V0.4.3 is applicable to the F version.
Copyright © 2009 ITE Tech. Inc.
This is a Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous material issued for the products herein
referenced. Please contact ITE Tech. Inc. for the latest document(s).
All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE, IT8516E/F/G is a trademark of ITE Tech. Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
If you have any marketing or sales questions, please contact:
P.Y. Chang, at ITE Taiwan:
E-mail: p.y.chang@ite.com.tw, Tel: 886-2-29126889 X6052, Fax: 886-2-29102551
You may also find the local sales representative nearest you on the ITE web site.
To find out more about ITE, visit our World Wide Web at:
http://www.ite.com.tw
Or e-mail itesupport@ite.com.tw for more product information/services
ITE Tech. Inc.
Marketing Department
7F, No.233-1, Baociao Rd., Sindian City,
Taipei County 23145, Taiwan, ROC
Phone:
Fax:
(02) 29126889
(02) 2910-2551, 2910-2552
Revision History
Revision History
Revision
Added PECI host. Refer to section 7.8 Platform Environment Control
Interface (PECI).
Added PECI and PECIRQT# pins
GPF6 is not 5V tolerant after this modification.
6.3.4.11 HSPI Control Register 3 (HSPICTRL3R)
7.7.4.10 Slave Data Register (SLDA)
7.7.4.11 SMBus Pin Control Register (SMBPCTL)
SMFI: Added new register.
SMB: Changed register definition.
SMB: Added new register bit 4. Changed the definition of bit 3.
SMB: Added new register bit 2.
SMB: Added new register bit 4.
7.7.4.13 Slave Interrupt Control Register (SICR)
7.7.4.17 Host Control Register 2 (HOCTL2)
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IT8516E/F/G V0.4.3
Contents
CONTENTS
1. Features
. ................................................................................................................................. 1
2. General Description ....................................................................................................................................... 3
3. System Block Diagram................................................................................................................................... 5
3.1 Block Diagram..................................................................................................................................... 5
3.2 Host/EC Mapped Memory Space ....................................................................................................... 6
3.3 EC Mapped Memory Space................................................................................................................ 9
3.4 Register Abbreviation........................................................................................................................ 10
4. Pin Configuration ......................................................................................................................................... 11
4.1 Top View ........................................................................................................................................... 11
5. Pin Descriptions ........................................................................................................................................... 17
5.1 Pin Descriptions ................................................................................................................................ 17
5.2 Chip Power Planes and Power States.............................................................................................. 24
5.3 Pin Power Planes and States ........................................................................................................... 25
5.4 PWRFAIL# Interrupt to INTC ........................................................................................................... 29
5.5 Reset Sources and Types................................................................................................................. 30
5.5.1 Related Interrupts to INTC ................................................................................................... 30
5.6 Chip Power Mode and Clock Domain............................................................................................... 31
5.7 Pins with Pull, Schmitt-Trigger or Open-Drain Function ................................................................... 35
5.8 Power Consumption Consideration .................................................................................................. 36
6. Host Domain Functions................................................................................................................................ 39
6.1 Low Pin Count Interface.................................................................................................................... 39
6.1.1 Overview............................................................................................................................... 39
6.1.2 Features ............................................................................................................................... 39
6.1.3 Accepted LPC Cycle Type ................................................................................................... 39
6.1.4 Debug Port Function ............................................................................................................ 40
6.1.5 Serialized IRQ (SERIRQ)..................................................................................................... 40
6.1.6 Related Interrupts to WUC ................................................................................................... 40
6.1.7 LPCPD# and CLKRUN#....................................................................................................... 40
6.1.8 Check Items.......................................................................................................................... 41
6.2 Plug and Play Configuration (PNPCFG)........................................................................................... 42
6.2.1 Logical Device Assignment .................................................................................................. 45
6.2.2 Super I/O Configuration Registers ....................................................................................... 46
6.2.2.1 Logical Device Number (LDN)................................................................................. 46
6.2.2.2 Chip ID Byte 1 (CHIPID1)........................................................................................ 46
6.2.2.3 Chip ID Byte 2 (CHIPID2)........................................................................................ 46
6.2.2.4 Chip Version (CHIPVER)......................................................................................... 46
6.2.2.5 Super I/O Control Register (SIOCTRL) ................................................................... 46
6.2.2.6 Super I/O IRQ Configuration Register (SIOIRQ)..................................................... 47
6.2.2.7 Super I/O General Purpose Register (SIOGP)........................................................ 47
6.2.2.8 Super I/O Power Mode Register (SIOPWR) ........................................................... 48
6.2.3 Standard Logical Device Configuration Registers................................................................ 48
6.2.3.1 Logical Device Activate Register (LDA)................................................................... 48
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 48
6.2.3.2
6.2.3.3
I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 49
I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 49
6.2.3.4
I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 49
6.2.3.5
6.2.3.6
Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 49
6.2.3.7
Interrupt Request Type Select (IRQTP) .................................................................. 50
6.2.3.8 DMA Channel Select 0 (DMAS0) ............................................................................ 50
6.2.3.9 DMA Channel Select 1 (DMAS1) ............................................................................ 50
6.2.4 Serial Port 1 (UART1) Configuration Registers.................................................................... 51
6.2.4.1 Logical Device Activate Register (LDA)................................................................... 51
IT8516E/F/G V0.4.3
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IT8516E/F/G (For F Version)
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 51
6.2.4.2
I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 51
6.2.4.3
I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 51
6.2.4.4
I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 52
6.2.4.5
Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 52
6.2.4.6
6.2.4.7
Interrupt Request Type Select (IRQTP) .................................................................. 52
6.2.4.8 High Speed Baud Rate Select (HHS)...................................................................... 52
6.2.5 Serial Port 2 (UART2) Configuration Registers.................................................................... 53
6.2.5.1 Logical Device Activate Register (LDA)................................................................... 53
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 53
6.2.5.2
I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 53
6.2.5.3
6.2.5.4
I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 53
6.2.5.5
I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 54
6.2.5.6
Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 54
6.2.5.7
Interrupt Request Type Select (IRQTP) .................................................................. 54
6.2.5.8 High Speed Baud Rate Select (HHS)...................................................................... 54
6.2.6 System Wake-Up Control (SWUC) Configuration Registers ............................................... 55
6.2.6.1 Logical Device Activate Register (LDA)................................................................... 55
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 55
6.2.6.2
I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 55
6.2.6.3
6.2.6.4
I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 55
6.2.6.5
I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 56
Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 56
6.2.6.6
6.2.6.7
Interrupt Request Type Select (IRQTP) .................................................................. 56
6.2.7 KBC / Mouse Interface Configuration Registers .................................................................. 57
6.2.7.1 Logical Device Activate Register (LDA)................................................................... 57
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 57
6.2.7.2
I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 57
6.2.7.3
6.2.7.4
I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 57
6.2.7.5
I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 58
6.2.7.6
Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 58
6.2.7.7
Interrupt Request Type Select (IRQTP) .................................................................. 58
6.2.8 KBC / Keyboard Interface Configuration Registers.............................................................. 59
6.2.8.1 Logical Device Activate Register (LDA)................................................................... 59
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 59
6.2.8.2
6.2.8.3
I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 59
I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 59
6.2.8.4
6.2.8.5
I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 59
6.2.8.6
Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 60
6.2.8.7
Interrupt Request Type Select (IRQTP) .................................................................. 60
6.2.9 Consumer IR Configuration Registers ................................................................................. 61
6.2.9.1 Logical Device Activate Register (LDA)................................................................... 61
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 61
6.2.9.2
6.2.9.3
I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 61
Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 61
6.2.9.4
6.2.9.5
Interrupt Request Type Select (IRQTP) .................................................................. 61
6.2.10 Shared Memory/Flash Interface (SMFI) Configuration Registers........................................ 62
6.2.10.1 Logical Device Activate Register (LDA)................................................................... 62
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 62
6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 62
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 62
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 63
6.2.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 63
6.2.10.7 Interrupt Request Type Select (IRQTP) .................................................................. 63
6.2.10.8 Shared Memory Configuration Register (SHMC) .................................................... 63
6.2.10.9 H2RAM-HLPC Base Address [15:12] (HLPCRAMBA[15:12])................................. 63
6.2.10.10 H2RAM-HLPC Base Address [23:16] (HLPCRAMBA[23:16])................................. 63
IT8516E/F/G V0.4.3
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