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PIPE4: PHY inteface for Pcie.pdf
1 Preface
1.1 Scope of this Revision
1.2 Revision History
2 Introduction
2.1 PCI Express PHY Layer
2.2 USB PHY Layer
2.3 SATA PHY Layer
3 PHY/MAC Interface
4 PCI Express and USB PHY Functionality
4.1 Transmitter Block Diagram (2.5 and 5.0 GT/s)
4.2 Transmitter Block Diagram (8.0/10 GT/s)
4.3 Receiver Block Diagram (2.5 and 5.0 GT/s)
4.4 Receiver Block Diagram (8.0/10.0 GT/s)
4.5 Clocking
5 SATA PHY Functionality
5.1 Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s)
5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s)
5.3 Clocking
6 PIPE Interface Signal Descriptions
6.1 PHY/MAC Interface Signals
6.1.1 Message Bus Interface
6.1.1.1 Message Bus Interface Commands
6.1.1.2 Message Bus Interface Framing
6.2 External Signals
7 PIPE Message Bus Address Spaces
7.1 PHY Registers
7.1.1 Address 0h: RX Margin Control0
7.1.2 Address 1h: RX Margin Control1
7.1.3 Address 2h: Elastic Buffer Control
7.2 MAC Registers
7.2.1 Address 0h: RX Margin Status0
7.2.2 Address 1h: RX Margin Status1
7.2.3 Address 2h: RX Margin Status2
7.2.4 Address 3h: Elastic Buffer Status
1
8 PIPE Operational Behavior
8.1 Clocking
8.2 Reset
8.3 Power Management – PCI Express Mode
1.1
8.4 Power Management – USB Mode
8.5 Power Management – SATA Mode
8.6 Changing Signaling Rate, PCLK Rate, or Data Bus Width
8.6.1 PCI Express Mode
8.6.2 USB Mode
8.6.3 SATA Mode
8.6.4 Fixed data path implementations
8.6.5 Fixed PCLK implementations
8.7 Transmitter Margining – PCI Express Mode and USB Mode
8.8 Selectable De-emphasis – PCI Express Mode
8.9 Receiver Detection – PCI Express Mode and USB Mode
8.10 Transmitting a beacon – PCI Express Mode
8.11 Transmitting LFPS – USB Mode
8.12 Detecting a beacon – PCI Express Mode
8.13 Detecting Low Frequency Periodic Signaling – USB Mode
8.14 Clock Tolerance Compensation
8.15 Error Detection
8.15.1 8B/10B Decode Errors
8.15.2 Disparity Errors
8.15.3 Elastic Buffer Errors
8.16 Loopback
8.17 Polarity Inversion – PCI Express and USBModes
8.18 Setting negative disparity (PCI Express Mode)
8.19 Electrical Idle – PCI Express Mode
8.20 Link Equalization Evaluation
8.21 Implementation specific timing and selectable parameter support
8.22 Control Signal Decode table – PCI Express Mode
8.23 Control Signal Decode table – USB Mode
8.24 Control Signal Decode table – SATA Mode
8.25 Required synchronous signal timings
8.26 128b/130b Encoding and Block Synchronization (PCI Express 8 GT/s)
8.27 128b/132b Encoding and Block Synchronization (USB 10 GT/s)
8.28 Message Bus Interface
9 Sample Operational Sequences
9.1 Active PM L0 to L0s and back to L0 – PCI Express Mode
9.2 Active PM to L1 and back to L0 - – PCI Express Mode
9.3 Receivers and Electrical Idle – PCI Express Mode Example
9.4 Using CLKREQ# with PIPE – PCI Express Mode
9.5 RX Margining Sequence
PHY Interface
For the
PCI Express, SATA, and USB 3.1
Architectures
Version 4.4
©2007 - 2016 Intel Corporation—All rights reserved.
PHY Interface for PCI Express, SATA, and USB 3.1 Architectures, ver 4.4
Intellectual Property Disclaimer
THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES
WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS
FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING
OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE.
A COPYRIGHT LICENSE IS HEREBY GRANTED TO REPRODUCE AND
DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER
LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY
OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED
HEREBY.
INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION DISCLAIM
ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF
PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION
IN THIS DOCUMENT AND THE SPECIFICATION. INTEL CORPORATION AND
THE AUTHORS OF THIS SPECIFICATION ALSO DO NOT WARRANT OR
REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH
RIGHTS.
ALL SUGGESTIONS OR FEEDBACK RELATED TO THIS SPECIFICATION
BECOME THE PROPERTY OF INTEL CORPORATION UPON SUBMISSION.
INTEL CORPORATION MAY MAKE CHANGES TO SPECIFICATIONS, PRODUCT
DESCRIPTIONS, AND PLANS AT ANY TIME, WITHOUT NOTICE.
Notice: Implementations developed using the information provided in this specification may
infringe the patent rights of various parties including the parties involved in the development of
this specification. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights (including without limitation rights under any party’s patents) are granted herein.
All product names are trademarks, registered trademarks, or service marks of their respective
owners
Contributors
Jeff Morris
Andy Martwick
Brad Hosler
Matthew Myers
Bob Dunstan
Saleem Mohammad Peter Teng
Sue Vining
Tadashi Iwasaki
Yoichi Iizuka
Rahman Ismail
Ben Graniello
Michelle Jen
Bruce Tennant
Quinn Devine
Su Wei Lim
Hooi Kar Loo
Poh Thiam Teoh
Sathyanarayanan Gopal
Siang Lin Tan
Jake Li
Zeeshan Sarwar
Jim Choate
Paul Mattos
Dan Froelich
Duane Quiet
Hajime Nozaki
Karthi Vadivelu
Mineru Nishizawa
Takanori Saeki
Andrew Lillie
Frank Kavanagh
©2007-2016 Intel Corporation – All rights reserved
Page 2 of 114
PHY Interface for PCI Express, SATA, and USB 3.1 Architectures, ver 4.4
Dedicated to the memory of Brad Hosler, the impact of
whose accomplishments made the Universal Serial Bus
one of the most successful technology innovations of
the Personal Computer era.
©2007-2016 Intel Corporation – All rights reserved
Page 3 of 114
PHY Interface for PCI Express, SATA, and USB 3.1 Architectures, ver 4.4
Table of Contents
2
6.1
1 Preface ...................................................................................................................................... 8
1.1
Scope of this Revision ...................................................................................................... 8
1.2 Revision History ............................................................................................................... 8
Introduction ............................................................................................................................ 10
2.1
PCI Express PHY Layer ................................................................................................. 12
2.2 USB PHY Layer ............................................................................................................. 13
2.3
SATA PHY Layer ........................................................................................................... 13
3 PHY/MAC Interface .............................................................................................................. 14
4 PCI Express and USB PHY Functionality ............................................................................. 19
Transmitter Block Diagram (2.5 and 5.0 GT/s) .............................................................. 19
4.1
4.2
Transmitter Block Diagram (8.0/10 GT/s) ...................................................................... 20
4.3 Receiver Block Diagram (2.5 and 5.0 GT/s) .................................................................. 21
4.4 Receiver Block Diagram (8.0/10.0 GT/s) ....................................................................... 22
4.5 Clocking .......................................................................................................................... 22
5 SATA PHY Functionality ...................................................................................................... 23
5.1
Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ..................................................... 24
5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ........................................................... 25
5.3 Clocking .......................................................................................................................... 25
6 PIPE Interface Signal Descriptions ........................................................................................ 26
PHY/MAC Interface Signals .......................................................................................... 26
6.1.1 Message Bus Interface ............................................................................................. 60
6.1.1.1 Message Bus Interface Commands .................................................................. 61
6.1.1.2 Message Bus Interface Framing ....................................................................... 63
External Signals .............................................................................................................. 64
7 PIPE Message Bus Address Spaces ....................................................................................... 67
PHY Registers ................................................................................................................. 67
7.1.1 Address 0h: RX Margin Control0 ............................................................................ 67
7.1.2 Address 1h: RX Margin Control1 ............................................................................ 68
7.2 MAC Registers................................................................................................................ 68
7.2.1 Address 0h: RX Margin Status0 .............................................................................. 69
7.2.2 Address 1h: RX Margin Status1 .............................................................................. 69
7.2.3 Address 2h: RX Margin Status2 .............................................................................. 70
8 PIPE Operational Behavior .................................................................................................... 70
8.1 Clocking .......................................................................................................................... 70
8.2 Reset ................................................................................................................................ 71
Power Management – PCI Express Mode ...................................................................... 71
8.3
Power Management – USB Mode .................................................................................. 74
8.4
8.5
Power Management – SATA Mode ................................................................................ 75
8.6 Changing Signaling Rate, PCLK Rate, or Data Bus Width ............................................ 76
8.6.1
PCI Express Mode ................................................................................................... 76
8.6.2 USB Mode ............................................................................................................... 76
SATA Mode ............................................................................................................ 77
8.6.3
8.6.4
Fixed data path implementations ............................................................................. 77
Fixed PCLK implementations ................................................................................. 78
8.6.5
Transmitter Margining – PCI Express Mode and USB Mode ........................................ 79
8.7
8.8
Selectable De-emphasis – PCI Express Mode ................................................................ 79
8.9 Receiver Detection – PCI Express Mode and USB Mode .............................................. 80
Transmitting a beacon – PCI Express Mode ............................................................... 81
8.10
8.11
Transmitting LFPS – USB Mode ................................................................................ 81
6.2
7.1
©2007-2016 Intel Corporation – All rights reserved
Page 4 of 114
PHY Interface for PCI Express, SATA, and USB 3.1 Architectures, ver 4.4
8.12
8.13
8.14
8.15
Detecting a beacon – PCI Express Mode .................................................................... 82
Detecting Low Frequency Periodic Signaling – USB Mode ....................................... 82
Clock Tolerance Compensation .................................................................................. 82
Error Detection ............................................................................................................ 85
8.15.1 8B/10B Decode Errors ............................................................................................. 85
8.15.2 Disparity Errors ....................................................................................................... 86
8.15.3 Elastic Buffer Errors ................................................................................................ 86
Loopback ..................................................................................................................... 87
8.16
Polarity Inversion – PCI Express and USBModes ...................................................... 89
8.17
Setting negative disparity (PCI Express Mode) .......................................................... 89
8.18
Electrical Idle – PCI Express Mode ............................................................................ 90
8.19
Link Equalization Evaluation ...................................................................................... 91
8.20
Implementation specific timing and selectable parameter support ............................. 92
8.21
Control Signal Decode table – PCI Express Mode ................................................... 100
8.22
Control Signal Decode table – USB Mode ............................................................... 102
8.23
Control Signal Decode table – SATA Mode ............................................................. 102
8.24
Required synchronous signal timings ........................................................................ 103
8.25
128b/130b Encoding and Block Synchronization (PCI Express 8 GT/s) .................. 103
8.26
8.27
128b/132b Encoding and Block Synchronization (USB 10 GT/s) ............................ 105
8.28 Message Bus Interface .............................................................................................. 105
9 Sample Operational Sequences ............................................................................................ 105
9.1 Active PM L0 to L0s and back to L0 – PCI Express Mode .......................................... 106
9.2 Active PM to L1 and back to L0 - – PCI Express Mode .............................................. 107
9.3 Receivers and Electrical Idle – PCI Express Mode Example ....................................... 108
9.4 Using CLKREQ# with PIPE – PCI Express Mode ....................................................... 109
9.5 RX Margining Sequence ............................................................................................... 110
©2007-2016 Intel Corporation – All rights reserved
Page 5 of 114
PHY Interface for PCI Express, SATA, and USB 3.1 Architectures, ver 4.4
Table of Figures
Figure 2-1: Partitioning PHY Layer for PCI Express .................................................................... 11
Figure 2-2 Partitioning PHY Layer for USB ................................................................................. 12
Figure 3-1: PHY/MAC Interface ................................................................................................... 14
Figure 4-1: PHY Functional Block Diagram ................................................................................. 19
Figure 4-2: Transmitter Block Diagram ........................................................................................ 19
Figure 4-3: Transmitter Block Diagram (8.0/10 GT/s) ................................................................. 20
Figure 4-4: Receiver Block Diagram ............................................................................................ 21
Figure 4-5: Receiver Block Diagram (8.0 GT/s) ........................................................................... 22
Figure 4-6: Clocking and Power Block Diagram .......................................................................... 22
Figure 5-1: PHY Functional Block Diagram ................................................................................. 23
Figure 5-2: Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) .................................................. 24
Figure 5-3: Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ....................................................... 25
Figure 5-4: Clocking and Power Block Diagram .......................................................................... 25
Figure 6-1 – PCI Express 3.0 Example Timings For BlockAlignControl ..................................... 60
Figure 6-2. Command Only Message Bus Transaction Timing (NOP, write_ack) ....................... 63
Figure 6-3. Command+Address Message Bus Transaction Timing (Read) .................................. 63
Figure 6-4. Command+Data Message Bus Transaction Timing (Read completion) .................... 63
Figure 6-5. Command+Address+Data Message Bus Transaction Timing (Write_uncommitted,
Write_committed) .................................................................................................................. 63
Figure 6-6. Message Bus Transaction Framing ............................................................................ 64
Figure 8-1 PCI Express P2 Entry and Exit with PCLK as PHY Output ....................................... 73
Figure 8-2PCI Express P2 Entry and Exit with PCLK as PHY Input ........................................... 73
Figure 8-3 Change from PCI Express 2.5 Gt/s to 5.0 Gt/s with PCLK as PHY Input. ................. 78
Figure 8-4 – PCI Express 3.0 TxDataValid Timings for Electrical Idle Exit and Entry. .............. 91
Figure 8-5. Data Throttling and TxElecIdle ................................................................................. 91
Figure 8-6 – PCI Express 3.0 Successful Equalization Evaluation Request ................................. 92
Figure 8-7 – PCI Express 3.0 Equalization Evaluation Request Resulting in Invalid Feedback .. 92
Figure 8-8 – PCI Express 3.0 TxDataValid Timing for 8 Bit Wide TxData Interface ................ 104
Figure 8-9 – PCI Express 3.0 TxDataValid Timing for 16 Bit Wide TxData Interface .............. 104
Figure 8-10 – PCI Express 3.0 RxDataValid Timing for 16 Bit Wide RxData Interface ........... 104
Figure 9-1. Sample RX Margining Sequence .............................................................................. 111
Table of Tables
Table 3-1 SATA Mode – Possible PCLK rates and data widths .................................................. 16
Table 3-2. PCI Express Mode - Possible PCLK rates and data widths ........................................ 17
Table 3-3. USB Mode – Possible PCLK rates and data widths.................................................... 17
Table 6-1: Transmit Data Interface Signals ................................................................................... 26
Table 6-2: Receive Data Interface Signals .................................................................................... 28
Table 6-3: Command Interface Signals ......................................................................................... 30
Table 6-4: Status Interface Signals ................................................................................................ 53
Table 6-5 Message Bus Interface Signals ..................................................................................... 60
Table 6-6 Message Bus Commands .............................................................................................. 61
Table 6-7: External Signals ........................................................................................................... 64
Table 7-1 PHY Registers ............................................................................................................... 67
Table 7-2 MAC Registers .............................................................................................................. 69
Table 8-2 Parameters Advertised in PHY Datasheet ..................................................................... 93
©2007-2016 Intel Corporation – All rights reserved
Page 6 of 114
PHY Interface for PCI Express, SATA, and USB 3.1 Architectures, ver 4.4
©2007-2016 Intel Corporation – All rights reserved
Page 7 of 114
PHY Interface for PCI Express, SATA, and USB 3.1 Architectures, ver 4.4
1 Preface
1.1 Scope of this Revision
The PCI Express, SATA and USB PHY Interface Specification has definitions of all functional
blocks and signals. This revision includes support for PCI Express implementations conforming
to the PCI Express Base Specification, Revision 4.0, SATA implementations conforming to the
SATA specification, revision 3.0, and USB implementations conforming to the Universal Serial
Bus Specification, Revision 3.1.
1.2 Revision History
Revision
Number
0.1
0.5
0.6
0.7
0.8
0.9
0.95
1.00
1.70
1.81
1.86
1.87
1.90
2.00
2.7
2.71
2.75
2.90
3.0
4.0
4.0
4.0
4.1
4.1
4.1
4.2
4.3
Date
Description
7/31/02
8/16/02
10/4/02
11/4/02
11/22/02
12/16/02
4/25/03
6/19/03
11/6/05
12/4/2005
2/27/2006
9/28/2006
3/24/2007
7/21/2007
12/31/200
7
1/21/2008
2/8/08
8/11/08
3/11/09
4/5/11
4/13/11
9/1/11
12/7/11
12/12/11
5/21/12
7/1/13
1/31/14
Initial Draft
Draft for industry review
Provides operational detail
Includes timing diagrams
More operational detail. Receiver detection sequence changed.
Minor updates. Solid enough for implementations to be finalized.
Updates to reflect 1.0a Base Spec. Added multilane suggestions.
Stable revision for implementation.
First pass at Gen. 2 PIPE
Fixed up areas based on feedback.
Fixed up more areas based on feedback. Added a section on how
to handle CLKREQ#.
Removed references to Compliance Rate determination. Added
sections for TX Margining and Selectable De-emphasis. Fixed up
areas (6.4) based on feedback.
Minor updates, mostly editorial.
Minor updates, stable revision for implementation.
Initial draft of updates to support the USB specification, revision
3.0.
Updates for SKP handling and USB SuperSpeed PHY power
management.
Additional updates for SKP handling.
Added 32 bit data interface support for USB SuperSpeed mode,
support for USB SuperSpeed mode receiver equalization training,
and support for USB SuperSpeed mode compliance patterns that
are not 8b/10b encoded.
Solid enough for implementation architectures to be finalized.
Final update
Draft 1 update adding SATA.
Draft 3 update adding PCI Express 3.0 rev .9.
Draft 6 update adding updates based on PCI Express 3.0 rev .9
feedback.
Initial draft with per lane clocking option
Draft 2. Updates for initial review feedback and addition of several
example timing diagrams for PCI Express 3.0 related signals.
Updated for Draft 2 feedback from various reviewers.
Added support for USB 3.1 – preliminary review release based on
USB 3.1 specification revision .9
Added support for PTM (preliminary for review), L1 Substates
(preliminary for review), and PCI Express 4.0 (preliminary rev .3).
©2007-2016 Intel Corporation – All rights reserved
Page 8 of 114
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