spartan3 开发板原理图.pdf

发布时间：2022-05-29 发布人：admin 分类：说明书资料大小：0.22M 资料格式：pdf 举报版权申诉

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A B C D E 4 5 6 2 3 1 3SxLC REV1 BOARD NAME : BOARD PART NUMBER : BOARD REVISION : SPARTAN 3 EVALUATION BOARD DS-BD-3SxLC-PQ208 1 MemecBoard Calgary, Alberta Canada 1 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE TITLE PAGE LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 1 of 8 2 3 4 5 6 A B C D E

1 2 1 2 1 2 TP8 3.3V 2.5V TP7 1.2V H G F E D C B A 5V 3.3V 5V 3V3ENABLE + C162 330u C3 2.2u 5V + C159 330u C1 2.2u 5V R98 10k 1% C163 2.2u C175 .01u 6 0402 1 2 JP22 1X2 3.3V DISABLE U2 TPS78633KTT 1 2 3 4 5 ENABLE IN GND OUT BYPASS/FB GND 6 Q5 Si2333 2 3 1 R129 100 SOFTSTART CIRCUIT C182 .1u 6 0603 R130 210k 1% C183 47n 6 0402 3.3V 2V5ENABLE C161 .1u 6 0603 C160 2.2u 1 2 3 4 5 U1 EN IN GND OUT BYPASS/FB TPS79525DCQ GND 6 Q6 Si2333 2 3 1 R131 100 SOFTSTART CIRCUIT C184 .1u 6 0603 R132 121k 1% C185 47n 6 0402 2.5V 3.3V R115 100 DS6 GREEN LABEL = 3.3V 2.5V R1 100 DS1 GREEN LABEL = 2.5V 5V R2 330 1% DS2 GREEN LABEL = 1.2V 10 9 8 7 6 5 4 3 2 1 VOLTAGE INPUT JACK REGULATION LED GROUND TEST LOOPS JP1 1 2 Barrel Jack SMT TP6 VINJACK VINUSB VINJACK VIN (5V) 1 JP32 1X2 2 INSTALL SHUNT TO POWER THE BOARD FROM USB SW1 1 3 SPDT Slide 6A 2 + C56 330u 5V TP5 FEET NE1 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB NE2 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB NE3 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB NE4 Little Rubber Feet -Thick MOUNT TO BOTTOM AS PER SSB MOUNTING HOLES NE6 Mounting Hole (.125) NE7 Mounting Hole (.125) NE8 Mounting Hole (.125) NE9 Mounting Hole (.125) H G F E D C B A 5V 1.2V 2.5V C191 1u 6 0603 C192 10u 6.3 1206 C193 10u 6.3 1206 C100 10u 6.3 1206 C104 .1u 0603 6 2.5V R13 10k 1% 1 JP34 1.2V DISABLE 1X2 2 11 12 13 14 15 16 17 18 19 20 U3 PGND PGND PGND VIN VIN VIN VBIAS SS/ENA SYNC RT TPS54110PWP PH PH PH PH PH BOOT PWRGD COMP VSENSE AGND 10 9 8 7 6 5 4 3 2 1 R3 73.2k 1% 1V2ENABLE C189 1u 6 0603 C105 47n 6 0402 3V3ENABLE C103 10u 6.3 1206 + 1.2V C195 330u R24 30.1k 1% C186 2.7n 6 0603 C190 470p 16 0603 R134 1.91k 1% C187 27p 6 0603 R127 10k 1% C194 22u 6 1206 1.2V R1 1 R2 3 2 SUPERVISOR 5V 2V5ENABLE 8 7 6 5 U5 VDD SENSE RESET RESET TLC7733IPW CONTROL RESIN CT GND 1 2 3 4 Q3 BCR108 R12 3.3k 1% 5V R133 3.3k 1% C188 4.7u 6 0603 1 JP33 1X2 2 2.5V DISABLE MemecBoard Calgary, Alberta Canada 10 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE POWER 9 8 7 LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 2 of 8 5 4 3 2 1 L1 6.2uH R135 28.7k 1% 6

10 BANK 0 - P160 LEFT & CLOCK H 9 3.3V 8 8 1 1 0 2 0 _ O C C V 0 _ O C C V U4A XC3S400 8 7 6 5 BANK 1 - P160 LEFT BANK 2 - P160 LEFT 3.3V 7 7 1 4 6 1 1 _ O C C V 1 _ O C C V U4B XC3S400 4 3.3V 3 5 1 6 3 1 2 _ O C C V 2 _ O C C V LIO_B39 LIO_B38 LIO_B37 LIO_B36 LIO_B35 LIO_B34 205 204 203 200 199 198 184 183 IO/VREF_0 IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO/VREF_0,nc IO_L25N_0 IO_L25P_0 IO_L32N_0/GCLK7 IO_L32P_0/GCLK6 IO IO IO_L30P_0 IO_L30N_0 IO_L27P_0 IO_L27N_0 IO_L31P_0/VREF_0 IO_L31N_0 197 189 190 191 194 196 185 187 LIO_B33 LIO_B28 LIO_B29 LIO_B30 LIO_B31 LIO_B32 LIO_A39 LIO_B27 G FPGA_GCLK CLK_SOCKET LIO_A9 LIO_A11 LIO_A17 LIO_A19 LIO_A21 161 162 165 166 167 181 180 IO_L01P_1/VRN_1 IO_L01N_1/VRP_1 IO_L10P_1 IO_L10N_1/VREF_1 IO IO_L32N_1/GCLK5 IO_L32P_1/GCLK4 IO_L27P_1 IO_L27N_1 IO_L28P_1 IO_L28N_1 IO IO_L31P_1 IO_L31N_1/VREF_1 IO 168 169 171 172 175 176 178 182 LIO_A23 LIO_A25 LIO_A27 LIO_A29 LIO_A31 LIO_A33 LIO_A35 LIO_A37 LIO_A15 LIO_A13 LIO_B26 LIO_B25 LIO_B24 LIO_B23 LIO_B22 LIO_B21 LIO_B20 LIO_B19 LIO_B18 156 155 154 152 150 149 148 147 146 IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO/VREF_2,nc IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2 IO_L22P_2 IO_L22N_2 IO_L24P_2 IO_L24N_2 IO_L23P_2 IO_L23N_2/VREF_2 IO_L39N_2,nc IO_L39P_2,nc IO_L40N_2 IO_L40P_2/VREF_2 3 2 BANK 3 - P160 RIGHT 1 U4D XC3S400 3.3V 0 1 1 7 2 1 3 _ O C C V 3 _ O C C V RIO_A19 RIO_A20 RIO_A17 RIO_A18 RIO_A15 RIO_A16 RIO_A13 RIO_A14 RIO_A11 RIO_A12 107 106 109 108 113 111 115 114 117 116 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L17N_3,nc IO_L17P_3/VREF_3,nc IO_L19N_3 IO_L19P_3 IO_L20N_3 IO_L20P_3 IO_L21N_3 IO_L21P_3 IO_L40P_3 IO_L40N_3/VREF_3 IO_L39P_3,nc IO_L39N_3,nc IO_L24P_3 IO_L24N_3 IO_L23P_3/VREF_3 IO_L23N_3 IO_L22P_3 IO_L22N_3 130 131 126 128 124 125 122 123 119 120 RIO_A2 RIO_A1 RIO_A4 RIO_A3 RIO_A6 RIO_A5 RIO_A8 RIO_A7 RIO_A10 RIO_A9 U4C XC3S400 143 144 138 139 140 141 137 135 133 132 LIO_B16 LIO_B17 LIO_B12 LIO_B13 LIO_B14 LIO_B15 LIO_B11 LIO_B10 LIO_B9 LIO_B8 16 BANK 4 - P160 RIGHT 15 P160 LEFT 1 CLOCK 15 15 P160 LEFT 19 19 P160 LEFT 20 20 P160 RIGHT BANK 5 - P160 RIGHT BANK 6 - P160 RIGHT & DISPLAY & DIP BANK 7 - RS232 & USB & DIP & PUSH & & LED & P160 LEFT 3.3V 8 9 4 8 4 _ O C C V 4 _ O C C V IO_L27P_4/D1 IO_L30N_4/D2 IO_L30P_4/D3 IO/VREF_4 IO_L31N_4/INIT_B IO_L31P_4/DOUT/BUSY IO_L32N_4/GCLK1 IO_L32P_4/GCLK0 IO IO_L27N_4/DIN/D0 IO_L25P_4 IO_L25N_4 IO/VREF_4,nc IO,nc IO_L01P_4/VRN_4 IO_L01N_4/VRP_4 IO/VREF_4 3.3V 0 6 3 7 5 _ O C C V 5 _ O C C V U4F XC3S400 3.3V 9 4 2 3 6 _ O C C V 6 _ O C C V U4G XC3S400 RIO_A29 RIO_A30 RIO_A27 RIO_A28 RIO_A26 RIO_B34 RIO_B36 58 57 62 61 63 77 76 IO_L01N_5/RDWR_B IO_L01P_5/CS_B IO_L10N_5/VRP_5 IO_L10P_5/VRN_5 IO IO_L32N_5/GCLK3 IO_L32P_5/GCLK2 IO_L27P_5 IO_L27N_5/VREF_5 IO_L28N_5/D6 IO_L28P_5/D7 IO IO_L31P_5/D5 IO_L31N_5/D4 IO/VREF_5 64 65 68 67 71 72 74 78 RIO_A25 RIO_A24 RIO_A22 RIO_A23 RIO_A21 RIO_B40 RIO_B38 RIO_B32 RIO_A31 RIO_A32 RIO_A33 RIO_A34 RIO_A35 RIO_A36 RIO_A37 RIO_A38 RIO_A39 52 51 50 48 46 45 44 43 42 IO_L01N_6/VRP_6 IO_L01P_6/VRN_6 IO/VREF_6,nc IO_L19N_6 IO_L19P_6 IO_L20N_6 IO_L20P_6 IO_L21N_6 IO_L21P_6 IO_L22N_6 IO_L22P_6 IO_L23N_6 IO_L23P_6 IO_L24N_6/VREF_6 IO_L24P_6 IO_L39N_6,nc IO_L39P_6,nc IO_L40N_6 IO_L40P_6/VREF_6 40 39 37 36 35 34 33 31 29 28 RIO_A40 DISPLAY.1C DISPLAY.1B DISPLAY.1A DISPLAY.1G DISPLAY.1F DISPLAY.1D DISPLAY.1E DIP4 DIP3 U4E XC3S400 93 92 94 95 96 97 100 101 102 D0 RIO_B16 RIO_B14 RIO_B12 RIO_B10 RIO_B8 RIO_B6 RIO_B4 RIO_B2 FPGA OUT RXD LIO_B40 USB_RI FPGA IN TXD USB_DTR USB_DCD USB_SOUT USB_DSR USB_RTS USB_SIN 3 2 5 4 9 7 11 10 13 12 3.3V 3 62 7 _ O C C V 7 _ O C C V IO_L01N_7/VRP_7 IO_L01P_7/VRN_7 IO_L16N_7,nc IO_L16P_7/VREF_7,nc IO_L19N_7/VREF_7 IO_L19P_7 IO_L20N_7 IO_L20P_7 IO_L21N_7 IO_L21P_7 IO_L22P_7 IO_L22N_7 IO_L23P_7 IO_L23N_7 IO_L24P_7 IO_L24N_7 IO_L39P_7,nc IO_L39N_7,nc IO_L40P_7 IO_L40N_7/VREF_7 INITn RIO_B18 RIO_B20 RIO_B22 RIO_B24 RIO_B26 RIO_B28 RIO_B30 90 87 86 85 83 81 80 79 15 2 CONFIG CONFIGURATION BLOCK F E D C B A U4H XC3S400 15 16 18 19 20 21 22 24 26 27 USB_CTS USB_RESETn LED3 LED4 LED1 LED2 PUSH1 PUSH2 DIP1 DIP2 2 LED 1 P160 LEFT 2 DIP 2 PUSH 2 RS232 9 USB 2 UNUSED H G F E D C B A 15 P160 RIGHT 15 15 P160 RIGHT 19 POWER BLOCK 2.5V R5 3.3k R6 3.3k R7 3.3k 2.5V R8 3.3k 1% Mode Master-serial Slave Serial Master SelectMAP Slave SelectMAP Boundary-scan Pull-ups ON Pull-ups OFF Pull-ups 0 1 2 3 DONE No No Yes No No Indicates jumper installed ('0') Indicates jumper removed ('1') 1 3 5 7 0 1 2 3 J1 2X4 2 4 6 8 NE10 SHUNT-LO-CL INSTALL ON J1[1-2] NE11 SHUNT-LO-CL INSTALL ON J1[3-4] NE12 SHUNT-LO-CL INSTALL ON J1[5-6] U4I XC3S400 PROGRAMn FPGA.CCLK M0 M1 M2 TCK TDI.FPGA TDO.FPGA.to.TDO.PORT TMS MHS 207 104 103 55 54 56 159 208 158 160 206 PROG_B CCLK DONE M0 M1 M2 TCK TDI TDO TMS HSWAP_EN 7 DISPLAY 10 P160 RIGHT 2 DIP 20 1.2V 2.5V 2 9 1 4 7 1 8 8 0 7 3 9 1 3 7 1 2 4 1 1 2 1 9 8 9 6 8 3 7 1 I I I T N C C V T N C C V T N C C V T N C C V I X U A C C V X U A C C V X U A C C V X U A C C V X U A C C V X U A C C V X U A C C V X U A C C V U4J XC3S400 D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G 2 1 1 6 8 1 3 6 1 6 6 5 2 7 5 1 7 4 9 9 9 5 1 4 2 0 2 5 0 1 5 9 1 1 5 1 5 4 1 4 1 0 13 8 1 1 9 7 1 9 2 1 0 7 81 5 7 2 8 4 3 1 3 5 1 9 MemecBoard Calgary, Alberta Canada 10 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE FPGA LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 3 of 8 9 8 7 6 5 4 3 2 1

10 9 8 7 6 PROM (PLATFORM FLASH) PROGRAM PUSHBUTTON 5 DONE LED 4 3 2 1 PROM JTAG BYPASS 2.5V 2.5V R113 3.3k 1% R114 3.3k 1% TDO.PROM TDI.PORT.to.TDI.PROM TMS TCK FPGA.CCLK 17 4 5 6 3 8 13 10 INITn DONE 3.3V 2.5V 2.5V 2.5V R128 100k 1% DEPOPULATED = Y D0 PROGRAMn 1 16 2 15 7 14 9 12 D0/DATA DNC DNC DNC CF DNC DNC DNC U10 TDO TDI TMS TCK 8 1 0 2 9 1 C C V J C C V O O C C V XCF02SVO20C CLK OE/RESET CEO CE D N G 1 1 2.5V R10 3.3k PROGRAMn 1 4 2 3 SW2 TL1105SP LABEL = PROGRAM 2.5V R9 100 DS5 GREEN LABEL = DONE Q2 BCR108 3 2 DONE R1 1 R2 NE17 SHUNT-LO-CL INSTALL ON J11 TDO.PROM J11 1 1X2 RA 2 TDI.FPGA SEE DIAGRAM BELOW FOR CONFIGURATION 2.5V 2.5V 3.3V C8 .1u C61 .1u C62 .1u CLOCKs JTAG PORT 1 2 Y2 EN GND 50MHz VCC OUT 4 3 3.3V 3.3V C179 .1u C164 .01u 6 0402 3.3V 3.3V R136 33 1% CLK_SOCKET 2.5V R105 33 1% CLK_50M PLACE CLOSE TO Y2 ACTUAL VALUE SET ON BOM 58 C C V E L B A N E T U O D N G 1 4 Y3 CAN PLACE CLOSE TO Y2 ACTUAL VALUE SET ON BOM 3.3V 3.3V C180 .1u C181 .01u 6 0402 J2 GND GND GND GND GND GND GND 1 3 5 7 9 11 13 JTAG SSer VREF VREF TMS PROG TCK CCLK TDO DONE TDI DIN NC NC NC INIT 2 4 6 8 10 12 14 Parallel IV RA TMS R11 TDO.FPGA.to.TDO.PORT TDI.PORT.to.TDI.PROM 33 1% TCK PLACE CLOSE TO J2 ACTUAL VALUE SET ON BOM JTAG CONNECTION DIAGRAM JTAG CABLE CONNECTIONS FPGA ONLY IN CHAIN PROM ONLY IN CHAIN PROM & FPGA IN CHAIN J2/SAM TCK TMS TDO TDI TCK TMS TDI TDO JP11 JUMPER OUT JP11 JUMPER OUT JP11 JUMPER IN TCK TMS TDI TDO R11 TCK TMS TDI TDO TCK TMS TCK TMS PROM TDI.PORT.to.TDI.PROM TDI TCK TMS TDI FPGA TDO.PROM TDO TDO.FPGA.to.TDO.PORT TDO 1 2 J11 TDI.FPGA MemecBoard Calgary, Alberta Canada 10 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE FPGA PERIPHERALS LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 4 of 8 9 8 7 6 5 4 3 2 1 H G F E D C B A H G F E D C B A

H G F E D C B A 10 9 8 7 6 5 4 3 2 1 FPGA CORE DECOUPLING (4 pins) FPGA BANK DECOUPLING (16 pins) FPGA AUX DECOUPLING (8 pins) 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 3.3V 3.3V 3.3V 3.3V 2.5V 2.5V 2.5V 2.5V C27 .01u 6 0402 C29 .01u 6 0402 C30 .01u 6 0402 C31 .01u 6 0402 C32 .01u 6 0402 C33 .01u 6 0402 C85 .01u 6 0402 C86 .01u 6 0402 C87 .01u 6 0402 C88 .01u 6 0402 C165 .01u 6 0402 C166 .01u 6 0402 C167 .01u 6 0402 C168 .01u 6 0402 DEPOPULATED = Y DEPOPULATED = Y DEPOPULATED = Y DEPOPULATED = Y 1.2V 1.2V 1.2V 3.3V 3.3V 3.3V 3.3V C35 .1u 6 0603 C36 .1u 6 0603 C37 .1u 6 0603 DEPOPULATED = Y DEPOPULATED = Y 1.2V 1.2V C39 1u 6 0603 C40 1u 6 0603 DEPOPULATED = Y 1.2V C41 10u 6.3 1206 1.2V 1.2V + C79 330u 6.3 + C80 330u 6.3 C94 .01u 6 0402 C95 .01u 6 0402 C96 .01u 6 0402 C97 .01u 6 0402 3.3V 3.3V 3.3V 3.3V C89 .1u 6 0603 C90 .1u 6 0603 C98 .1u 6 0603 C99 .1u 6 0603 3.3V 3.3V 3.3V C92 1u 6 0603 C101 1u 6 0603 C110 1u 6 0603 3.3V C93 10u 6.3 1206 3.3V 3.3V + C102 330u 6.3 + C111 330u 6.3 AS PER XILINX APP NOTE UPDATE 2.5V 2.5V C169 .1u 6 0603 C170 .1u 6 0603 2.5V 2.5V C171 1u 6 0603 C172 1u 6 0603 2.5V C173 10u 6.3 1206 2.5V + C174 330u 6.3 MemecBoard Calgary, Alberta Canada 10 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE DECOUPLING LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 5 of 8 9 8 7 6 5 4 3 2 1 H G F E D C B A

10 9 8 7 6 5 4 3 2 1 SEVEN SEGMENT DISPLAYs 3.3V A B C 3 D 8 E F G DP DD1 RED CA 7 6 4 2 1 10 9 5 R18 100 1% R20 100 1% R19 100 1% R14 100 1% R15 100 1% R16 100 1% R17 100 1% f e a g d b c DISPLAY.1A DISPLAY.1B DISPLAY.1C DISPLAY.1D DISPLAY.1E DISPLAY.1F DISPLAY.1G USB DIP SWITCH DIP1 DIP2 DIP3 DIP4 PULL-UPS MUST BE IMPLEMENTED IN FPGA SW3 8 7 6 5 1 2 3 4 SWDIP04 PUSHBUTTONS LEDs PULL-UPS MUST BE IMPLEMENTED IN FPGA 1 4 2 3 SW4 TL1105SP LABEL = PUSH1 1 4 2 3 SW5 TL1105SP LABEL = PUSH2 PUSH1 PUSH2 LED1 LED2 LED3 LED4 SERIAL PORT 3.3V 3.3V 3.3V 3.3V R21 100 1% DS3 GREEN R80 100 1% DS4 GREEN R137 100 1% DS7 RED R138 100 1% DS8 RED LABEL = LED1 LABEL = LED2 LABEL = LED3 LABEL = LED4 NE5 SHUNT-LO-CL INSTALL ON JP3[2-3] VUSB VUSB C176 1u 0603 6 C177 .1u 0402 6.3 VUSB C178 10u 1206 6.3 U11 67 CP2101 I N G E R D D V 5V VINUSB JP3 1 1X3 3 2 BOARD POWERED USB POWERED VUSB VUSB J3 USB-B USB_DTR USB_RTS USB_SOUT USB_SIN USB_RI USB_DCD USB_DSR USB_CTS 28 24 26 25 2 1 27 23 DTR RTS SOUT SIN RI DCD DSR CTS VBUS D+ D- SUSPEND SUSPEND RESET NC NC NC NC NC NC NC NC NC NC NC 8 4 5 12 11 9 10 13 14 15 16 17 18 19 20 21 22 D N G D N G D N G 0 3 9 2 3 4 3 2 1 GND D+ D- VCC l i i l d e h S d e h S USB_RESETn VINUSB 56 R139 330 1% DS9 GREEN LABEL = USB POWER 3.3V C13 .1u C14 .47u 6 0603 1 2 3 4 5 6 7 8 U8 EN C1+ V+ C1- C2+ C2- V- RIN MAX3221 FORCEOFF VCC GND DOUT FORCEON DIN INVALID ROUT 16 15 14 13 12 11 10 9 3.3V C12 .1u C15 .47u 6 0603 C16 .47u 6 0603 FPGA SERIAL IN FPGA SERIAL OUT TXD RXD JD1 DCD DSR RD RTS TD CTS DTR RI GND 1 6 2 7 3 8 4 9 5 DB9F RA USE STANDARD STRAIGHT-THRU CABLE WHEN CONNECTING TO A PC H G F E D C B A MemecBoard Calgary, Alberta Canada 10 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE USER IO LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 6 of 8 9 8 7 6 5 4 3 2 1 H G F E D C B A

10 9 8 7 6 5 4 P160 5V 3.3V 2.5V JX1 P160 Left Header MB A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 TCK GND TMS VIN TDI GND TDO 3.3V IOA9 GND IOA11 2.5V IOA13 GND IOA15 VIN IOA17 GND IOA19 3.3V IOA21 GND IOA23 2.5V IOA25 GND IOA27 VIN IOA29 GND IOA31 3.3V IOA33 GND IOA35 2.5V IOA37 GND IOA39 VIN CLK CLK LIO_A9 LIO_A11 LIO_A13 LIO_A15 LIO_A17 LIO_A19 LIO_A21 LIO_A23 LIO_A25 LIO_A27 LIO_A29 LIO_A31 LIO_A33 LIO_A35 LIO_A37 LIO_A39 DIN DOUT CCLK DONE INITn PROGRAMn NC IOB8 IOB9 IOB10 IOB11 IOB12 IOB13 IOB14 IOB15 IOB16 IOB17 IOB18 IOB19 IOB20 IOB21 IOB22 IOB23 IOB24 IOB25 IOB26 IOB27 IOB28 IOB29 IOB30 IOB31 IOB32 IOB33 IOB34 IOB35 IOB36 IOB37 IOB38 IOB39 IOB40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 LIO_B8 LIO_B9 LIO_B10 LIO_B11 LIO_B12 LIO_B13 LIO_B14 LIO_B15 LIO_B16 LIO_B17 LIO_B18 LIO_B19 LIO_B20 LIO_B21 LIO_B22 LIO_B23 LIO_B24 LIO_B25 LIO_B26 LIO_B27 LIO_B28 LIO_B29 LIO_B30 LIO_B31 LIO_B32 LIO_B33 LIO_B34 LIO_B35 LIO_B36 LIO_B37 LIO_B38 LIO_B39 LIO_B40 SYSTEM ACE MODULE PLACEMENT FPGA CLOCK INPUT FROM CAN FPGA CLOCK INPUT FROM SAM SAM CLOCK INPUT FROM CAN FPGA & SAM CLOCK INPUTs FROM CAN NE18 SHUNT-LO-CL INSTALL ON JP30[1-2] 3.3V 2.5V CLK_50M 2 4 1 3 JP30 2X2 2.5V 3.3V FPGA_GCLK TDO.FPGA.to.TDO.PORT TMS TDI.PORT.to.TDI.PROM PROGRAMn RIO_A19 RIO_B32 RIO_A35 RIO_A10 RIO_B10 RIO_A15 RIO_A16 RIO_A11 RIO_A14 RIO_B14 RIO_A21 RIO_A33 RIO_A37 LIO_B20 LIO_B37 DONE FPGA.CCLK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 JP29 3.3V TDO TMS TDI PROGRAMn GND OEn A00 A02 2.5V D00 D02 D04 D06 D08 D10 D12 D14 A04 A06 IRQ RESETn DONE CCLK GND SAM Header CUT PIN 50 3.3V GND CLOCK GND TCK GND INITn WEn A01 A03 2.5V D01 D03 D05 D07 D09 D11 D13 D15 A05 GND CEn BRDY BITSTREAM GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 TCK INITn RIO_A40 RIO_A34 RIO_B36 RIO_B12 RIO_A12 RIO_B16 RIO_B18 RIO_A9 RIO_A13 RIO_A17 RIO_A18 RIO_A36 LIO_B18 RIO_A39 D0 H G F E D C B A 3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 RIO_A1 RIO_A2 RIO_A3 RIO_A4 RIO_A5 RIO_A6 RIO_A7 RIO_A8 RIO_A9 RIO_A10 RIO_A11 RIO_A12 RIO_A13 RIO_A14 RIO_A15 RIO_A16 RIO_A17 RIO_A18 RIO_A19 RIO_A20 RIO_A21 RIO_A22 RIO_A23 RIO_A24 RIO_A25 RIO_A26 RIO_A27 RIO_A28 RIO_A29 RIO_A30 RIO_A31 RIO_A32 RIO_A33 RIO_A34 RIO_A35 RIO_A36 RIO_A37 RIO_A38 RIO_A39 RIO_A40 2 1 JX2 P160 Right Header MB 2.5V 3.3V 5V IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 IOA8 IOA9 IOA10 IOA11 IOA12 IOA13 IOA14 IOA15 IOA16 IOA17 IOA18 IOA19 IOA20 IOA21 IOA22 IOA23 IOA24 IOA25 IOA26 IOA27 IOA28 IOA29 IOA30 IOA31 IOA32 IOA33 IOA34 IOA35 IOA36 IOA37 IOA38 IOA39 IOA40 GND IOB2 VIN IOB4 GND IOB6 3.3V IOB8 GND IOB10 2.5V IOB12 GND IOB14 VIN IOB16 GND IOB18 3.3V IOB20 GND IOB22 2.5V IOB24 GND IOB26 VIN IOB28 GND IOB30 3.3V IOB32 GND IOB34 2.5V IOB36 GND IOB38 VIN IOB40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 RIO_B2 RIO_B4 RIO_B6 RIO_B8 RIO_B10 RIO_B12 RIO_B14 RIO_B16 RIO_B18 RIO_B20 RIO_B22 RIO_B24 RIO_B26 RIO_B28 RIO_B30 RIO_B32 RIO_B34 RIO_B36 RIO_B38 RIO_B40 P156 P157 19 20 P131 P132 P105 P104 1 X J 9 4 CLK PINS 13 2 BANK 2 19 BANK 3 20 BANK 1 15 BANK 0 16 P182 P183 15 BANK 7 20 BANK 6 19 2 X J 0 6 M A S BANK 4 15 BANK 5 15 P79 P78 15 15 10 1 1 1 USB CLK CAN P208 P1 P27 P28 P53 P52 2 7 4 6 7 2 RS232 USB EEPROM DISPLAY DIP(2) DIP(2) PUSHs(2) LED(2) USED DISPLAY EEPROM RS232 DIP PUSH LEDs JX1 JX2 CLOCK USB 7 4 2 4 2 2 49 60 2 7 AVAILABLE BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 16 15 19 20 15 15 19 20 TOTAL : 139 TOTAL : 139 MemecBoard Calgary, Alberta Canada 10 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE P160 & SAM LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 7 of 8 9 8 7 6 5 4 3 2 1 H G F E D C B A

10 9 8 7 6 5 4 3 2 1 REV A REV 1 CHANGED USB FROM TI TO CYGNAL ADDED ASSEMBLY NOTES ADDED CLOCK SOCKET REMOVED EEPROM CHANGED U5 SUPERVISOR CHANGED 1.2V CONVERTER TO SWIFT REDESIGNED POWER SEQUENCING ADDED SOFTSTART CIRCUITS TO 2.5V AND 3.3V CHANGED DONE LED DRIVE TRANSISTOR TO BCR108 ADDED TWO USER LEDs REDUCED CURRENT THROUGH 1.2V LED (100 TO 330 OHM) ADDED JUMPER BLOCK TO USB UART SIGNALS H G F E D C B A MemecBoard Calgary, Alberta Canada 10 BOARD TITLE SPARTAN 3Sx EVALUATION BOARD PAGE TITLE HISTORY LAST MODIFIED Wednesday, January 14, 2004 SIZE C DESIGNER JBE REVISION 1 SHEET 8 of 8 9 8 7 6 5 4 3 2 1 H G F E D C B A

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