module ks123(clk,rst,in,out); input clk,rst; input [31:0] in; output [1023:0] out; reg [1023:0] temout; reg [4:0] count; always@(posedge clk or negedge rst) begin if(!rst) count=5'b00000; else count=count+1'b1; end always@(posedge clk or negedge rst) begin if(!rst) temout<=1024'b0; else temout<={temout[991:0],in}; end assign out=(count==5'b11111)?temout:1024'b0; endmodule module ks123cs; reg [1023:0] data; wire[31:0] data_in; reg clk,rst; wire[1023:0] out; initial begin clk=1'b0; rst=1'b0; #3 rst=1'b1; data=1024'b100000000000000000000000000000001100000000000000000000000000000011100000000 00000000000000000000011110000000000000000000000000000111110000000000000000000000000001 11111000000000000000000000000001111111000000000000000000000000011111111000000000000000 0000000001111111110000000000000000000000011111111110000000000000000000000; #1000 $stop; end always #5 clk=~clk; always @(posedge clk) data={data[991:0],data[1023:992]}; assign data_in=data[1023:992]; ks123 a(.in(data_in),.clk(clk),.rst(rst),.out(out)); initial $monitor ($time,"rst=%b,data=%b,data_in=%b,out=%b",rst,data,data_in,out); endmodule