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broadcom phy BCM5482S datasheet(开发用).pdf
BCM5482S Data Sheet
Revision History
Table of Contents
List of Figures
List of Tables
Section 1: Functional Description
Overview
Modes of Operation
Copper Mode
Fiber Mode
SGMII Mode
Media Converter Mode
Reduced Gigabit Media Independent Interface
Serial GMII Interface
SerDes Interface (Complies with IEEE 802.3™, Clauses 36 and 37)
Management Interface
Encoder
Decoder
Carrier Sense
Link Monitor
Digital Adaptive Equalizer
Echo Canceler
Crosstalk Canceler
Analog-to-Digital Converter
Clock Recovery/Generator
Baseline Wander Correction
Multimode TX Digital-to-Analog Converter
Stream Cipher
Wire Map and Pair Skew Correction
Automatic MDI Crossover
10/100BASE-T Forced Mode Auto-MDIX
Auto-negotiation
Copper Mode
Fiber Mode
SGMII Mode
Media Converter Mode
Synchronous Ethernet
BCM5482SSGMII-to-Fiber Mode
BCM5482SSGMII-to-Copper Mode
Energy Detect
Internal Voltage Regulators
Power-Down Modes
Jumbo Packets
Copper Modes
Fiber Mode
SGMII/Media Converter Mode
SGMII-to-Secondary SerDes 100 FX Application
Section 2: Hardware Signal Descriptions
Section 3: Pinout Diagram
Section 4: Operational Description
Reset
PHY Address
Isolate Mode
Copper Mode
Fiber Mode
Standby Power-Down Mode
Auto Power-Down Mode
CLK125 Clock Output
Ultra-Low Power-Down Mode
Reset Requirements
Energy Detect Function
Internal Loopback Mode
RGMII to Copper Configuration
SGMII to Copper Configuration
RGMII to 1000BASE-X Configuration
SGMII to 1000BASE-X or SGMII-to-100BASE-FX Configuration
Lineside (Remote) Loopback Mode
RGMII-to-Copper or SGMII-to-Copper Configuration
SGMII-to-1000BASE-X Configuration
RGMII-to-100BASE-FX or RGMII-to-1000Base-X Configuration
SGMII-to-100BASE-FX Configuration
SGMII/Media Converter Mode
External Loopback Mode
Full-Duplex Operation
Copper Mode
Fiber Mode
Ethernet@Wirespeed™
Software Enable
Changing the Number of Failed Link Attempts Before Ethernet@Wirespeed Downgrade
Monitoring Ethernet@Wirespeed
Master/Slave Configuration
Next Page Exchange
100BASE-FX
RGMII Interface
RGMII-to-SGMII Slave Mode
SGMII Interface
Control Information Exchange Between Links
SGMII-to-SGMII Slave Mode
SerDes Interface
Media Converter Mode
Copper/Fiber Mode Auto-Detection
SGMII/Media Converter Mode Auto-Detection
Voltage Regulators
Dual-Input Configuration/LED Output Function
General-Purpose LED Programmability
Interrupt Function
LED Modes
Multicolor LED
Open/Short LED
Energy Link LED
Media Converter Mode LED
Additional LED Modes
Section 5: Register Summary
MII Management Interface Register Programming
Register Map
Register Notations
1000BASE-T/100BASE-TX/10BASE-T Registers Descriptions
1000BASE-T/100BASE-TX/10BASE-T MII Control
Reset
Internal Loopback
Speed Selection (LSB)
Auto-negotiation Enable
Power-Down
Isolate
Restart Auto-negotiation
Duplex Mode
Speed Selection (MSB)
Collision Test
1000BASE-T/100BASE-TX/10BASE-T MII Status
100BASE-T4 Capable
100BASE-X Full-Duplex Capable
100BASE-X Half-Duplex Capable
10BASE-T Full-Duplex Capable
10BASE-T Half-Duplex Capable
100BASE-T2 Full-Duplex Capable
100BASE-T2 Half-Duplex Capable
Extended Status
Management Frames Preamble Suppression
Auto-negotiation Complete
Remote Fault
Auto-negotiation Ability
Link Status
Jabber Detect
Extended Capability
1000BASE-T/100BASE-TX/10BASE-T PHY Identifier
1000BASE-T/100BASE-TX/10BASE-T Auto-negotiation Advertisement
Next Page
Remote Fault
Reserved Technology
Asymmetric Pause
Pause Capable
100BASE-T4 Capable
100BASE-TX Full-Duplex Capable
100BASE-TX Half-Duplex Capable
10BASE-T Full-Duplex Capable
10BASE-T Half-Duplex Capable
Selector Field
1000BASE-T/100BASE-TX/10BASE-T Auto-negotiation Link Partner Ability
Next Page
Acknowledge
Remote Fault
Reserved Technology
Asymmetric Pause
Pause Capable
100BASE-T4 Capable
100BASE-TX Full-Duplex Capable
100BASE-TX Half-Duplex Capable
10BASE-T Full-Duplex Capable
10BASE-T Half-Duplex Capable
Protocol Selector Field
1000BASE-T/100BASE-TX/10BASE-T Auto-negotiation Expansion
Parallel Detection Fault
Link Partner Next Page Ability
Next Page Capable
Page Received
Link Partner Auto-negotiation Ability
1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit
Next Page
Message Page
Acknowledge2
Toggle
Message/Unformatted Code Field
1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page
Next Page
Acknowledge
Message Page
Acknowledge2
Toggle
Message Code Field
1000BASE-T Control
Test Mode
Master/Slave Configuration Enable
Master/Slave Configuration Value
Repeater/DTE
Advertise 1000BASE-T Full-Duplex Capability
Advertise 1000BASE-T Half-Duplex Capability
1000BASE-T Status
Master/Slave Configuration Fault
Master/Slave Configuration Resolution
Local Receiver Status
Remote Receiver Status
1000BASE-T Full-Duplex Capability
1000BASE-T Half-Duplex Capability
Idle Error Count
1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status
1000BASE-X Full-Duplex Capable
1000BASE-X Half-Duplex Capable
1000BASE-T Full-Duplex Capable
1000BASE-T Half-Duplex Capable
1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control
Disable Automatic MDI Crossover
Transmit Disable
Interrupt Disable
Force Interrupt
Bypass 4B/5B Encoder/Decoder (100BASE-T)
Bypass Scrambler/Descrambler (100BASE-T)
Bypass MLT3 Encoder/Decoder (100BASE-T)
Bypass Receive Symbol Alignment (100BASE-T)
Reset Scrambler (100BASE-T)
Enable LED Traffic Mode
Force LEDs On
Force LEDs Off
1000-Mbps PCS Transmit FIFO Elasticity (Jumbo Packets)
1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status
Auto-negotiation Base Page Selector Field Mismatch
Ethernet@WireSpeed Downgrade
MDI Crossover State
Interrupt Status
Remote Receiver Status
Local Receiver Status
Locked
Link Status
CRC Error Detected
Carrier Extension Error Detected
Bad SSD Detected (False Carrier)
Bad ESD Detected (Premature End)
Receive Error Detected
Transmit Error Detected
Lock Error Detected
MLT3 Code Error Detected
1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter
Receive Error Counter
1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter
False Carrier Sense Counter
1000BASE-T/100BASE-TX/10BASE-T Receiver NOT_OK Counter
Local Receiver NOT_OK Counter
Remote Receiver NOT_OK Counter
1000BASE-T/100BASE-TX/10BASE-T Expansion Register Access
Expansion Register Select
Expansion Register Accessed
1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Shadow Value Access Register
External Loopback
Extended Packet Length
Edge-Rate Control (1000BASE-T)
Transmit Mode
Disable Partial Response Filter
Edge-Rate Control (100BASE-TX)
Shadow Register Select
10BASE-T
Manchester Code Error
EOF Error
Polarity Error
Block RX_DV Extension (IPG)
10BASE-T TXC Invert Mode
Jabber Disable
1000BASE-T Signal Detect Threshold
10BASE-T Signal Detect Threshold
10BASE-T Echo Mode
SQE Enable Mode
10BASE-T No Dribble
Shadow Register Select
1000BASE-T/100BASE-TX/10BASE-T Power/MII Control
Low-Power Driver
Super Isolate (Copper Only)
Shadow Register Select
1000BASE-T/100BASE-TX/10BASE-T Misc Test Register
Lineside [Remote] Loopback Enable
Lineside [Remote] Loopback Tristate
Swap RX MDIX
10BASE-T Halfout
Shadow Register Select
1000BASE-T/100BASE-TX/10BASE-T Misc Control
Write Enable (Bits 11:3)
Shadow Register Read Selector
Packet Counter Mode
Force Auto-MDIX Mode
RGMII Timing Mode
RGMII RX_DV Mode
RGMII Out-of-Band Status (OOBS) Disable
Ethernet@WireSpeed Enable
MDIO All PHY Select
Shadow Register Select
1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Summary
Auto-negotiation Complete
Auto-negotiation Complete Acknowledge
Auto-negotiation Acknowledge Detect
Auto-negotiation Ability Detect
Auto-negotiation Next Page Wait
Auto-negotiation HCD (Current Operating Speed and Duplex Mode)
Parallel Detection Fault
Remote Fault
Auto-negotiation Page Received
Link Partner Auto-negotiation Ability
Link Partner Next Page Ability
Link Status
Pause Resolution—Receive Direction and Transmit Direction
1000BASE-T/100BASE-TX/10BASE-T Interrupt Status
Signal Detect/Energy Detect Change
Illegal Pair Swap
MDIX Status Change
Exceeded High Counter Threshold
Exceeded Low Counter Threshold
Auto-negotiation Page Received
No HCD Link
No HCD
Negotiated Unsupported HCD
Scrambler Synchronization Error
Remote Receiver Status Change
Local Receiver Status Change
Duplex Mode Change
Link Speed Change
Link Status Change
CRC Error
1000BASE-T/100BASE-TX/10BASE-T Interrupt Mask
Interrupt Mask Vector
1000BASE-T/100BASE-TX/10BASE-T Register 1Ch Access
1000BASE-T/100BASE-TX/10BASE-T Spare Control 1
Write Enable
Shadow Register Selector
Link LED Mode
1000BASE-T/100BASE-TX/10BASE-T Clock Alignment Control
Write Enable
Shadow Register Selector
GTXCLK Clock Delay Enable
1000BASE-T/100BASE-TX/10BASE-T Spare Control 2
Write Enable
Shadow Register Selector
Ethernet@WireSpeed Retry Limit
Energy Detect on INTR Pin
1000BASE-T/100BASE-TX/10BASE-T Spare Control 3
Write Enable
Shadow Register Selector
TXC/RXC Disable During Auto Power-Down
TXC Disable
Signal Detect/Energy Detect Enable
CLK125 Auto Power-Down
CLK125 Output
1000BASE-T/100BASE-TX/10BASE-T LED Status
Write Enable
Shadow Register Selector
Slave Indicator
FDX Indicator
INTR Indicator
LINKSPD Indicator
Transmit Indicator
Receive Indicator
Quality Indicator
1000BASE-T/100BASE-TX/10BASE-T LED Control
Write Enable
Shadow Register Selector
Override Media Converter LED Mode
Activity/Link LED Enable
ACTIVITY LED Enable
Remote Fault LED Enable
Link Utilization LED Selector
1000BASE-T/100BASE-TX/10BASE-T Auto Power-Down
Write Enable
Shadow Register Selector
TXC/RXC Disable During Auto Power-Down
Auto Power-Down Mode
Sleep Timer Select
Wake-up Timer Select
1000BASE-T/100BASE-TX/10BASE-T LED Selector 1
External Control 2
Write Enable
Shadow Register Selector
LED3 (LINKSPD[2]) Selector
LED1 (LINKSPD[1]) Selector
1000BASE-T/100BASE-TX/10BASE-T LED Selector 2
Write Enable
Shadow Register Selector
LED2 (INTR) Selector
LED4 (Activity) Selector
1000BASE-T/100BASE-TX/10BASE-T LED GPIO Control/Status
Write Enable
Shadow Register Selector
LED I/O Status
Programmable LED I/O Control
SerDes 100BASE-FX Status
Write Enable
Shadow Register Selector
Bad ESD Detected (Premature End)
False Carrier Detected
Transmit Error Detected
Receive Error Detected
Lock Timer Expired
Lost Lock
Faulting
Locked
100FX Link (SerDes)
SerDes 100BASE-FX Extend Register
Write Enable
Shadow Register Selector
Far End Fault Enable
100BASE-FX SerDes Full-Duplex
100BASE-FX SerDes Enable
Secondary SerDes Control
Write Enable
Shadow Register Selector
Secondary SerDes Link Status Change
Secondary SerDes Link
Secondary SerDes Duplex
Secondary SerDes 100BASE-FX Full-Duplex
Secondary SerDes 100BASE-FX Mode
Secondary SerDes LED Mode
Select Sync Status
Select SD
Secondary SerDes Select
SGMII Slave
Write Enable
Shadow Register Selector
SerDes Link
SerDes Duplex
SerDes Speed
SerDes Link Status Change
Mode Select
RGMII-to-SGMII Slave 10/100 TX FIFO Frequency Lock Mode
SGMII Slave Mode
SGMII Slave Auto-Detection
Primary SerDes Control
Write Enable
Shadow Register Selector
Signal Detect Enable
SerDes Auto-Negotiation Parallel Detect Enable
Misc 1000BASE-X Control 2
SerDes Transmit Disable
Signal Detect Enable
Disable Media Converter Updates From GPHY SerDes
Force XMIT = Data
1000BASE-X Auto-Detect SGMII/Media Converter
Write Enable
Shadow Register Selector
SerDes Resolution Fault
1000BASE-T PCS Transmit FIFO Elasticity (SGMII/Media Converter Mode)
SGMII 10/100BASE-T RX FIFO Frequency Lock Mode
SGMII/Media Converter Auto-Detect Mode Enable
1000BASE-X Auto-negotiation Debug
Write Enable
Shadow Register Selector
Consistency Mismatch
RUDI Invalid
Sync Status Detected
AN_Sync_Status
Idle Detect State
Complete Acknowledge State
Acknowledge Detect State
Ability Detect State
Sync Status Failed
AN_Enable State
Auxiliary 1000BASE-X Control
Write Enable
Shadow Register Selector
Use SerDes Mode Counters
Disable Remote Fault Sensing
Auto-negotiation Error Timer Enable
Comma Detect Enable
1000BASE-X PCS Transmit, SGMII 10/100BASE-T Transmit and Receive FIFO Elasticity
Disable CRC Checker
Auxiliary 1000BASE-X Status
Write Enable
Shadow Register Selector
Link Status Change
SGMII Selector Mismatch
Auto-negotiation Resolution Error
Link Partner Remote Fault
Auto-negotiation Page Received
Current Operating Duplex Mode
Link Status
PAUSE Resolution—Receive Side
PAUSE Resolution—Transmit Side
Misc 1000BASE-X Status
Write Enable
Shadow Register Selector
False Carrier Detected
CRC Error Detected
Transmit Error Detected
Receive Error Detected
Carrier Extend Error Detected
Early End Extension Detected
Copper/Fiber Auto-Detect Medium
Write Enable
Shadow Register Selector
Secondary SerDes Auto-Detection
Invert Fiber Signal Detect from SD Pin
Fiber In-Use LED Mode
Fiber LED Mode
Qualify Fiber Signal Detect with Sync Status
Auto-Detect Media Default
Auto-detect Media Priority
Auto-detect Media Enable
Mode Control
Write Enable
Shadow Register Selector
Mode Select Change
Copper Link
SerDes Link
Copper Energy Detect
Fiber Signal Detect
Mode Select
Enable 1000BASE-X Registers
1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed
Enable Shadow Register
Master/Slave Seed Match
Link Partner Repeater/DTE Bit
Link Partner Manual Master/Slave Configuration Value
Link Partner Manual Master/Slave Configuration Enable
Local Master/Slave Seed Value
1000BASE-T/100BASE-TX/10BASE-T HCD Status
Enable Shadow Register
Ethernet@WireSpeed Disable Gigabit Advertising
Ethernet@WireSpeed Disable 100BASE-TX Advertising
Ethernet@WireSpeed Downgrade
HCD 1000BASE-T FDX
HCD 1000BASE-T
HCD 100BASE-TX FDX
HCD 100BASE-T
HCD 10BASE-T FDX
HCD 10BASE-T
HCD 1000BASE-T FDX (Link Never Came Up)
HCD 1000BASE-T (Link Never Came Up)
HCD 100BASE-TX FDX (Link Never Came Up)
HCD 100BASE-TX (Link Never Came Up)
HCD 10BASE-T FDX (Link Never Came Up)
HCD 10BASE-T FDX (Link Never Came Up)
1000BASE-T/100BASE-TX/10BASE-T Test Register 1
CRC Error Counter Selector
Manual Swap MDI State
Primary SerDes Register Descriptions
1000BASE-X MII Control
Reset
Internal Loopback
Auto-negotiation Enable
Power-Down
Isolate
Restart Auto-negotiation
Duplex Mode
Collision Test
1000BASE-X MII Status
100BASE-T4 Capable
100BASE-X Full-Duplex Capable
100BASE-X Half-Duplex Capable
10BASE-T Full-Duplex Capable
10BASE-T Half-Duplex Capable
100BASE-T2 Full-Duplex Capable
100BASE-T2 Half-Duplex Capable
Extended Status
Management Frames Preamble Suppression
Auto-negotiation Complete
Remote Fault
Auto-negotiation Ability
Link Status
Jabber Detect
Extended Capability
1000BASE-X Auto-negotiation Advertisement
Remote Fault
Pause
Half-Duplex Capable
Full-Duplex Capable
1000BASE-X Auto-Negotiation Link Partner Ability
1000BASE-X Mode
Next Page
Acknowledge
Remote Fault
Pause
Half-Duplex Capable
Full-Duplex Capable
SGMII Mode
Copper Link
Acknowledge
Copper Duplex
Copper Speed
1000BASE-X Auto-negotiation Extended Status
Next Page Capable
Page Received
1000BASE-X IEEE Extended Status
1000BASE-X Full-Duplex Capable
1000BASE-X Half-Duplex Capable
1000BASE-T Full-Duplex Capable
1000BASE-T Half-Duplex Capable
Expansion Registers
Expansion Register 00h: Receive/Transmit Packet Counter
Packet Counter (Copper Only)
Expansion Register 01h: Expansion Interrupt Status
Mode Select Change
SerDes Link Status Change
RUDI_C Detected
Expansion Interrupt Status
Transmit CRC Error (Copper Only)
Expansion Register 02h: Expansion Interrupt Mask
Expansion Register 04h: Multicolor LED Selector
Flash Now
In Phase
MULTICOLOR[2] LED Selector
MULTICOLOR[1] LED Selector
Expansion Register 05h: Multicolor LED Flash Rate Controls
Alternating Rate
Flash Rate
Expansion Register 06h: Multicolor LED Programmable Blink Controls
Blink Update Now
Blink Rate
Expansion Register 42h: Operating Mode Status
SerDes Link
SerDes Speed
SerDes Duplex
Copper Link
Copper Speed
Copper Duplex
Copper Energy Detect
Fiber Signal Detect
Sync Status
Operating Mode Status
Expansion Register 44h: SGMII Recover Control
Select Recovered CLK
Expansion Register 50h: SerDes/SGMII RX Control
RX Power Down
Expansion Register 52h: SerDes/SGMII Control
TX Clock Pad Disable R/W
Secondary SerDes Registers
1000BASE-X Control
Secondary SerDes Reset
Loopback
Manual Speed [0]
Auto-negotiation Enable
Power-Down
Restart Auto-negotiation
Manual Full-Duplex Mode
Manual Speed [1]
1000BASE-X Auto-Negotiation Advertisement
Next Page
Remote Fault
Pause
Half Duplex
Full Duplex
1000BASE-X Auto-Negotiation Link Partner Ability
Next Page
Acknowledge
Remote Fault
Pause
Half-Duplex Capable
Full-Duplex Capable
Copper Link
Acknowledge
Copper Duplex
Copper Speed
SGMII Selector
1000BASE-X Auto-Negotiation Secondary SerDes Register
Next Page Receive Location Able
Next Page Receive Location
Page Received
1000BASE-X Auto-Negotiation Next Page Transmit
Next Page
Message Page
Acknowledge2
Toggle
Code Field
1000BASE-X Auto-Negotiation Link Partner Next Page
Next Page
1000BASE-X Extended Status
1000BASE-X Full-Duplex Capable
1000BASE-X Half-Duplex Capable
1000BASE-T Full-Duplex Capable
1000BASE-T Half-Duplex Capable
Misc 1
Enable Interrupts
Invert Signal Detect
Extended Packet Length (100-FX Mode)
100BASE-FX Status
100FX Link Status Change (SerDes)
Bad ESD Detected (Premature End)
False Carrier Detected
Transmit Error Detected
Receive Error Detected
Lock Timer Expired
Lost Lock
Faulting
Locked
100FX Link (SerDes)
100BASE-FX Test
Far End Fault Enable
Unidirectional
Packet Counter
Packet Counter
Error Counter
Error Counter
SGMII Slave
SerDes Link
SerDes Duplex
SerDes Speed
SerDes Link Status Change
SGMII Slave Mode
SGMII Slave Auto-Detection
Secondary SerDes Control
SerDes Detect Enable
SerDes Auto-Negotiation Parallel Detect Enable
Misc 1000BASE-X Control 2
SerDes Transmit Disable
Signal Detect Enable
Disable GBIC Updates from GPHY SerDes
Force XMIT = Data
Misc 1000-X Control 3
XMIT = Data
Fiber SD
SD Amplitude Status
SD Amplitude Status Changed
Enable CRC Fragment Errors
Auto-Negotiation 1000BASE-X Debug
Consistency Mismatch
RUDI Invalid
Sync Status Detected
AN_Sync_Status
Idle Detect State
Complete Acknowledge State
Acknowledge Detect State
Ability Detect State
Error State
Sync Status Failed
AN_Enable State
Secondary SerDes Auxiliary 1000BASE-X Control Register
Disable Remote Fault Sensing
Auto-negotiation Error Timer Enable
Comma Detect Enable
1000BASE-X PCS Transmit, SGMII 10/100BASE-T Transmit, and Receive FIFO Elasticity
Disable CRC Checker
Auxiliary 1000BASE-X Status
Secondary SerDes Link Status Change
SGMII Selector Mismatch
Auto-negotiation Resolution Error
Link Partner Remote Fault
Auto-negotiation Page Received
Current Operating Duplex Mode
SerDes Link
PAUSE Resolution—Receive Side
PAUSE Resolution—Transmit Side
Misc 1000BASE-X Status
Transmit FIFO Error
Receive FIFO Error
Bad FIFO Pointer
False Carrier Detected
CRC Error Detected
Transmit Error Detected
Receive Error Detected
Carrier Extend Error Detected
Early End Extension Detected
Spare Register
Invert Interrupt
Secondary SerDes Interrupt Status
SerDes CRC Error
SGMII Slave Mode Change
100BASE-FX SerDes Mode Change
SerDes Auto-negotiation Page Received
Secondary SerDes Select Change
Signal Detect Amplitude Change
SerDes Link Status Change
Lost Sync Status
Rudi-C Detected
SerDes Auto-negotiation Error
Idle Codeword Detected
Secondary SerDes Interrupt MASK
Secondary SerDes Interrupt Mask
Secondary SerDes Lineside Loopback Control
Secondary SerDes Lineside Loopback
Section 6: Timing and AC Characteristics
Section 7: Electrical Characteristics
Section 8: Mechanical and Thermal Data
RoHS-Compliant Packaging
Mechanical Drawings
Thermal Information
Junction Temperature Estimation and YJT vs. qJC
Section 9: Ordering Information
正规文本，开发使用
Data Sheet
BCM5482S
10/100/1000BASE-T Gigabit Ethernet Transceiver
GENERAL DESCRIPTION
FEATURES
The BCM5482S is a dual triple-speed 1000BASE-T/
100BASE-TX/10BASE-T Gigabit Ethernet transceiver
integrated in a single monolithic CMOS chip. The device
performs all physical-layer functions for 1000BASE-T,
100BASE-TX, and 10BASE-T Ethernet on standard
category 5 UTP cable. 10BASE-T can also run on
standard category 3, 4, and 5 UTP. The BCM5482S also
has a serial interface for connection to serial MAC
interfaces and fiber modules.
The BCM5482S is a highly integrated solution combining
digital adaptive equalizers, ADCs, phase-locked loops,
line drivers, encoders, decoders, echo cancellers,
crosstalk cancellers, and all required support circuitry.
Based on Broadcom’s proven digital signal processor
technology, the BCM5482S is designed to be fully
compliant with RGMII, allowing compatibility with
industry-standard Ethernet MACs and switch controllers.
The BCM5482S includes two SerDes cores. The primary
SerDes can be configured for SGMII protocol to connect
to an SGMII MAC, and the Secondary SerDes can be
configured to interface with an SFP/fiber transceiver. The
BCM5482S supports 100BASE-FX optical modules
through the SerDes interface pins. Media Converter
mode provides SerDes-to-copper translation capability.
Designed for reliable operation over worst-case Category
5 cable, the BCM5482S automatically negotiates with its
link partner to determine the highest possible operating
speed. The device detects and corrects most common
wiring problems. The digital nature of the BCM5482S
allows data to be brought out for displaying cable
diagnostics, such as attenuation and return loss, using
available software.
• Single-chip integrated triple-speed Ethernet
transceiver—MAC to magnetics:
-
1000BASE-T IEEE 802.3ab
100BASE-TX IEEE 802.3u
-
-
10BASE-T IEEE 802.3
IEEE 802.3z
RGMII, SGMII, and SerDes MAC interface options
Line-side copper and fiber (1000SX/LX and
100BASE-FX) interfaces
SGMII-to-SGMII and RGMII-to-SGMII support for
10/100/1000BASE-T SFP modules
SerDes-to-copper translation for media-converter
applications
Automatic auto-sense mode automatically configures
for dual medium applications
Integrated voltage regulators
Low EMI emissions
Super Isolate mode
Ethernet@WireSpeed™
Cable plant diagnostic
Robust CESD tolerance
Support for jumbo packets up to 10 KB
Detection and correction of pair swaps (MDI
crossover), pair skew, and pair polarity
Trace matched output impedance
MAC-side and line-side loopback
Auto-negotiation with next page support
125-MHz clock generator and timing recovery
JTAG support
Low-power, 1.2V CMOS core
2.5V or 3.3V CMOS I/O
Industrial temperature available
Devices packages: 121-pin BGA
APPLICATIONS
Gigabit Ethernet uplinks
SGMII-to-SGMII slave converter
5300 California Avenue • Irvine, CA 92617 Phone: 949-926-5000 Fax: 949-926-5203
2/16/2009 1539I
5482S-DS09-R
02/13/09
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BCM5482S
Data Sheet
02/13/09
TX DAC
+]
TRD 2 [3:0
+
TRD1[3:0]
Bseline
Wander
Correction
PGA
ADC
Auto-
Negotiation
Clock
Generator
Bias Generator
Voltage
Regulator
XTALI
XTALO
RDAC
REG_ SUP
REG_OUT
{2:1}
{2:1
}
XTALK
Canceller
x3
DFE &
Trellis
Decoder
Echo
Canceller
FFE
Timing & Phase
Recovery
Symbol Encoder
SGMII / SerDes
Symbol Decoder
Aligner
/
LED Drivers
MII Registers
MII Management
Control
Figure 1: Functional Block Diagram
{2:1}[3:0]
{2:1}
TXD
TX _EN
{2:1}
GTX_CLK
+
SGIN _P1
+
SGOUT_P1
+
SGCLK_P1
+
SGIN_P 2
+
SGOUT_P2
+
SGCLK_P2
+
S_SGIN _P1
S_SGOUT _P1
+
S_SGIN
S_SGOUT
_P2
RXC {2:1}
RX _DV {2:1}
RXD 1 [3:0]
RXD 2 [3:0]
LED_ P1[1]/ANEN (LED1)
LED
INTR
LED_ 1 3] (LED3)
LED_P1[4] (LED4)
LED_ P2[1]/SPD0 (LED1)
LED_P2[ 2]/ INTR /F1000/SD (LED2)
LED_ 2[3] (LED3)
LED_ 2[4] (LED4)
MDC _P1
MDIO_P1
MDC _P2
MDIO_P2
DRVSEL [1:0]
INTFSEL[1:0]
/FDX/SD (LED2)
_
P1[2]/
P
_P2
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Document 5482S-DS09-R
Broadcom Corporation
2/16/2009 1539I
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Data Sheet
02/13/09
REVISION HISTORY
Revision
5482S-DS09-R
Date
02/13/09
5482S-DS08-R
10/18/07
BCM5482S
Change Description
Updated:
Table 3, ”Hardware Signal Descriptions,” on page 17: Changed pin description for
pin A6 description, and pin label for J1, J2, K1, K2
Figure 9, ”121-Pin FBGA Pinout Diagram, Top View,” on page 25: Changed pin
names for E4, K1, and K2.
“RGMII-to-Copper or SGMII-to-Copper Configuration” on page 30: Updated signal
names and register name.
“RGMII Interface” on page 37: Text changes.
“Interrupt Function” on page 43: Text changes.
“Media Converter Mode LED” on page 44: Changed LED definitions.
Table 41, ”1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Register
(Address 18h, Shadow Value 000),” on page 75: Bit 14 description.
“Extended Packet Length” on page 76. Changed maximum packet length.
Table 50, ”1000BASE-T/100BASE-TX/10BASE-T Spare Control 1 Register
(Address 1Ch, Shadow Value 00010),” on page 91: Changed bits 2 definition.
Table 58, ”1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Register
(Address 1Ch, Shadow Value 01101),” on page 100 and Table 58, ”1000BASE-T/
100BASE-TX/10BASE-T LED Selector 1 Register (Address 1Ch, Shadow Value
01101),” on page 100: Changed definition of bits [7:4] and [3:0].
Table 90, ”Expansion Reg 42h: Operating Mode Status Register,” on page 142:
Updated bit 15 description.
Table 101, ”Misc 1 Register (Address 10h),” on page 154: Modified defintion of bits
4 and [2:1].
“Secondary SerDes Registers” on page 145: Changed reference to “Secondary
SerDes”.
“Ordering Information” on page 184: Deleted obsolete part numbers.
Updated:
Table 119, ”Clock Input Timing,” on page 171
RGMII parameter in Table 128, ”DC Characteristics,” on page 176
“Ordering Information” on page 184
Document 5482S-DS09-R
Page iii
Broadcom Corporation
2/16/2009 1539I
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BCM5482S
Revision
5482S-DS07-R
Date
09/07/07
Data Sheet
02/13/09
Change Description
Added:
Figure 8, ”Management Interface,” on page 6
Note to “Fiber Mode” on page 12
“Synchronous Ethernet” on page 13
“BCM5482SE SGMII-to-Fiber Mode” on page 13
“BCM5482SE SGMII-to-Copper Mode” on page 13
Table 91, ”SGMII Recover Control Register (Address 44h),” on page 144
“Shadow Register Selector” on page 111
“Expansion Register 44h: SGMII Recover Control” on page 144
Updated:
D1, D11, C7, and E4 description rows in Table 3, ”Hardware Signal Descriptions,”
on page 18
Figure 9, ”121-Pin FBGA Pinout Diagram, Top View,” on page 25
Descriptive text in “RGMII Interface” on page 37
Expansion value register information (44h) Table 19, ”Register Map,” on page 48
Default values for Bits 7 and 8 in Table 45, ”1000BASE-T/100BASE-TX/10BASE-T
Misc Control Register (Address 18h, Shadow Value 111),” on page 81
Descriptive text in “RGMII Timing Mode” on page 82
Descriptive text in “Shadow Register Selector” on page 97
Bit values in Table 66, ”Primary SerDes Control Register (Address 1C, Shadow
Value = 10110),” on page 111
XTALI input clock jitter tolerance Max value in Table 119, ”Clock Input Timing,” on
page 172
“Ordering Information” on page 185
Page iv
Document 5482S-DS09-R
Broadcom Corporation
2/16/2009 1539I
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Data Sheet
02/13/09
Revision
5482S-DS06-R
Date
2/15/07
Change Description
Added:
BCM5482S
“SGMII-to-Secondary SerDes 100 FX Application” on page 13
“ppd = peak to peak differential” on page 14
“External Control 2” on page 96
Table 57 on page 96
“Extended Packet Length (100-FX mode)” on page 150
“Far End Fault Enable” on page 152
Updated:
Table 3 on page 15
“Ultra-Low Power-Down Mode” on page 26
“SGMII to 1000BASE-X or SGMII-to-100BASE-FX Configuration” on page 27
“RGMII-to-100BASE-FX or RGMII-to-1000Base-X Configuration” on page 28
Table 13 on page 35
“Interrupt Function” on page 40
Table 19 on page 45
“Test Mode” on page 61
Table 57 on page 96
Table 58 on page 97
“LED3 (LINKSPD[2]) Selector” on page 98
Table 59 on page 99
“LED4 (Activity) Selector” on page 100
“SerDes 100BASE-FX Status” on page 101
Table 61 on page 101
“SerDes 100BASE-FX Extend Register” on page 102
Table 62 on page 103
“SerDes 100BASE-FX Extend Register” on page 102
Table 66 on page 108
“SerDes Auto-Negotiation Parallel Detect Enable” on page 108
Table 67 on page 109
“Disable Media Converter Updates From GPHY SerDes” on page 109
“Misc 1 Register (Address 10h)” on page 150
Table 102 on page 152
“SerDes Auto-Negotiation Parallel Detect Enable” on page 155
Table 118 on page 167
Table 127 on page 171
Document 5482S-DS09-R
Page v
Broadcom Corporation
2/16/2009 1539I
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BCM5482S
Revision
5482S-DS05-R
Date
08/10/06
Data Sheet
02/13/09
Change Description
Updated:
Table 2, ”Hardware Mode Selection INTFSEL[1:0],” on page 3
Figure 1, ”Functional Block Diagram,” on page ii
Pins E11, F10, F11, G11, H7, H8, H9, H10, J1, J2, K1, K2 in Table 3, ”Hardware
Signal Descriptions,” on page 16
Figure 8, ”121-Pin FBGA Pinout Diagram, Top View,” on page 23
“Lineside (Remote) Loopback Mode” on page 29
“General-Purpose LED Programmability” on page 42
“Interrupt Function” on page 43
Table 15, ”Dual Input Configuration/LED Output LEDs,” on page 41
Table 16, ”Programmable LEDs,” on page 42
Default values in Table 45, ”1000BASE-T/100BASE-TX/10BASE-T Misc Control
Register (Address 18h, Shadow Value 111),” on page 82 and Table 51,
”1000BASE-T/100BASE-TX/10BASE-T Clock Alignment Control Register
(Address 1Ch, Shadow Value 00011),” on page 94
Table 19, ”Register Map,” on page 47
“1000BASE-T/100BASE-TX/10BASE-T LED Selector 1” on page 102
“1000BASE-T/100BASE-TX/10BASE-T LED Selector 2” on page 104
“Secondary SerDes Control” on page 109
Power-Down in “1000BASE-T/100BASE-TX/10BASE-T Registers Descriptions”
on page 51, “Primary SerDes Register Descriptions” on page 130, “Secondary
SerDes Registers” on page 150
Table 103, ”Secondary SerDes Control Register,” on page 164
“Misc 1” on page 160
“Ordering Information” on page 192
Added:
Table 64, ”Primary SerDes Control Register (Address 1C, Shadow Value =
10110),” on page 113
Table 93, ”1000BASE-X Auto-Negotiation Secondary SerDes Register,” on page
156
Table 94, ”1000BASE-X Auto-Negotiation Next Page Transmit Register,” on page
157
Table 95, ”1000BASE-X Auto-Negotiation Link Partner Next Page Register,” on
page 158
Table 103, ”Secondary SerDes Control Register,” on page 164
Table 113, ”Secondary SerDes Lineside Loopback Control Register,” on page 176
“Expansion Register 42h: Operating Mode Status” on page 146
“Expansion Register 50H:SerDes/SGMII RX Control” on page 149
“1000BASE-X Extended Status” on page 159
“Packet Counter” on page 162
“Error Counter” on page 163
“Misc 1000BASE-X Control 2” on page 165
“Misc 1000-X Control 3” on page 166
“Auto-Negotiation 1000BASE-X Debug” on page 167
“Auxiliary 1000BASE-X Status” on page 170
“Misc 1000BASE-X Status” on page 171
“Spare Register” on page 173
Page vi
Document 5482S-DS09-R
Broadcom Corporation
2/16/2009 1539I
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Data Sheet
02/13/09
Revision
5482S-DS04-R
Date
03/14/06
Change Description
Updated:
BCM5482S
”Interrupt Function” on page 42
Table 104, ”Clock Input Timing,” on page 157
Table 112, ”DC Characteristics,” on page 162
”Mechanical Drawings” on page 167
Added:
Table 60, ”SerDes 100BASE-FX Status Register (Address 1Ch, Shadow Value =
10001),” on page 102
Table 89, ”Auto-Negotiation Advertisement Register (Address 04h),” on page 142
Table 94, ”Misc 1 Register (Address 10h),” on page 147
Table 95, ”100BASE-FX Status Register (Address 11h),” on page 148
Table 96, ”100BASE-FX Test Register (Address 12h),” on page 149
Table 99, ”Secondary SerDes Auxiliary 1000BASE-X Control Register (Address
1Bh),” on page 151
5482S-DS03-R
01/16/06
Updated:
“Secondary SerDes Interface Data Input” description, pins A3/B3 and A9/B9 in
Table 3, ”Hardware Signal Descriptions,” on page 16
“DAC Bias Resistor” description, pin L1 in Table 3, ”Hardware Signal Descriptions,”
on page 16
“Shadow value XXX” to “shadow value 111” in ”RGMII-to-Copper Mode” on page
34
Table note, “Expansion register 03h, bit 1 = 1,” to “Expansion register 52h, bit 2 =
1” in Table 13, ”SGMII Interface Pins,” on page 36
Step 3 below ”SGMII-to-SGMII Slave Mode” on page 36
Included reference to Table 86, ”Expansion Register 52h: SerDes/SGMII Control,”
on page 137 in Table 19, ”Register Map,” on page 45
Bit 11 description in Table 44, ”1000BASE-T/100BASE-TX/10BASE-T Misc Test
Register (Address 18h, Shadow Value 100),” on page 78
Table 53 on page 92, to include descriptions for bits 5 and 6
Typographical errors throughout relating to the phrase, “10/100/1000BASE-T”
Figure 20, ”121-Pin FBGA Package,” on page 158
Added:
Description for “Bias VDD,” pin L2, to Table 3, ”Hardware Signal Descriptions,” on
page 16
Third paragraph below ”PHY Address” on page 24
Step 4 below ”SGMII-to-SGMII Slave Mode” on page 36
Below Table 53 on page 92, added ”Signal Detect/Energy Detect Enable” on page
93
”Expansion Register 52h: SerDes/SGMII Control” on page 137, and Table 86,
”Expansion Register 52h: SerDes/SGMII Control,” on page 137
Table 88, ”1000BASE-X Auto-Negotiation Link Partner Ability Register,” on page
140
Table 94, ”Secondary SerDes Interrupt MASK Register,” on page 146
Document 5482S-DS09-R
Page vii
Broadcom Corporation
2/16/2009 1539I
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Revision
5482S-DS03-R
(continued)
Date
01/16/06
Change Description
Removed:
The note “In RGMII-to-fiber mode the following features are not supported: RXC
clock delay with respect to RXD data, In-band status (optional) mode” from ”RGMII-
to-Copper Mode” on page 34
The phrase “Use the following methods to enter and exit the ultra-low-power mode”
from ”Ultra-Low Power-Down Mode” on page 27
The sentence “CRS is still asserted when a valid frame is received” from ”Bypass
4B/5B Encoder/Decoder (100BASE-T)” on page 66
The sentence “The TXEN signal also echoes on the CRS pin and CRS deassertion
directly follows the TXEN deassertion” from ”10BASE-T Echo Mode” on page 76
5482S-DS02-R
11/07/05
Updated:
“Ultra-Low Power-Down Mode” on page 27
5482S-DS01-R
07/29/05
Added:
Industrial temperature version
Table 99, ”Theta-Ja vs. Airflow for the FBGA Package with Heat Sink,” on page 161
Updated:
”Ordering Information” on page 162
5482S-DS00-R
05/19/05
Initial release.
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2009 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, and Ethernet@Wirespeed™ are
among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the
EU. Any other trademarks or trade names mentioned are the property of their respective owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or
certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous
substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS", WITHOUT
WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING,
WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, AND NON-INFRINGEMENT.
2/16/2009 1539I
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