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数字系统实验-电子钟.docx
一、功能实现
二、源代码
2.1 顶层图设计
2.2 时钟分频模块
2.3 秒计时模块
2.4 分计时模块
2.5 时计时模块
2.6 置数模块
2.7 按键消抖模块
2.8 报时模块
2.9 LED灯管显示模块
三、仿真
3.1 时钟19:59:58仿真
3.2 时钟23:59:58仿真
四、下载验证
4.1 管脚设计图
4.2 编译结果图
4.3 下载验证图
目录
一、功能实现............................................................................................... 2
二、源代码................................................................................................... 2
2.1 顶层图设计.................................................................................... 2
2.2 时钟分频模块................................................................................ 2
2.3 秒计时模块.................................................................................... 3
2.4 分计时模块.................................................................................... 4
2.5 时计时模块.................................................................................... 6
2.6 置数模块........................................................................................ 7
2.7 按键消抖模块................................................................................ 9
2.8 报时模块...................................................................................... 11
2.9 LED 灯管显示模块.......................................................................13
三、仿真..................................................................................................... 15
3.1 时钟 19:59:58 仿真...................................................................... 15
3.2 时钟 23:59:58 仿真...................................................................... 15
四、下载验证............................................................................................. 16
4.1 管脚设计图.................................................................................. 16
4.2 编译结果图.................................................................................. 16
4.3 下载验证图.................................................................................. 17
一、功能实现
1. 时分秒时钟显示；
2. 定点报时功能，x 点钟报时 x 次；
3. 时钟清零。按下按钮就可使时钟时、分、秒数字请零；
4. 按键消抖功能；
5. 置数功能。能够通过按按钮对时、分、秒进行置数。
二、源代码
2.1 顶层图设计
2.2 时钟分频模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk_sourse is
port(
clk:in std_logic;
clk2:out std_logic;
clk3:out std_logic
);
end clk_sourse;
architecture a of clk_sourse is
signal clk0:std_logic;
signal clk1:std_logic;
begin
clk2<=clk1;
clk3<=clk0;
process(clk)
variable cnt:integer range 0 to 50000000;
variable cnt1:integer range 0 to 5000;
begin
if(clk'event and clk='1')then
cnt:=cnt+1;
cnt1:=cnt1+1;
if(cnt=50000000)then
clk1<=not clk1;
cnt:=0;
end if;
if(cnt1=5000)then
clk0<=not clk0;
cnt1:=0;
end if;
end if;
end process;
end a;
2.3 秒计时模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter1 is
port(
clk:in std_logic;
clr:in std_logic;
key1:in std_logic;
min:out std_logic;
chg0:in std_logic_vector(3 downto 0);
chg1:in std_logic_vector(3 downto 0);
data0:out std_logic_vector(3 downto 0);
data1:out std_logic_vector(3 downto 0)
);
end counter1;
architecture a of counter1 is
signal cnt0:std_logic_vector(3 downto 0):="0000";
signal cnt1:std_logic_vector(3 downto 0):="0000";
begin
process(clk,clr,key1)
begin
if(clr='1' and key1='1')then
if(clk'event and clk='1')then
cnt0<=cnt0+1;
if(cnt0=9)then
cnt0<="0000";
cnt1<=cnt1+1;
end if;
if(cnt1=5 and cnt0=9)then
cnt0<="0000";
cnt1<="0000";
min<='1';
else
min<='0';
elsif(clr='0' and key1='1')then
elsif(key1='0' and clr='1')then
end if;
end if;
cnt0<="0000";
cnt1<="0000";
cnt0<=chg0;
cnt1<=chg1;
else
null;
end if;
data0<=cnt0;
data1<=cnt1;
end process;
end a;
2.4 分计时模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter2 is
port(
clk:in std_logic;
clr,key1:in std_logic;--reset
hour:out std_logic;
chg2:in std_logic_vector(3 downto 0);
chg3:in std_logic_vector(3 downto 0);
data2:out std_logic_vector(3 downto 0);
data3:out std_logic_vector(3 downto 0)
);
end counter2;
architecture a of counter2 is
signal cnt0:std_logic_vector(3 downto 0):="0000";--9
signal cnt1:std_logic_vector(3 downto 0):="0000";--1
begin
process(clk,clr,key1)
begin
if(clr='1' and key1='1')then
if(clk'event and clk='1')then
cnt0<=cnt0+1;
if(cnt0=9)then
cnt0<="0000";
cnt1<=cnt1+1;
end if;
if(cnt1=5 and cnt0=9)then
cnt0<="0000";
cnt1<="0000";
hour<='1';
else
hour<='0';
elsif(clr='0' and key1='1')then
elsif(key1='0' and clr='1')then
end if;
end if;
cnt0<="0000";
cnt1<="0000";
hour<='0';
cnt0<=chg2;
cnt1<=chg3;
else
null;
end if;
data2<=cnt0;
data3<=cnt1;
end process;
end a;
2.5 时计时模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter3 is
port(
clk:in std_logic;
clr,key1:in std_logic;
chg4,chg5:in std_logic_vector(3 downto 0);
key2:in std_logic;
data4:out std_logic_vector(3 downto 0);
data5:out std_logic_vector(3 downto 0)
);
end counter3;
architecture a of counter3 is
signal cnt0:std_logic_vector(3 downto 0):="0000";--hour gewei
signal cnt1:std_logic_vector(3 downto 0):="0000";--hour shiwei
begin
process(clk,clr,key1,key2)
begin
if(clr='1' and key1='1' and key2='1')then
if(clk'event and clk='1')then
cnt0<=cnt0+1;
if(cnt0=9)then
cnt0<="0000";
cnt1<=cnt1+1;
end if;
if(cnt1=2 and cnt0=3)then
cnt0<="0000";
cnt1<="0000";
end if;
end if;
elsif(clr='0' and key1='1' and key2='1')then
cnt0<="0000";
elsif(key1='0' and key2='0' and clr='1')then
cnt1<="0000";
cnt0<=chg4;
cnt1<=chg5;
else
null;
end if;
data4<=cnt0;--ge
data5<=cnt1;--shi
end process;
end a;
2.6 置数模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity chgclk is
port(
clk:in std_logic;
key1,key2,clr:in std_logic;--add,mode
t:out std_logic_vector(1 downto 0);--testport
clk2:out std_logic;
cdata0:out std_logic_vector(3 downto 0);
cdata1:out std_logic_vector(3 downto 0);
cdata2:out std_logic_vector(3 downto 0);
cdata3:out std_logic_vector(3 downto 0);
cdata4:out std_logic_vector(3 downto 0);
cdata5:out std_logic_vector(3 downto 0)
);
end chgclk;
--
--
architecture a of chgclk is
signal cnt0:std_logic_vector(3 downto 0):="0000";
signal cnt1:std_logic_vector(3 downto 0):="0000";
signal cnt2:std_logic_vector(3 downto 0):="0000";
signal cnt3:std_logic_vector(3 downto 0):="0000";
signal cnt4:std_logic_vector(3 downto 0):="0000";
signal cnt5:std_logic_vector(3 downto 0):="0000";
signal clk1:std_logic:='0';
begin
process(clk)
variable clkcnt:integer range 0 to 1000;--test
begin
if(clk'event and clk='1')then
clkcnt:=clkcnt+1;
if(clkcnt=1000)then--test
clk1<=not clk1;
clk2<=clk1;--test
clkcnt:=0;
end if;
--
end if;
end process;
process(clk1,key1,key2,clr)--change
begin
if(clr='1')then
if(key1='0' and key2='1')then
if(clk1'event and clk1='1')then
cnt0<=cnt0+1;
if(cnt0=9)then
cnt0<="0000";
cnt1<=cnt1+1;
end if;
if(cnt1=5 and cnt0=9)then
cnt0<="0000";
cnt1<="0000";
end if;
end if;
cdata0<=cnt0;
cdata1<=cnt1;
elsif(key1='1' and key2='0')then
if(clk1'event and clk1='1')then
cnt2<=cnt2+1;
if(cnt2=9)then
cnt2<="0000";
cnt3<=cnt3+1;
end if;
if(cnt3=5 and cnt2=9)then
cnt2<="0000";
cnt3<="0000";
end if;
end if;
cdata2<=cnt2;
cdata3<=cnt3;
elsif(key1='0' and key2='0')then
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