全志A20芯片原厂手册.pdf

发布时间：2022-06-01 发布人：admin 分类：说明书资料大小：8.13M 资料格式：pdf 举报版权申诉

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Declaration

Revision History

Table of Contents

Chapter 1 System

1.1. Overview

1.2. A20 Block Diagram

1.3. Memory Mapping

1.4. CPU Configuration

1.4.1. Overview

1.4.2. CPU Configuration Register List

1.4.3. CPUCFG Register Description

1.4.3.1. CPU0 Reset Control(Default: 0x00000003)

1.4.3.2. CPU0 Control Register(Default :0x00000000)

1.4.3.3. CPU0 Status Register(Default : 0x00000000)

1.4.3.4. CPU1 Reset Control(Default: 0x00000000)

1.4.3.5. CPU1 Control Register(Default :0x00000000)

1.4.3.6. CPU1 Status Register(Default : 0x00000000)

1.4.3.7. General Control Register(Default :0x00000020)

1.4.3.8. Event Input Register(Default : 0x00000000)

1.4.3.9. Private Register (Default: 0x00000000)

1.4.3.10. Idle Counter 0 Low Register (Default: 0x00000000)

1.4.3.11. Idle Counter 0 High Register (Default: 0x00000000)

1.4.3.12. Idle Counter 0 Control Register (Default: 0x00000000)

1.4.3.13. Idle Counter 1 Low Register (Default: 0x00000000)

1.4.3.14. Idle Counter 1 High Register (Default: 0x00000000)

1.4.3.15. Idle Counter 1 Control Register (Default: 0x00000000)

1.4.3.16. OSC24M 64-bit Counter Control Register (Default: 0x00000000)

1.4.3.17. OSC24M 64-bit Counter Low Register (Default: 0x00000000)

1.4.3.18. OSC24M 64-bit Counter High Register (Default: 0x00000000)

1.4.3.19. LOSC 64-bit Counter Control Register (Default: 0x00000000)

1.4.3.20. LOSC 64-bit Counter Low Register (Default: 0x00000000)

1.4.3.21. LOSC 64-bit Counter High Register (Default: 0x00000000)

1.5. CCU

1.5.1. Overview

1.5.2. Clock Tree Diagram

1.5.3. CCU Register List

1.5.4. CCU Register Description

1.5.4.1. PLL1-Core(Default: 0x21005000)

1.5.4.2. PLL1-Tuning(Default: 0x0A101000)

1.5.4.3. PLL2-Audio(Default: 0x08100010)

1.5.4.4. PLL2-Tuning(Default: 0x00000000)

1.5.4.5. PLL3-Video 0(Default: 0x0010D063)

1.5.4.6. PLL4-VE(Default: 0x21009911)

1.5.4.7. PLL5-DDR(Default: 0x11049280)

1.5.4.8. PLL5-Tuning(Default: 0x14888000)

1.5.4.9. PLL6-SATA(Default: 0x21009911)

1.5.4.10. PLL6-Tuning

1.5.4.11. PLL7-Video 1(Default: 0x0010D063)

1.5.4.12. PLL1-Tuning2(Default: 0x00000000)

1.5.4.13. PLL5-Tuning2(Default: 0x00000000)

1.5.4.14. PLL8-GPU(Default: 0x21009911)

1.5.4.15. OSC24M (Default: 0x00138013)

1.5.4.16. CPU/AHB/APB0 Clock Ratio(Default: 0x00010010)

1.5.4.17. APB1 Clock Divide Ratio(Default: 0x00000000)

1.5.4.18. AHB Module Clock Gating Register 0(Default: 0x00000000)

1.5.4.19. AHB Module Clock Gating Register 1(Default: 0x00000000)

1.5.4.20. APB0 Module Clock Gating(Default: 0x00000000)

1.5.4.21. APB1 Module Clock Gating(Default: 0x00000000)

1.5.4.22. NAND Clock(Default: 0x00000000)

1.5.4.23. MS Clock(Default: 0x00000000)

1.5.4.24. SD/MMC 0 CLOCK(DEFAULT: 0X00000000)

1.5.4.25. SD/MMC 1 Clock(Default: 0x00000000)

1.5.4.26. SD/MMC 2 Clock(Default: 0x00000000)

1.5.4.27. SD/MMC 3 Clock(Default: 0x00000000)

1.5.4.28. TS Clock(Default: 0x00000000)

1.5.4.29. SS Clock(Default: 0x00000000)

1.5.4.30. SPI0 Clock(Default: 0x00000000)

1.5.4.31. SPI1 Clock(Default: 0x00000000)

1.5.4.32. SPI2 Clock(Default: 0x00000000)

1.5.4.33. IR 0 Clock(Default: 0x00000000)

1.5.4.34. IR 1 Clock(Default: 0x00000000)

1.5.4.35. IIS0 Clock(Default: 0x00000000)

1.5.4.36. AC97 Clock(Default: 0x00030000)

1.5.4.37. KEYPAD Clock(Default: 0x0000001F)

1.5.4.38. SATA Clock(Default: 0x00000000)

1.5.4.39. USB Clock(Default: 0x00000000)

1.5.4.40. SPI3 Clock(Default: 0x00000000)

1.5.4.41. IIS1 Clock(Default: 0x00000000)

1.5.4.42. IIS2 Clock(Default: 0x00000000)

1.5.4.43. DRAM CLK(Default: 0x00000000)

1.5.4.44. DE-BE 0 Clock(Default: 0x00000000)

1.5.4.45. DE-BE 1 Clock(Default: 0x00000000)

1.5.4.46. DE-FE 0 Clock(Default: 0x00000000)

1.5.4.47. DE-FE 1 Clock(Default: 0x00000000)

1.5.4.48. DE-MP Clock(Default: 0x00000000)

1.5.4.49. LCD 0 CH0 Clock(Default: 0x00000000)

1.5.4.50. LCD 1 CH0 Clock(Default: 0x00000000)

1.5.4.51. CSI special clock regitster(Default: 0x00000000)

1.5.4.52. TVD Clock(Default: 0x00000000)

1.5.4.53. LCD 0 CH1 Clock(Default: 0x00000000)

1.5.4.54. LCD 1 CH1 Clock(Default: 0x00000000)

1.5.4.55. CSI 0 Clock(Default: 0x00000000)

1.5.4.56. CSI 1 Clock(Default: 0x00000000)

1.5.4.57. VE Clock(Default: 0x00000000)

1.5.4.58. Audio Codec Clock(Default: 0x00000000)

1.5.4.59. AVS Clock(Default: 0x00000000)

1.5.4.60. ACE Clock(Default: 0x00000000)

1.5.4.61. LVDS Clock(Default: 0x00000000)

1.5.4.62. HDMI Clock(Default: 0x00000000)

1.5.4.63. Mali400 Clock(Default: 0x00000000)

1.5.4.64. MBUS Clock Control(Default: 0x00000000)

1.5.4.65. GMAC Clock Register (Default: 0x00000000)

1.5.4.66. HDMI1 Reset Register (Default: 0x00000000)

1.5.4.67. HDMI1 Control Register (Default: 0x00000000)

1.5.4.68. HDMI1 Slow Clock Register (Default: 0x00000000)

1.5.4.69. HDMI1 Repeat Clock Register (Default: 0x00000000)

1.5.4.70. CLK_OUTA_REG (Default: 0x00000000)

1.5.4.71. CLK_OUTB_REG (Default: 0x00000000)

1.6. System Boot

1.6.1. Overview

1.6.2. System Boot Diagram

1.7. System Control

1.7.1. Overview

1.7.2. System Control Register List

1.7.3. System Control Register

1.7.3.1. SRAM Control Register 0(Default: 0x7FFFFFFF)

1.7.3.2. SRAM Control Register 1(Default: 0x00001300)

1.7.3.3. Version Register(Default: 0x00000000)

1.7.3.4. NMI Interrupt Control Register(Default: 0x00000000)

1.7.3.5. NMI Interrupt Pending Register(Default: 0x00000000)

1.7.3.6. NMI Interrupt Enable Register(Default: 0x00000000)

1.8. PWM

1.8.1. Overview

1.8.2. PWM Register List

1.8.3. PWM Register Description

1.8.3.1. PWM Control Register(Default: 0x00000000)

1.8.3.2. PWM Channel 0 Period Register

1.8.3.3. PWM Channel 1 Period Register

1.9. Timer

1.9.1. Overview

1.9.2. Timer Register List

1.9.3. Timer Register Description

1.9.3.1. Timer IRQ Enable Register(Default: 0x00000000)

1.9.3.2. Timer IRQ Status Register(Default: 0x00000000)

1.9.3.3. Timer 0 Control Register(Default: 0x00000004)

1.9.3.4. Timer 0 Interval Value Register

1.9.3.5. Timer 0 Current Value Register

1.9.3.6. Timer 1 Control Register(Default: 0x00000004)

1.9.3.7. Timer 1 Interval Value Register

1.9.3.8. Timer 1 Current Value Register

1.9.3.9. Timer 2 Control Register(Default: 0x00000004)

1.9.3.10. Timer 2 Interval Value Register

1.9.3.11. Timer 2 Current Value Register

1.9.3.12. Timer 3 Control Register(Default: 0x00000000)

1.9.3.13. Timer 3 Interval Value Register

1.9.3.14. Timer 4 Control Register(Default: 0x00000004)

1.9.3.15. Timer 4 Interval Value Register

1.9.3.16. Timer 4 Current Value Register

1.9.3.17. Timer 5 Control Register(Default: 0x00000004)

1.9.3.18. Timer 5 Interval Value Register

1.9.3.19. Timer 5 Current Value Register

1.9.3.20. AVS Counter Control Register(Default: 0x00000000)

1.9.3.21. AVS Counter 0 Register(Default: 0x00000000)

1.9.3.22. AVS Counter 1 Register(Default: 0x00000000)

1.9.3.23. AVS Counter Divisor Register(Default: 0x05DB05DB)

1.9.3.24. Watchdog Control Register

1.9.3.25. Watchdog Mode Register(Default: 0x00000000)

1.9.3.26. LOSC Control Register (Default: 0x00004000)

1.9.3.27. RTC YY-MM-DD Register (Default: 0x00000000)

1.9.3.28. RTC HH-MM-SS Register

1.9.3.29. Alarm Counter DD-HH-MM-SS Register

1.9.3.30. Alarm Week HH-MM-SS Register

1.9.3.31. Alarm Enable Register

1.9.3.32. Alarm IRQ Enable Register

1.9.3.33. Alarm IRQ Status Register

1.9.3.34. Timer General Purpose Register

1.9.3.35. Alarm Config Register (Default: 0x00000000)

1.10. High Speed Timer

1.10.1. Overview

1.10.2. High Speed Timer Register List

1.10.3. High Speed Timer Controller Register

1.10.3.1. HS Timer IRQ Enable Register (Default: 0x00000000)

1.10.3.2. HS Timer IRQ Status Register (Default: 0x00000000)

1.10.3.3. HS Timer 0 Control Register (Default: 0x00000000)

1.10.3.4. HS Timer 0 Interval Value Lo Register

1.10.3.5. HS Timer 0 Interval Value Hi Register

1.10.3.6. HS Timer 0 Current Value Lo Register

1.10.3.7. HS Timer 0 Current Value Hi Register

1.10.3.8. HS Timer 1 Control Register (Default: 0x00000000)

1.10.3.9. HS Timer 1 Interval Value Lo Register

1.10.3.10. HS Timer 1 Interval Value Hi Register

1.10.3.11. HS Timer 1 Current Value Lo Register

1.10.3.12. HS Timer 1 Current Value Hi Register

1.10.3.13. HS Timer 2 Control Register (Default: 0x00000000)

1.10.3.14. HS Timer 2 Interval Value Lo Register

1.10.3.15. HS Timer 2 Interval Value Hi Register

1.10.3.16. HS Timer 2 Current Value Lo Register

1.10.3.17. HS Timer 2 Current Value Hi Register

1.10.3.18. HS Timer 3 Control Register (Default: 0x00000000)

1.10.3.19. HS Timer 3 Interval Value Lo Register

1.10.3.20. HS Timer 3 Interval Value Hi Register

1.10.3.21. HS Timer 3 Current Value Lo Register

1.10.3.22. HS Timer 3 Current Value Hi Register

1.11. GIC

1.11.1. Interrupt Source

1.12. DMA

1.12.1. Overview

1.12.2. DMA Register List

1.12.3. DMA Controller Register Description

1.12.3.1. DMA IRQ Enable Register(Default: 0x00000000)

1.12.3.2. DMA IRQ Pending Status Register(Default: 0x00000000)

1.12.3.3. NDMA Auto Gating Register(Default: 0x00000000)

1.12.3.4. Normal DMA Configuration Register(Default: 0x00000000)

1.12.3.5. Normal DMA Source Address Register(Default: 0x00000000)

1.12.3.6. Normal DMA Destination Address Register(Default: 0x00000000)

1.12.3.7. Normal DMA Byte Counter Register(Default: 0x00000000)

1.12.3.8. Dedicated DMA Configuration Register(Default: 0x00000000)

1.12.3.9. Dedicated DMA Source Start Address Register

1.12.3.10. Dedicated DMA Destination Start Address Register

1.12.3.11. Dedicated DMA Byte Counter Register

1.12.3.12. Dedicated DMA Parameter Register

1.13. Audio Codec

1.13.1. Overview

1.13.2. Audio Codec Block Diagram

1.13.3. Audio Codec Register List

1.13.4. Audio Codec Register Description

1.13.4.1. DAC Digital Part Control Register

1.13.4.2. DAC FIFO Control Register

1.13.4.3. DAC FIFO Status Register

1.13.4.4. DAC TX DATA register

1.13.4.5. DAC Analog Control Register

1.13.4.6. DAC/ADC Analog Performance Tuning Register

1.13.4.7. ADC FIFO Control Register

1.13.4.8. ADC FIFO Status Register

1.13.4.9. ADC RX DATA register

1.13.4.10. ADC Analog Control Register

1.13.4.11. DAC TX Counter register

1.13.4.12. ADC RX Counter register

1.13.4.13. Bias & DA16 Calibration Verify Register

1.13.4.14. MIC Gain & Phone out Control Register

1.14. LRADC

1.14.1. Overview

1.14.2. LRADC Block Diagram

1.14.3. LRADC Register List

1.14.4. LRADC Register Description

1.14.4.1. LRADC Control Register

1.14.4.2. LRADC Interrupt Control Register

1.14.4.3. LRADC Interrupt Status Register

1.14.4.4. LRADC Data 0 Register

1.14.4.5. LRADC Data 1 Register

1.15. TP

1.15.1. Overview

1.15.2. Typical Application Circuit

1.15.3. TP Clock Tree

1.15.4. A/D Conversion Time

1.15.5. Principle of Operation

1.15.6. TP Register List

1.15.7. TP Register Description

1.15.7.1. TP Control Register 0

1.15.7.2. TP control Register 1

1.15.7.3. TP control Register 2

1.15.7.4. Median and Averaging Filter Control Register

1.15.7.5. TP Interrupt& FIFO Control Register

1.15.7.6. TP Interrupt& FIFO Status Register

1.15.7.7. TP Temperature Period Register

1.15.7.8. Common Data Register

1.15.7.9. Temperature Data Register

1.15.7.10. TP Data Register

1.15.7.11. 3.6.11 TP PORT IO Configure Register

1.15.7.12. TP Port Data Register

1.16. Security System

1.16.1. Overview

1.16.2. Security System Block Diagram

1.16.3. Security System Register List

1.16.4. Security System Register Description

1.16.4.1. Security System Control Register

1.16.4.2. Security System Key [n] Register

1.16.4.3. Security System IV[n] Register

1.16.4.4. Security System Counter[n] Register

1.16.4.5. Security System FIFO Control/ Status Register

1.16.4.6. Security System Interrupt Control/ Status Register

1.16.4.7. Security System Message Digest[n] Register

1.16.4.8. Security System CTS Length Register

1.16.4.9. Security System RX FIFO Register

1.16.4.10. Security System TX FIFO Register

1.16.4.11. Security System Clock Requirement

1.17. Security JTAG

1.17.1. Overview

1.17.2. Security JTAG Register List

1.17.3. Security JTAG Register Description

1.17.3.1. SJTAG Password 0 Register

1.17.3.2. SJTAG Password 1 Register

1.17.3.3. SJTAG Status Register

1.18. Security ID

1.18.1. Overview

1.18.2. SID Block Diagram

1.18.3. Security System Register List

1.18.4. Security ID Register Description

1.18.4.1. SID Root Key 0 Register

1.18.4.2. SID Root Key 1 Register

1.18.4.3. SID Root Key 2 Register

1.18.4.4. SID Root Key 3 Register

1.18.4.5. SID Boot Key 0 Register

1.18.4.6. SID Boot Key 1 Register

1.18.4.7. SID Boot Key 2 Register

1.18.4.8. SID Boot Key 3 Register

1.18.4.9. SID SJTAG Key 0 Register

1.18.4.10. SID SJTAG Key 1 Register

1.18.4.11. SID Common Key Register

1.18.4.12. SID Program/Read Control Register

1.18.4.13. SID Program Key Value Register

1.18.4.14. SID Read Key Value Register

1.19. Port Controller

1.19.1. Port Description

1.19.2. Port Configuration Table

1.19.3. Port Register List

1.19.4. Port Register Description

1.19.4.1. PA Configure Register 0

1.19.4.2. PA Configure Register 1

1.19.4.3. PA Configure Register 2

1.19.4.4. PA Configure Register 3

1.19.4.5. PA Data Register

1.19.4.6. PA Multi-Driving Register 0

1.19.4.7. PA Multi-Driving Register 1

1.19.4.8. PA Pull Register 0

1.19.4.9. PA Pull Register 1

1.19.4.10. PB Configure Register 0

1.19.4.11. PB Configure Register 1

1.19.4.12. PB Configure Register 2

1.19.4.13. PB Configure Register 3

1.19.4.14. PB Data Register

1.19.4.15. PB Multi-Driving Register 0

1.19.4.16. PB Multi-Driving Register 1

1.19.4.17. PB Pull Register 0

1.19.4.18. PB Pull Register 1

1.19.4.19. PC Configure Register 0

1.19.4.20. PC Configure Register 1

1.19.4.21. PC Configure Register 2

1.19.4.22. PC Configure Register 3

1.19.4.23. PC Data Register

1.19.4.24. PC Multi-Driving Register 0

1.19.4.25. PC Multi-Driving Register 1

1.19.4.26. PC Pull Register 0

1.19.4.27. PC Pull Register 1

1.19.4.28. PD Configure Register 0

1.19.4.29. PD Configure Register 1

1.19.4.30. PD Configure Register 2

1.19.4.31. PD Configure Register 3

1.19.4.32. PD Data Register

1.19.4.33. PD Multi-Driving Register 0

1.19.4.34. PD Multi-Driving Register 1

1.19.4.35. PD Pull Register 0

1.19.4.36. PD Pull Register 1

1.19.4.37. PE Configure Register 0

1.19.4.38. PE Configure Register 1

1.19.4.39. PE Configure Register 2

1.19.4.40. PE Configure Register 3

1.19.4.41. PE Data Register

1.19.4.42. PE Multi-Driving Register 0

1.19.4.43. PE Multi-Driving Register 1

1.19.4.44. PE Pull Register 0

1.19.4.45. PE Pull Register 1

1.19.4.46. PF Configure Register 0

1.19.4.47. PF Configure Register 1

1.19.4.48. PF Configure Register 2

1.19.4.49. PF Configure Register 3

1.19.4.50. PF Data Register

1.19.4.51. PF Multi-Driving Register 0

1.19.4.52. PF Multi-Driving Register 1

1.19.4.53. PF Pull Register 0

1.19.4.54. PF Pull Register 1

1.19.4.55. PG Configure Register 0

1.19.4.56. PG Configure Register 1

1.19.4.57. PG Configure Register 2

1.19.4.58. PG Configure Register 3

1.19.4.59. PG Data Register

1.19.4.60. PG Multi-Driving Register 0

1.19.4.61. PG Multi-Driving Register 1

1.19.4.62. PG Pull Register 0

1.19.4.63. PG Pull Register 1

1.19.4.64. PH Configure Register 0

1.19.4.65. PH Configure Register 1

1.19.4.66. PH Configure Register 2

1.19.4.67. PH Configure Register 3

1.19.4.68. PH Data Register

1.19.4.69. PH Multi-Driving Register 0

1.19.4.70. PH Pull Register 0

1.19.4.71. PH Pull Register 1

1.19.4.72. PI Configure Register 0

1.19.4.73. PI Configure Register 1

1.19.4.74. PI Configure Register 2

1.19.4.75. PI Configure Register 3

1.19.4.76. PI Data Register

1.19.4.77. PI Multi-Driving Register 0

1.19.4.78. PI Multi-Driving Register 1

1.19.4.79. PI Pull Register 0

1.19.4.80. PI Pull Register 1

1.19.4.81. PIO Interrupt Configure Register 0

1.19.4.82. PIO Interrupt Configure Register 1

1.19.4.83. PIO Interrupt Configure Register 2

1.19.4.84. PIO Interrupt Configure Register 3

1.19.4.85. PIO Interrupt Control Register

1.19.4.86. PIO Interrupt Status Register

1.19.4.87. PIO Interrupt Debounce Register

Chapter 2 Memory

2.1. DRAM

1.19.5. Overview

2.2. NAND Flash

1.19.6. Overview

1.19.7. Nand Flash Block Diagram

1.19.8. NFC Timing Diagram

1.19.9. NFC Operation Guide

Chapter 3 Graphic

3.1. Mixer Processor

3.1.1. Overview

3.1.2. Mixer Processor Block Diagram

3.1.3. MP Register List

3.1.4. MP Register Description

3.1.4.1. Mixer control register

3.1.4.2. Mixer Status register

3.1.4.3. Input DMA globe control register

3.1.4.4. Input DMA start address high 4bits register

3.1.4.5. Input DMA start address low 32bits register

3.1.4.6. Input DMA line width register

3.1.4.7. INPUT DMA MEMORY BLOCK SIZE REGISTER

3.1.4.8. Input DMA memory block coordinate control register

3.1.4.9. Input DMA setting register

3.1.4.10. Input DMA fill-color register

3.1.4.11. Color space converter 0 control register

3.1.4.12. Color space converter 1 control register

3.1.4.13. Scaler control register

3.1.4.14. Scaling output size register

3.1.4.15. Scaler horizontal scaling factor register

3.1.4.16. Scaler vertical scaling factor register

3.1.4.17. Scaler horizontal start phase setting register

3.1.4.18. Scaler vertical start phase setting register

3.1.4.19. ROP control register

3.1.4.20. ROP channel 3 index 0 control table setting register

3.1.4.21. ROP channel 3 index 1 control table setting register

3.1.4.22. Alpha / Color key control register

3.1.4.23. Color key min color register

3.1.4.24. Color key max color register

3.1.4.25. Fill color of ROP output setting register

3.1.4.26. Color space converter 2 control register

3.1.4.27. Output control register

3.1.4.28. Output size register

3.1.4.29. Output address high 4bits register

3.1.4.30. Output address low 32bits register

3.1.4.31. Output line width register

3.1.4.32. Output alpha control register

3.1.4.33. CSC0/1 Y/G coefficient register

3.1.4.34. CSC0/1 Y/G constant register

3.1.4.35. CSC0/1 U/R coefficient register

3.1.4.36. CSC0/1 U/R constant register

3.1.4.37. CSC0/1 V/B coefficient register

3.1.4.38. CSC0/1 V/B constant register

3.1.4.39. CSC2 Y/G coefficient register

3.1.4.40. CSC2 Y/G constant register

3.1.4.41. CSC2 U/R coefficient register

3.1.4.42. CSC2 U/R constant register

3.1.4.43. CSC2 V/B coefficient register

3.1.4.44. CSC2 V/B constant register

3.1.4.45. Scaling horizontal filtering coefficient RAM block

3.1.4.46. Scaling vertical filtering coefficient RAM block

3.1.4.47. Palette Table

3.1.4.48. Input data pixel sequence table

3.1.4.49. Output data pixel sequence

Chapter 4 Image

4.1. CSI0

4.1.1. Overview

4.1.2. CSI0 Block Diagram

4.1.3. CSI0 Description

4.1.3.1. CSI data ports

4.1.3.2. Timing Diagram

4.1.4. CSI0 Register List

4.1.5. CSI0 Register Description

4.1.5.1. CSI Enable Register

4.1.5.2. CSI configuration register

4.1.5.3. CSI capture control register

4.1.5.4. CSI horizontal scale register

4.1.5.5. CSI Channel_0 FIFO 0 output buffer-A address register

4.1.5.6. CSI Channel_0 FIFO 0 output buffer-B address register

4.1.5.7. CSI Channel_0 FIFO 1 output buffer-A address register

4.1.5.8. CSI Channel_0 FIFO 1 output buffer-B address register

4.1.5.9. CSI Channel_0 FIFO 2 output buffer-A address register

4.1.5.10. CSI Channel_0 FIFO 2 output buffer-B address register

4.1.5.11. CSI Channel_0 output buffer control register

4.1.5.12. CSI Channel_0 status register

4.1.5.13. CSI Channel_0 interrupt enable register

4.1.5.14. CSI Channel_0 interrupt status register

4.1.5.15. CSI Channel_0 horizontal size register

4.1.5.16. CSI Channel_0 vertical size register

4.1.5.17. CSI Channel_0 buffer length register

4.1.5.18. CSI Channel_1 FIFO 0 output buffer-A address register

4.1.5.19. CSI Channel_1 FIFO 0 output buffer-B address register

4.1.5.20. CSI Channel_1 FIFO 1 output buffer-A address register

4.1.5.21. CSI Channel_1 FIFO 1 output buffer-B address register

4.1.5.22. CSI Channel_1 FIFO 2 output buffer-A address register

4.1.5.23. CSI Channel_1 FIFO 2 output buffer-B address register

4.1.5.24. CSI Channel_1 output buffer control register

4.1.5.25. CSI Channel_1 status register

4.1.5.26. CSI Channel_1 interrupt enable register

4.1.5.27. CSI Channel_1 interrupt status register

4.1.5.28. CSI Channel_1 horizontal size register

4.1.5.29. CSI Channel_1 vertical size register

4.1.5.30. CSI Channel_1 buffer length register

4.1.5.31. CSI Channel_2 FIFO 0 output buffer-A address register

4.1.5.32. CSI Channel_2 FIFO 0 output buffer-B address register

4.1.5.33. CSI Channel_2 FIFO 1 output buffer-A address register

4.1.5.34. CSI Channel_2 FIFO 1 output buffer-B address register

4.1.5.35. CSI Channel_2 FIFO 2 output buffer-A address register

4.1.5.36. CSI Channel_2 FIFO 2 output buffer-B address register

4.1.5.37. CSI Channel_2 output buffer control register

4.1.5.38. CSI Channel_2 status register

4.1.5.39. CSI Channel_2 interrupt enable register

4.1.5.40. CSI Channel_2 interrupt status register

4.1.5.41. CSI Channel_2 horizontal size register

4.1.5.42. CSI Channel_2 vertical size register

4.1.5.43. CSI Channel_2 buffer length register

4.1.5.44. CSI Channel_3 FIFO 0 output buffer-A address register

4.1.5.45. CSI Channel_3 FIFO 0 output buffer-B address register

4.1.5.46. CSI Channel_3 FIFO 1 output buffer-A address register

4.1.5.47. CSI Channel_3 FIFO 1 output buffer-B address register

4.1.5.48. CSI Channel_3 FIFO 2 output buffer-A address register

4.1.5.49. CSI Channel_3 FIFO 2 output buffer-B address register

4.1.5.50. CSI Channel_3 output buffer control register

4.1.5.51. CSI Channel_3 status register

4.1.5.52. CSI Channel_3 interrupt enable register

4.1.5.53. CSI Channel_3 interrupt status register

4.1.5.54. CSI Channel_3 horizontal size register

4.1.5.55. CSI Channel_3 vertical size register

4.1.5.56. CSI Channel_3 buffer length register

4.2. CSI1

4.2.1. Overview

4.2.2. CSI1 Block Diagram

4.2.3. CSI1 Description

4.2.3.1. CSI data ports

4.2.4. CSI1 Timing Diagram

4.2.5. CSI1 Register List

4.2.6. CSI1 Register Description

4.2.6.1. CSI Enable Register

4.2.6.2. CSI Configuration Register

4.2.6.3. CSI capture control register

4.2.6.4. CSI horizontal scale register

4.2.6.5. CSI Channel_0 FIFO 0 output buffer-A address register

4.2.6.6. CSI Channel_0 FIFO 0 output buffer-B address register

4.2.6.7. CSI Channel_0 FIFO 1 output buffer-A address register

4.2.6.8. CSI Channel_0 FIFO 1 output buffer-B address register

4.2.6.9. CSI Channel_0 FIFO 2 output buffer-A address register

4.2.6.10. CSI Channel_0 FIFO 2 output buffer-B address register

4.2.6.11. CSI Channel_0 output buffer control register

4.2.6.12. CSI Channel_0 status register

4.2.6.13. CSI Channel_0 interrupt enable register

4.2.6.14. CSI Channel_0 interrupt status register

4.2.6.15. CSI Channel_0 horizontal size register

4.2.6.16. CSI Channel_0 vertical size register

4.2.6.17. CSI Channel_0 buffer length register

4.3. TV Decoder

4.3.1. Overview

Chapter 5 Display

5.1. TCON

5.1.1. Overview

5.1.2. TCON Block Diagram

5.1.3. TCON Register List

5.1.4. TCON Register Description

5.1.4.1. TCON global control register

5.1.4.2. TCON global interrupt register0

5.1.4.3. TCON global interrupt register1

5.1.4.4. TCON FRM control register

5.1.4.5. TCON0 data clock register

5.1.4.6. TCON0 basic timing register0

5.1.4.7. TCON0 basic timing register1

5.1.4.8. TCON0 basic timing register2

5.1.4.9. TCON0 basic timing register3

5.1.4.10. TCON0 hv panel interface register

5.1.4.11. TCON0 cpu panel interface register

5.1.4.12. TCON0 cpu panel write data register

5.1.4.13. TCON0 cpu panel read data register0

5.1.4.14. TCON0 cpu panel read data register1

5.1.4.15. TCON0 ttl panel timing register 0

5.1.4.16. TCON0 tttl panel timing register 1

5.1.4.17. TCON0 ttl panel timing register 2

5.1.4.18. TCON0 ttl panel timing register3

5.1.4.19. TCON0 ttl panel timing register3

5.1.4.20. TCON0 lvds panel interface register

5.1.4.21. TCON0 IO polarity register

5.1.4.22. TCON0 IO control register

5.1.4.23. TCON1 control register

5.1.4.24. TCON1 basic timing register0

5.1.4.25. TCON1 basic timing register1

5.1.4.26. TCON1 basic timing register2

5.1.4.27. TCON1 basic timing register3

5.1.4.28. TCON1 basic timing register4

5.1.4.29. TCON1 basic timing register5

5.1.4.30. TCON1 IO polarity register

5.1.4.31. TCON1 IO control register

5.1.4.32. TCON CEU control register

5.1.4.33. TCON CEU coefficent register

5.1.4.34. TCON1 fill data control register

5.1.4.35. TCON1 fill data begin register

5.1.4.36. TCON1 fill data end register

5.1.4.37. TCON1 fill data value register

5.1.4.38. TCON1 fill data begin register

5.1.4.39. TCON1 fill data end register

5.1.4.40. TCON1 fill data value register

5.1.4.41. TCON1 fill data begin register

5.1.4.42. TCON1 fill data end register

5.1.4.43. TCON1 fill data value register

5.2. HDMI

5.2.1. Overview

5.2.2. HDMI Block Diagram

5.2.3. HDMI Control Register Description

5.2.4. HDMI Register Description

5.2.4.1. HDMI Version ID

5.2.4.2. System Control Register

5.2.4.3. Interrupt Status Register

5.2.4.4. HDMI Hot Plug Register

5.2.4.5. Video Control Register

5.2.4.6. Video Timing Register0

5.2.4.7. Video Timing Register1

5.2.4.8. Video Timing Register2

5.2.4.9. Video Timing Register3

5.2.4.10. Video Timing Register4

5.2.4.11. Audio Control Register:

5.2.4.12. Audio DMA&FIFO control Register:

5.2.4.13. Audio Format Control Register

5.2.4.14. Audio PCM Control Register

5.2.4.15. Audio CTS register

5.2.4.16. Audio N register

5.2.4.17. Audio PCM channel Status 0

5.2.4.18. Audio PCM channel Status 1

5.2.4.19. AVI_INFO_FRMAE_PACKET

5.2.4.20. AUDIO_INFO_FRMAE_PACKET

5.2.4.21. ACP_PACKET

5.2.4.22. General_Control_PACKET

5.2.4.23. SPD_PACKET

5.2.4.24. PLL/DRV Setting 0: Pad Ctrl0

5.2.4.25. PLL/DRV Setting 1: Pad Ctrl1

5.2.4.26. PLL/DRV Setting 2: PLL Ctrl0

5.2.4.27. PLL/DRV Setting 3: PLL Dbg0

5.2.4.28. PLL/DRV Setting 4: PLL Dbg0

5.2.4.29. PLL/DRV Setting 5: HPD/CEC

5.2.4.30. PACKET_CONTROL0

5.2.4.31. PACKET CONTROL1

5.2.4.32. Audio Normal DMA Port

5.2.4.33. DDC Control Register

5.2.4.34. DDC Slave Address Register

5.2.4.35. DDC Interrupt Mask Register

5.2.4.36. DDC Interrupt Status Register:

5.2.4.37. DDC FIFO Control Register

5.2.4.38. DDC FIFO Status Register

5.2.4.39. DDC FIFO Access Register

5.2.4.40. DDC Access Data Byte Number

5.2.4.41. DDC Access Command Register

5.2.4.42. DDC Extended Register

5.2.4.43. DDC Clock Register

5.3. Display Engine Frontend

5.3.1. Overview

5.3.2. DEFE Block Diagram

5.3.3. DEFE Register List

5.3.4. DEFE Register Description

5.3.4.1. DEFE_EN_REG

5.3.4.2. DEFE_FRM_CTRL_REG

5.3.4.3. DEFE_BYPASS_REG

5.3.4.4. DEFE_AGTH_SEL_REG

5.3.4.5. DEFE_LINT_CTRL_REG

5.3.4.6. DEFE_BUF_ADDR0_REG

5.3.4.7. DEFE_BUF_ADDR1_REG

5.3.4.8. DEFE_BUF_ADDR2_REG

5.3.4.9. DEFE_FIELD_CTRL_REG

5.3.4.10. DEFE_TB_OFF0_REG

5.3.4.11. DEFE_TB_OFF1_REG

5.3.4.12. DEFE_TB_OFF2_REG

5.3.4.13. DEFE_LINESTRD0_REG

5.3.4.14. DEFE_LINESTRD1_REG

5.3.4.15. DEFE_LINESTRD2_REG

5.3.4.16. DEFE_INPUT_FMT_REG

5.3.4.17. DEFE_WB_ADDR0_REG

5.3.4.18. DEFE_WB_ADDR1_REG

5.3.4.19. DEFE_WB_ADDR2_REG

5.3.4.20. DEFE_OUTPUT_FMT_REG

5.3.4.21. DEFE_INT_EN_REG

5.3.4.22. DEFE_INT_STATUS_REG

5.3.4.23. DEFE_STATUS_REG

5.3.4.24. DEFE_CSC_COEF00_REG

5.3.4.25. DEFE_CSC_COEF01_REG

5.3.4.26. DEFE_CSC_COEF02_REG

5.3.4.27. DEFE_CSC_COEF03_REG

5.3.4.28. DEFE_CSC_COEF10_REG

5.3.4.29. DEFE_CSC_COEF11_REG

5.3.4.30. DEFE_CSC_COEF12_REG

5.3.4.31. DEFE_CSC_COEF13_REG

5.3.4.32. DEFE_CSC_COEF20_REG

5.3.4.33. DEFE_CSC_COEF21_REG

5.3.4.34. DEFE_CSC_COEF22_REG

5.3.4.35. DEFE_CSC_COEF23_REG

5.3.4.36. DEFE_DI_CTRL_REG

5.3.4.37. DEFE_DI_DIAGINTP_REG

5.3.4.38. DEFE_DI_TEMPDIFF_REG

5.3.4.39. DEFE_DI_SAWTOOTH_REG

5.3.4.40. DEFE_DI_SPATCOMP_REG

5.3.4.41. DEFE_DI_BURSTLEN_REG

5.3.4.42. DEFE_DI_PRELUMA_REG

5.3.4.43. DEFE_DI_TILEFLAG_REG

5.3.4.44. DEFE_DI_FLAGLINESTRD_REG

5.3.4.45. DEFE_WB_LINESTRD_EN_REG

5.3.4.46. DEFE_WB_LINESTRD0_REG

5.3.4.47. DEFE_WB_LINESTRD1_REG

5.3.4.48. DEFE_WB_LINESTRD2_REG

5.3.4.49. DEFE_3D_CTRL_REG

5.3.4.50. DEFE_3D_BUF_ADDR0_REG

5.3.4.51. DEFE_3D_BUF_ADDR1_REG

5.3.4.52. DEFE_3D_BUF_ADDR2_REG

5.3.4.53. DEFE_3D_TB_OFF0_REG

5.3.4.54. DEFE_3D_TB_OFF1_REG

5.3.4.55. DEFE_3D_TB_OFF2_REG

5.3.4.56. DEFE_CH0_INSIZE_REG

5.3.4.57. DEFE_CH0_OUTSIZE_REG

5.3.4.58. DEFE_CH0_HORZFACT_REG

5.3.4.59. DEFE_CH0_VERTFACT_REG

5.3.4.60. DEFE_CH0_HORZPHASE_REG

5.3.4.61. DEFE_CH0_VERTPHASE0_REG

5.3.4.62. DEFE_CH0_VERTPHASE1_REG

5.3.4.63. DEFE_CH0_HORZTAP0_REG

5.3.4.64. DEFE_CH0_HORZTAP1_REG

5.3.4.65. DEFE_CH0_VERTTAP_REG

5.3.4.66. DEFE_CH1_INSIZE_REG

5.3.4.67. DEFE_CH1_OUTSIZE_REG

5.3.4.68. DEFE_CH1_HORZFACT_REG

5.3.4.69. DEFE_CH1_VERTFACT_REG

5.3.4.70. DEFE_CH1_HORZPHASE_REG

5.3.4.71. DEFE_CH1_VERTPHASE0_REG

5.3.4.72. DEFE_CH1_VERTPHASE1_REG

5.3.4.73. DEFE_CH1_HORZTAP0_REG

5.3.4.74. DEFE_CH1_HORZTAP1_REG

5.3.4.75. DEFE_CH1_VERTTAP_REG

5.3.4.76. DEFE_CH0_HORZCOEF0_REGN (N=0 :31)

5.3.4.77. DEFE_CH0_HORZCOEF1_REGN (N=0 :31)

5.3.4.78. DEFE_CH0_VERTCOEF_REGN (N=0 :31)

5.3.4.79. DEFE_CH1_HORZCOEF0_REGN (N=0 :31)

5.3.4.80. DEFE_CH1_HORZCOEF1_REGN (N=0 :31)

5.3.4.81. DEFE_CH1_VERTCOEF_REGN (N=0 :31)

5.3.4.82. DEFE_VPP_EN_REG

5.3.4.83. DEFE_VPP_DCTI_REG

5.3.4.84. DEFE_VPP_LP1_REG

5.3.4.85. DEFE_VPP_LP2_REG

5.3.4.86. DEFE_VPP_WLE_REG

5.3.4.87. DEFE_VPP_BLE_REG

5.4. Display Engine Backend

5.4.1. Overview

5.4.2. Display Engine Block Diagram

5.4.3. DEBE Register list

5.4.4. DEBE Register Description

5.4.4.1. DE back-end mode control register

5.4.4.2. DE-back color control register

5.4.4.3. DE-back display size setting register

5.4.4.4. DE-layer size register

5.4.4.5. DE-layer coordinate control register

5.4.4.6. DE-layer frame buffer line width register

5.4.4.7. DE-layer frame buffer low 32 bit address register

5.4.4.8. DE-layer frame buffer high 4 bit address register

5.4.4.9. DE-Register buffer control register

5.4.4.10. DE-color key MAX register

5.4.4.11. DE-color key MIN register

5.4.4.12. DE-color key configuration register

5.4.4.13. DE-layer attribute control register1

5.4.4.14. Pixels sequence table

5.4.4.15. DE-HWC coordinate control register

5.4.4.16. DE-HWC frame buffer format register

5.4.4.17. DE backend write back control register

5.4.4.18. DE backend write back address register

5.4.4.19. DE backend write back buffer line width register

5.4.4.20. DE-sprite enable register

5.4.4.21. DE-sprite format control register

5.4.4.22. Pixels sequence description:

5.4.4.23. DE-sprite single block coordinate control register

5.4.4.24. DE-sprite single block attribute control register

5.4.4.25. DE-sprite single block address setting SRAM array

5.4.4.26. DE backend input YUV channel control register

5.4.4.27. Source data input data ports

5.4.4.28. DE backend YUV channel frame buffer address register

5.4.4.29. DE backend YUV channel buffer line width register

5.4.4.30. DE backend Y/G coefficient register

5.4.4.31. DE backend Y/G constant register

5.4.4.32. DE backend U/R coefficient register

5.4.4.33. DE backend U/R constant register

5.4.4.34. DE backend V/B coefficient register

5.4.4.35. DE backend V/B constant register

5.4.4.36. DE backend keystone correction control register

5.4.4.37. DE backend keystone back color control register

5.4.4.38. DE backend keystone output first line width setting register

5.4.4.39. DE backend keystone vertical scaling factor register

5.4.4.40. DE backend keystone horizontal filtering coefficient RAM block

5.4.4.41. DE backend output color control register

5.4.4.42. Color correction conversion algorithm formula:

5.4.4.43. DE backend output color R coefficient register

5.4.4.44. DE backend output color R constant register

5.4.4.45. DE backend output color G coefficient register

5.4.4.46. DE backend output color G constant register

5.4.4.47. DE backend output color B coefficient register

5.4.4.48. DE backend output color B constant register

5.4.4.49. DE-HWC pattern memory block

5.4.4.50. DE-HWC palette table

5.4.4.51. Sprite palette table

5.4.4.52. Palette mode

5.4.4.53. Internal frame buffer mode

5.4.4.54. Internal frame buffer mode palette table

5.4.4.55. Gamma correction mode

5.4.4.56. Display engine memory mapping

5.5. TV Encoder

5.5.1. Overview

Chapter 6 Interface

6.1. SD3.0

6.1.1. Overview

6.1.2. SD3.0 Timing Diagram

6.2. TWI

6.2.1. Overview

6.2.2. TWI Controller Timing Diagram

6.2.3. TWI Controller Register List

6.2.4. TWI Register Description

6.2.4.1. TWI Slave Address Register

6.2.4.2. TWI Extend Address Register

6.2.4.3. TWI Data Register

6.2.4.4. TWI Control Register

6.2.4.5. TWI Status Register

6.2.4.6. TWI Clock Register

6.2.4.7. TWI Enhance Feature Register

6.2.4.8. TWI Line Control Register

6.2.4.9. TWI DVFS Control Register

6.2.5. TWI Controller Special Requirement

6.2.5.1. TWI Pin List

6.2.5.2. TWI Controller Operation

6.3. SPI

6.3.1. Overview

6.3.2. SPI Timing Diagram

6.3.3. SPI Register List

6.3.4. SPI Register Description

6.3.4.1. SPI RX Data Register

6.3.4.2. SPI TX Data Register

6.3.4.3. SPI Control Register

6.3.4.4. SPI Interrupt Control Register

6.3.4.5. SPI Interrupt Status Register

6.3.4.6. SPI DMA Control Register

6.3.4.7. SPI Wait Clock Register

6.3.4.8. SPI Clock Control Register

6.3.4.9. SPI Burst Counter Register

6.3.4.10. SPI Transmit Counter Register

6.3.4.11. SPI FIFO Status Register

6.3.5. SPI Special Requirement

6.3.5.1. SPI Pin List

6.3.5.2. SPI Module Clock Source and Frequency

6.4. UART

6.4.1. Overview

6.4.2. UART Timing Diagram

6.4.3. UART Register List

6.4.4. UART Register Description

6.4.4.1. UART Receiver Buffer Register

6.4.4.2. UART Transmit Holding Register

6.4.4.3. UART Divisor Latch Low Register

6.4.4.4. UART Divisor Latch High Register

6.4.4.5. UART Interrupt Enable Register

6.4.4.6. UART Interrupt Identity Register

6.4.4.7. UART FIFO Control Register

6.4.4.8. UART Line Control Register

6.4.4.9. UART Modem Control Register

6.4.4.10. UART Line Status Register

6.4.4.11. UART Modem Status Register

6.4.4.12. UART Scratch Register

6.4.4.13. UART Status Register

6.4.4.14. UART Transmit FIFO Level Register

6.4.4.15. UART Receive FIFO Level Register

6.4.4.16. UART Halt TX Register

6.4.5. UART Special Requirement

6.4.5.1. UART Pin List

6.5. PS2

6.5.1. Overview

6.5.2. PS2 Block Diagram

6.5.3. PS2 Timing Diagram

6.5.4. PS2 Register List

6.5.5. PS2 Register Description

6.5.5.1. PS2 Global Control Register

6.5.5.2. PS2 Data Register

6.5.5.3. PS2 Line Control Register

6.5.5.4. PS2 Line Status Register

6.5.5.5. PS2 FIFO Control Register

6.5.5.6. PS2 FIFO Status Register

6.5.5.7. PS2 Clock Divider Register

6.5.6. PS2 Special Requirements

6.5.6.1. PS2 Interface Pin list

6.5.6.2. PS2 Clock Requirement

6.6. IR

6.6.1. Overview

6.6.2. IR Block Diagram

6.6.3. IR Register List

6.6.4. IR Register Description

6.6.4.1. IR Control Register

6.6.4.2. IR Transmitter Configure Register

6.6.4.3. IR Transmitter Address Register

6.6.4.4. IR Transmitter Counter Register

6.6.4.5. IR Receiver Configure Register

6.6.4.6. IR Receiver Address Register

6.6.4.7. IR Receiver Counter Register

6.6.4.8. IR Transmitter FIFO Register

6.6.4.9. IR Receiver FIFO Register

6.6.4.10. IR Transmitter Interrupt Control Register

6.6.4.11. IR Transmitter Status Register

6.6.4.12. IR Receiver Interrupt Control Register

6.6.4.13. IR Receiver Status Register

6.6.4.14. CIR Configure Register

6.7. USB OTG

6.7.1. Overview

6.7.2. USB OTG Timing Diagram

6.8. USB Host

6.8.1. Overview

6.8.2. USB Host Block Diagram

6.8.3. USB Host Timing Diagram

6.8.4. USB Host Register List

6.8.5. EHCI Register Description

6.8.5.1. EHCI Identification Register

6.8.5.2. EHCI Host Interface Version Number Register

6.8.5.3. EHCI Host Control Structural Parameter Register

6.8.5.4. EHCI Host Control Capability Parameter Register

6.8.5.5. EHCI Companion Port Route Description

6.8.5.6. EHCI USB Command Register

6.8.5.7. EHCI USB Status Register

6.8.5.8. EHCI USB Interrupt Enable Register

6.8.5.9. EHCI Frame Index Register

6.8.5.10. EHCI Periodic Frame List Base Address Register

6.8.5.11. EHCI Current Asynchronous List Address Register

6.8.5.12. EHCI Configure Flag Register

6.8.5.13. EHCI Port Status and Control Register

6.8.6. OHCI Register List

6.8.7. OHCI Register Description

6.8.7.1. HcRevision Register

6.8.7.2. HcControl Register

6.8.7.3. HcCommandStatus Register

6.8.7.4. HcInterruptStatus Register

6.8.7.5. HcInterruptEnable Register

6.8.7.6. HcInterruptDisable Register

6.8.7.7. HcHCCA Register

6.8.7.8. HcPeriodCurrentED Register

6.8.7.9. HcControlHeadED Register

6.8.7.10. HcControlCurrentED Register

6.8.7.11. HcBulkHeadED Register

6.8.7.12. HcBulkCurrentED Register

6.8.7.13. HcDoneHead Register

6.8.7.14. HcFmInterval Register

6.8.7.15. HcFmRemaining Register

6.8.7.16. HcFmNumber Register

6.8.7.17. HcPeriodicStart Register

6.8.7.18. HcLSThreshold Register

6.8.7.19. HcRhDescriptorA Register

6.8.7.20. HcRhDescriptorB Register

6.8.7.21. HcRhStatus Register

6.8.7.22. HcRhPortStatus Register

6.8.8. USB Host Special Requirement

6.8.8.1. USB Host Clock Requirment

6.9. Digital Audio Interface

6.9.1. Overview

6.9.2. Digital Audio Interface Block Diagram

6.9.3. Digital Audio Interface Timing Diagram

6.9.4. Digital Audio Interface Register List

6.9.5. Digital Audio Interface Register Description

6.9.5.1. Digital Audio Control Register

6.9.5.2. Digital Audio Format Register 0

6.9.5.3. Digital Audio Format Register 1

6.9.5.4. Digital Audio TX FIFO register

6.9.5.5. Digital Audio RX FIFO register

6.9.5.6. Digital Audio FIFO Control Register

6.9.5.7. Digital Audio FIFO Status Register

6.9.5.8. Digital Audio DMA & Interrupt Control Register

6.9.5.9. Digital Audio Interrupt Status Register

6.9.5.10. Digital Audio Clock Divide Register

6.9.5.11. Digital Audio TX Counter register

6.9.5.12. Digital Audio RX Counter register

6.9.5.13. Digital Audio TX Channel Select register

6.9.5.14. Digital Audio TX Channel Mapping Register

6.9.5.15. Digital Audio RX Channel Select register

6.9.5.16. Digital Audio RX Channel Mapping Register

6.9.6. Digital Audio Interface Special Requirement

6.9.6.1. Digital Audio Interface Pin List

6.9.6.2. Digital Audio Interface MCLK and BCLK

6.10. AC97 Interface

6.10.1. Overview

6.10.2. AC97 Block diagram

6.10.3. AC97 Interface Clock Tree

6.10.4. AC Link Frame Format

6.10.5. AC97 Interface Timing Diagram

6.10.5.1. Cold Reset timing diagram

6.10.5.2. Warm Reset timing diagram

6.10.5.3. Power Down timing diagram

6.10.5.4. AC-link Clock

6.10.5.5. Data transmission timing diagram

6.10.6. AC97 Interface Register List

6.10.7. AC97 Interface Register Description

6.10.7.1. AC97 Control Register

6.10.7.2. AC97 Format Register

6.10.7.3. AC97 Codec Command Register

6.10.7.4. AC97 Codec Status Register

6.10.7.5. AC97 TX FIFO Register

6.10.7.6. AC97 RX FIFO Register

6.10.7.7. AC97 FIFO Control Register

6.10.7.8. AC97 FIFO Status Register

6.10.7.9. AC97 Interrupt Control Register

6.10.7.10. AC97 Interrupt status Register

6.10.7.11. AC97 TX Counter register

6.10.7.12. AC97 RX Counter register

6.10.8. AC97 Interface Special Requirement

6.10.8.1. Pin list

6.10.8.2. AC97 Clock Requirement

6.11. EMAC

6.11.1. Overview

6.11.2. EMAC Block Diagram

6.11.3. EMAC Operation Diagram

6.11.3.1. TX Operation

6.11.3.2. RX Operation

6.12. GMAC

6.12.1. Overview

6.12.2. GMAC Block Diagram

6.13. Transport Stream

6.13.1. Overview

6.13.2. Transport Stream Block Diagram

6.13.3. Transport Stream Controller Register List

6.13.4. Transport Stream Register Description

6.13.4.1. TSC Control Register

6.13.4.2. TSC Status Register

6.13.4.3. TSC Port Control Register

6.13.4.4. TSC Port Parameter Register

6.13.4.5. TSC TSF Input Multiplex Control Register

6.13.4.6. TSC Port Output Multiplex Control Register

6.13.4.7. TSG Control and Status Register

6.13.4.8. TSG Packet Parameter Register

6.13.4.9. TSG Interrupt Enable and Status Register

6.13.4.10. TSG Clock Control Register

6.13.4.11. TSG Buffer Base Address Register

6.13.4.12. TSG Buffer Size Register

6.13.4.13. TSG Buffer Pointer Register

6.13.4.14. TSF Control and Status Register

6.13.4.15. TSF Packet Parameter Register

6.13.4.16. TSF Interrupt Enable and Status Register

6.13.4.17. TSF DMA Interrupt Enable Register

6.13.4.18. TSF Overlap Interrupt Enable Register

6.13.4.19. TSF DMA Interrupt Status Register

6.13.4.20. TSF Overlap Interrupt Status Register

6.13.4.21. TSF PCR Control Register

6.13.4.22. TSF PCR Data Register

6.13.4.23. TSF Channel Enable Register

6.13.4.24. TSF Channel PES Enable Register

6.13.4.25. TSF Channel Descramble Enable Register

6.13.4.26. TSF Channel Index Register

6.13.4.27. TSF Channel Control Register

6.13.4.28. TSF Channel Status Register

6.13.4.29. TSF Channel CW Index Register

6.13.4.30. TSF Channel PID Register

6.13.4.31. TSF Channel Buffer Base Address Register

6.13.4.32. TSF Channel Buffer Size Register

6.13.4.33. TSF Channel Buffer Write Pointer Register

6.13.4.34. TSF Channel Buffer Read Pointer Register

6.13.4.35. TSD Control Register

6.13.4.36. TSD Status Register

6.13.4.37. TSD Control Word Index Register

6.13.4.38. TSD Control Word Register

6.13.5. Transport Stream Clock Requirement

6.14. Smart Card Reader

6.14.1. Overview

6.14.2. Smart Card Reader Block Diagram

6.14.3. Smart Card Reader Timing Diagram

6.14.4. Smart Card Reader Register List

6.14.5. Smart Card Reader Register Description

6.14.5.1. Smart Card Reader Control and Status Register

6.14.5.2. Smart Card Reader Interrupt Enable Register

6.14.5.3. Smart Card Reader Interrupt Status Register

6.14.5.4. Smart Card Reader FIFO Control and Status Register

6.14.5.5. Smart Card Reader FIFO Count Register

6.14.5.6. Smart Card Reader Repeat Control Register

6.14.5.7. Smart Card Reader Clock Divisor Register

6.14.5.8. Smart Card Reader Line Time Register

6.14.5.9. Smart Card Reader Character Time Register

6.14.5.10. Smart Card Reader Line Control Register

6.14.5.11. Smart Card Reader FIFO Data Register

6.14.7. SCIO Pad Configuration

6.15. SATA Host

6.15.1. Overview

6.15.2. SATA_AHCI Timing Diagram

6.16. CAN

6.16.1. Overview

6.16.2. CAN System Block Diagram

6.16.3. CAN Bit Time Configuration

6.17. Keypad

6.17.1. Overview

6.17.2. Keypad Interface Register List

6.17.3. Keypad Interface Register Description

6.17.3.1. Keypad Control Register

6.17.3.2. Keypad Timing Register

6.17.3.3. Keypad Interrupt Configure Register

6.17.3.4. Keypad Interrupt Status Register

6.17.3.5. Keypad Input Data Register 0

6.17.3.6. Keypad Input Data Register 1

6.17.4. Keypad Interface Special Requirement

6.17.4.1. Keypad Interface Pin List

Appendix A

未标题

Declaration THIS A20 USER MANUAL IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY (“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER. THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF ALLWINNER. THIS DOCUMENTATION NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS FOR ANY PARTICULAR APPLICATION. THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE. A20 User Manual (Revision 1.1) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 2 / 806 CONFIDENTIAL

Revision Date 1.0 1.1 March 22, 2013 Revision History Description Initial version Septermber 17, 2013 Modify TVD and TVE description A20 User Manual (Revision 1.1) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 3 / 806 CONFIDENTIAL

Table of Contents 1.5. 1.6. 1.7. 1.8. 1.9. 1.1. 1.2. 1.3. 1.4. Declaration .................................................................................................................................................... 2 Revision History............................................................................................................................................. 3 Table of Contents........................................................................................................................................... 4 System ..................................................................................................................................... 9 Chapter 1 Overview ................................................................................................................................ 10 A20 Block Diagram ................................................................................................................ 17 Memory Mapping ................................................................................................................... 18 CPU Configuration ................................................................................................................. 22 1.4.1. Overview ........................................................................................................................ 22 1.4.2. CPU Configuration Register List .................................................................................... 23 1.4.3. CPUCFG Register Description ...................................................................................... 24 CCU ....................................................................................................................................... 33 1.5.1. Overview ........................................................................................................................ 33 1.5.2. Clock Tree Diagram ....................................................................................................... 34 1.5.3. CCU Register List........................................................................................................... 34 1.5.4. CCU Register Description .............................................................................................. 37 System Boot .......................................................................................................................... 94 1.6.1. Overview ........................................................................................................................ 94 1.6.2. System Boot Diagram .................................................................................................... 95 System Control ...................................................................................................................... 96 1.7.1. Overview ........................................................................................................................ 96 1.7.2. System Control Register List ......................................................................................... 97 1.7.3. System Control Register ................................................................................................ 97 PWM .................................................................................................................................... 101 1.8.1. Overview ...................................................................................................................... 101 1.8.2. PWM Register List........................................................................................................ 102 1.8.3. PWM Register Description ........................................................................................... 102 Timer .................................................................................................................................... 107 1.9.1. Overview ...................................................................................................................... 107 Timer Register List ....................................................................................................... 108 1.9.2. Timer Register Description ........................................................................................... 109 1.9.3. High Speed Timer ................................................................................................................ 133 Overview ............................................................................................................... 133 High Speed Timer Register List ............................................................................ 134 High Speed Timer Controller Register .................................................................. 135 1.11. GIC ...................................................................................................................................... 146 Interrupt Source ............................................................................................................ 146 DMA ..................................................................................................................................... 151 Overview ............................................................................................................... 151 DMA Register List ................................................................................................. 152 DMA Controller Register Description .................................................................... 153 Audio Codec ........................................................................................................................ 170 Overview ............................................................................................................... 170 Audio Codec Block Diagram ................................................................................. 171 Audio Codec Register List .................................................................................... 171 Audio Codec Register Description ........................................................................ 172 LRADC ................................................................................................................................. 189 1.13.1. 1.13.2. 1.13.3. 1.13.4. 1.10.1. 1.10.2. 1.10.3. 1.11.1. 1.12.1. 1.12.2. 1.12.3. 1.10. 1.12. 1.13. 1.14. A20 User Manual (Revision 1.1) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 4 / 806 CONFIDENTIAL

1.15. 1.16. 1.17. 1.18. 1.16.1. 1.16.2. 1.16.3. 1.16.4. 1.17.1. 1.17.2. 1.17.3. 1.14.1. 1.14.2. 1.14.3. 1.14.4. 1.18.1. 1.18.2. 1.18.3. 1.18.4. 1.15.1. 1.15.2. 1.15.3. 1.15.4. 1.15.5. 1.15.6. 1.15.7. Overview ............................................................................................................... 189 LRADC Block Diagram ......................................................................................... 190 LRADC Register List ............................................................................................. 190 LRADC Register Description ................................................................................ 191 TP ........................................................................................................................................ 198 Overview ............................................................................................................... 198 Typical Application Circuit ..................................................................................... 199 TP Clock Tree ....................................................................................................... 199 A/D Conversion Time ............................................................................................ 199 Principle of Operation ........................................................................................... 201 TP Register List..................................................................................................... 206 TP Register Description ........................................................................................ 207 Security System ................................................................................................................... 217 Overview ............................................................................................................... 217 Security System Block Diagram ........................................................................... 218 Security System Register List ............................................................................... 218 Security System Register Description .................................................................. 219 Security JTAG ..................................................................................................................... 227 Overview ............................................................................................................... 227 Security JTAG Register List .................................................................................. 228 Security JTAG Register Description ..................................................................... 228 Security ID ........................................................................................................................... 230 Overview ............................................................................................................... 230 SID Block Diagram ................................................................................................ 231 Security System Register List ............................................................................... 231 Security ID Register Description ........................................................................... 232 Port Controller ..................................................................................................................... 238 Port Description .................................................................................................... 238 Port Configuration Table ....................................................................................... 239 Port Register List .................................................................................................. 245 Port Register Description ...................................................................................... 246 Chapter 2 Memory ................................................................................................................................ 305 DRAM .................................................................................................................................. 306 2.1.1. Overview ...................................................................................................................... 306 NAND Flash ......................................................................................................................... 307 2.2.1. Overview ...................................................................................................................... 307 2.2.2. Nand Flash Block Diagram .......................................................................................... 308 2.2.3. NFC Timing Diagram .................................................................................................... 309 2.2.4. NFC Operation Guide .................................................................................................. 314 Chapter 3 Graphic ................................................................................................................................ 317 Mixer Processor ................................................................................................................... 318 3.1.1. Overview ...................................................................................................................... 318 3.1.2. Mixer Processor Block Diagram ................................................................................... 319 3.1.3. MP Register List ........................................................................................................... 319 3.1.4. MP Register Description .............................................................................................. 321 Image ................................................................................................................................... 361 CSI0 ..................................................................................................................................... 362 4.1.1. Overview ...................................................................................................................... 362 4.1.2. CSI0 Block Diagram ..................................................................................................... 363 4.1.3. CSI0 Description .......................................................................................................... 363 4.1.4. CSI0 Register List ........................................................................................................ 366 4.1.5. CSI0 Register Description ............................................................................................ 368 CSI1 ..................................................................................................................................... 396 4.2.1. Overview ...................................................................................................................... 396 1.19.1. 1.19.2. 1.19.3. 1.19.4. 2.1. 2.2. 3.1. 1.19. Chapter 4 4.1. 4.2. A20 User Manual (Revision 1.1) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 5 / 806 CONFIDENTIAL

5.2. 5.3. 4.3. 5.1. 5.4. 4.2.2. CSI1 Block Diagram ..................................................................................................... 397 4.2.3. CSI1 Description .......................................................................................................... 397 4.2.4. CSI1 Timing Diagram ................................................................................................... 397 4.2.5. CSI1 Register List ........................................................................................................ 398 4.2.6. CSI1 Register Description ............................................................................................ 399 TV Decoder.......................................................................................................................... 411 4.3.1. Overview ...................................................................................................................... 411 Chapter 5 Display ................................................................................................................................. 412 TCON ................................................................................................................................... 414 5.1.1. Overview ...................................................................................................................... 414 5.1.2. TCON Block Diagram ................................................................................................... 415 TCON Register List ...................................................................................................... 416 5.1.3. TCON Register Description.......................................................................................... 418 5.1.4. HDMI .................................................................................................................................... 444 5.2.1. Overview ...................................................................................................................... 444 5.2.2. HDMI Block Diagram .................................................................................................... 445 5.2.3. HDMI Control Register Description .............................................................................. 445 5.2.4. HDMI Register Description........................................................................................... 447 Display Engine Frontend ..................................................................................................... 485 5.3.1. Overview ...................................................................................................................... 485 5.3.2. DEFE Block Diagram ................................................................................................... 486 5.3.3. DEFE Register List ....................................................................................................... 486 5.3.4. DEFE Register Description .......................................................................................... 490 Display Engine Backend ..................................................................................................... 536 5.4.1. Overview ...................................................................................................................... 536 5.4.2. Display Engine Block Diagram ..................................................................................... 537 5.4.3. DEBE Register list ........................................................................................................ 537 5.4.4. DEBE Register Description .......................................................................................... 540 TV Encoder .......................................................................................................................... 582 5.5.1. Overview ...................................................................................................................... 582 Interface ............................................................................................................................... 583 SD3.0 ................................................................................................................................... 584 6.1.1. Overview ...................................................................................................................... 584 6.1.2. SD3.0 Timing Diagram ................................................................................................. 584 TWI ...................................................................................................................................... 585 6.2.1. Overview ...................................................................................................................... 585 TWI Controller Timing Diagram .................................................................................... 586 6.2.2. TWI Controller Register List ......................................................................................... 586 6.2.3. TWI Register Description ............................................................................................. 587 6.2.4. 6.2.5. TWI Controller Special Requirement............................................................................ 595 SPI ....................................................................................................................................... 597 6.3.1. Overview ...................................................................................................................... 597 6.3.2. SPI Timing Diagram ..................................................................................................... 598 6.3.3. SPI Register List........................................................................................................... 599 6.3.4. SPI Register Description .............................................................................................. 600 6.3.5. SPI Special Requirement ............................................................................................. 614 UART ................................................................................................................................... 615 6.4.1. Overview ...................................................................................................................... 615 6.4.2. UART Timing Diagram ................................................................................................. 616 6.4.3. UART Register List ....................................................................................................... 616 6.4.4. UART Register Description .......................................................................................... 617 6.4.5. UART Special Requirement ......................................................................................... 635 PS2 ...................................................................................................................................... 638 6.5.1. Overview ...................................................................................................................... 638 Chapter 6 6.3. 5.5. 6.1. 6.2. 6.4. 6.5. A20 User Manual (Revision 1.1) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 6 / 806 CONFIDENTIAL

6.9. 6.6. 6.7. 6.8. 6.5.2. PS2 Block Diagram ...................................................................................................... 639 6.5.3. PS2 Timing Diagram .................................................................................................... 639 6.5.4. PS2 Register List.......................................................................................................... 641 6.5.5. PS2 Register Description ............................................................................................. 641 6.5.6. PS2 Special Requirements .......................................................................................... 649 IR ......................................................................................................................................... 650 6.6.1. Overview ...................................................................................................................... 650 IR Block Diagram ......................................................................................................... 651 6.6.2. IR Register List ............................................................................................................. 651 6.6.3. IR Register Description ................................................................................................ 652 6.6.4. USB OTG ............................................................................................................................. 665 6.7.1. Overview ...................................................................................................................... 665 6.7.2. USB OTG Timing Diagram ........................................................................................... 665 USB Host ............................................................................................................................. 666 6.8.1. Overview ...................................................................................................................... 666 6.8.2. USB Host Block Diagram ............................................................................................. 667 6.8.3. USB Host Timing Diagram ........................................................................................... 667 6.8.4. USB Host Register List ................................................................................................ 667 6.8.5. EHCI Register Description ........................................................................................... 668 6.8.6. OHCI Register List ....................................................................................................... 687 6.8.7. OHCI Register Description ........................................................................................... 688 6.8.8. USB Host Special Requirement ................................................................................... 705 Digital Audio Interface ......................................................................................................... 706 6.9.1. Overview ...................................................................................................................... 706 6.9.2. Digital Audio Interface Block Diagram .......................................................................... 707 6.9.3. Digital Audio Interface Timing Diagram ........................................................................ 707 6.9.4. Digital Audio Interface Register List ............................................................................. 709 6.9.5. Digital Audio Interface Register Description ................................................................ 709 6.9.6. Digital Audio Interface Special Requirement ................................................................ 726 AC97 Interface ..................................................................................................................... 729 Overview ............................................................................................................... 729 AC97 Block diagram ............................................................................................. 730 AC97 Interface Clock Tree .................................................................................... 731 AC Link Frame Format.......................................................................................... 731 AC97 Interface Timing Diagram ............................................................................ 732 AC97 Interface Register List ................................................................................. 736 AC97 Interface Register Description .................................................................... 737 AC97 Interface Special Requirement ................................................................... 747 EMAC .................................................................................................................................. 748 6.11.1. Overview ...................................................................................................................... 748 6.11.2. EMAC Block Diagram .................................................................................................. 749 6.11.3. EMAC Operation Diagram ........................................................................................... 750 6.12. GMAC .................................................................................................................................. 753 Overview ............................................................................................................... 753 GMAC Block Diagram ........................................................................................... 754 Transport Stream ................................................................................................................. 755 Overview ............................................................................................................... 755 Transport Stream Block Diagram .......................................................................... 756 Transport Stream Controller Register List ............................................................ 756 Transport Stream Register Description................................................................. 758 Transport Stream Clock Requirement .................................................................. 777 Smart Card Reader ............................................................................................................. 778 Overview ............................................................................................................... 778 Smart Card Reader Block Diagram ...................................................................... 779 6.10.1. 6.10.2. 6.10.3. 6.10.4. 6.10.5. 6.10.6. 6.10.7. 6.10.8. 6.12.1. 6.12.2. 6.13.1. 6.13.2. 6.13.3. 6.13.4. 6.13.5. 6.14.1. 6.14.2. 6.10. 6.11. 6.13. 6.14. A20 User Manual (Revision 1.1) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 7 / 806 CONFIDENTIAL

6.15. 6.16. 6.17. 6.15.1. 6.15.2. 6.16.1. 6.16.2. 6.16.3. 6.14.3. 6.14.4. 6.14.5. 6.14.7. Smart Card Reader Timing Diagram .................................................................... 779 Smart Card Reader Register List ......................................................................... 779 Smart Card Reader Register Description ............................................................. 780 SCIO Pad Configuration ....................................................................................... 792 SATA Host ........................................................................................................................... 793 Overview ............................................................................................................... 793 SATA_AHCI Timing Diagram ................................................................................ 793 CAN ..................................................................................................................................... 794 Overview ............................................................................................................... 794 CAN System Block Diagram ................................................................................. 795 CAN Bit Time Configuration .................................................................................. 795 Keypad ................................................................................................................................. 796 Overview ............................................................................................................... 796 Keypad Interface Register List .............................................................................. 797 Keypad Interface Register Description ................................................................. 797 Keypad Interface Special Requirement ................................................................ 800 Appendix A ................................................................................................................................................ 801 6.17.1. 6.17.2. 6.17.3. 6.17.4. A20 User Manual (Revision 1.1) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 8 / 806 CONFIDENTIAL

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