//定义输入 module project_ba( Clk,Rst_n,KEY1,KEY2, LED); input Clk; input Rst_n; input KEY1; input KEY2; output [15:0] LED;//定义输出 reg [27:0] Cnt; reg Clk_100hz; reg en; reg Key1_n; reg Key1_n_reg; reg Key2_n; reg Key2_n_reg; reg [3:0] t; reg [15:0] led; wire key1,key2; parameter CNT = 28'd49_999; always@(posedge Clk or posedge Rst_n) begin if(Rst_n) begin Cnt <= 28'd0;Clk_100hz <= 0;end else if(Cnt == CNT) begin Cnt <= 28'd0;Clk_100hz <= ~Clk_100hz;end else Cnt <= Cnt + 1'b1; end always@(posedge Clk or posedge Rst_n) begin if(Rst_n) begin Key1_n <= 0;Key2_n <= 0;end else begin Key1_n <= Key1_n_reg; Key2_n <= Key2_n_reg;end end always@(*) begin if(Cnt == CNT) begin Key1_n_reg = KEY1; Key2_n_reg = KEY2;end else begin Key1_n_reg = Key1_n; 

Key2_n_reg = Key2_n;end end assign key1 = Key1_n & (~Key1_n_reg); assign key2 = Key2_n & (~Key2_n_reg); always@(posedge Clk_100hz or posedge Rst_n ) begin if(Rst_n) t <= 7; else if(en) case({key1,key2}) 2'b10 : t <= t + 1'b1; 2'b01 : t <= t - 1'b1; default:t <= t; endcase end always@(posedge Clk) begin if(t == 4'd0 || t == 4'd14) en <= 1'b0; else en <= 1'b1; end always@(*) begin case(t) 4'd0 : led = 16'b0000_0000_0000_0011; 4'd1 : led = 16'b0000_0000_0000_0110; 4'd2 : led = 16'b0000_0000_0000_1100; 4'd3 : led = 16'b0000_0000_0001_1000; 4'd4 : led = 16'b0000_0000_0011_0000; 4'd5 : led = 16'b0000_0000_0110_0000; 4'd6 : led = 16'b0000_0000_1100_0000; 4'd7 : led = 16'b0000_0001_1000_0000; 4'd8 : led = 16'b0000_0011_0000_0000; 4'd9 : led = 16'b0000_0110_0000_0000; 4'd10: led = 16'b0000_1100_0000_0000; 4'd11: led = 16'b0001_1000_0000_0000; 4'd12: led = 16'b0011_0000_0000_0000; 4'd13: led = 16'b0110_0000_0000_0000; 4'd14: led = 16'b1100_0000_0000_0000; default : led = 16'b0000_0000_0000_0000; 

Clk = 0; end endcase end//译码模块 assign LED = led; endmodule 5、测试文件 `define clk_period 10 //定义时钟周期 module BaTB(); reg Clk; reg Rst_n; reg KEY1，KEY2; wire[15:0] LED; project_ba u0( .Clk(Clk), .Rst_n(Rst_n), .KEY1(KEY1), .KEY2(KEY2), .LED(LED)); initial begin always #(`clk_period /2) Clk = ~ Clk; initial begin KEY1 = 0;KEY2 = 0; #(`clk_period * 10) ; Rst_n = 1; #(`clk_period * 10); Rst_n = 0; KEY1 = 1;KEY2 = 0; #(`clk_period * 100); KEY1 = 1;KEY2 = 0; #(`clk_period * 100); KEY1 = 1;KEY2 = 0; end endmodule 6、管脚约束 set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}] 

set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}] set_property PACKAGE_PIN L1 [get_ports {LED[15]}] set_property PACKAGE_PIN P1 [get_ports {LED[14]}] set_property PACKAGE_PIN N3 [get_ports {LED[13]}] set_property PACKAGE_PIN P3 [get_ports {LED[12]}] set_property PACKAGE_PIN U3 [get_ports {LED[11]}] set_property PACKAGE_PIN W3 [get_ports set_property PACKAGE_PIN V3 [get_ports {LED[9]}] set_property PACKAGE_PIN V13 [get_ports {LED[8]}] set_property PACKAGE_PIN V14 [get_ports {LED[7]}] set_property PACKAGE_PIN U14 [get_ports {LED[6]}] set_property PACKAGE_PIN U15 [get_ports {LED[5]}] set_property PACKAGE_PIN W18 [get_ports {LED[4]}] set_property PACKAGE_PIN V19 [get_ports {LED[3]}] set_property PACKAGE_PIN U19 [get_ports {LED[2]}] set_property PACKAGE_PIN E19 [get_ports {LED[1]}] set_property PACKAGE_PIN U16 [get_ports {LED[0]}] set_property PACKAGE_PIN W5 [get_port {LED[10]}]