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Xilinx Virtex-7 VC707用户手册手册.pdf
VC707 Evaluation Board for the Virtex-7 FPGA
Revision History
Table of Contents
Ch. 1: VC707 Evaluation Board Features
Overview
Additional Information
VC707 Board Features
Feature Descriptions
Virtex-7 XC7VX485T-2FFG1761C FPGA
DDR3 Memory
Linear BPI Flash Memory
USB 2.0 ULPI Transceiver
SD Card Interface
USB JTAG
Clock Generation
GTX Transceivers
PCI Express Endpoint Connectivity
SFP/SFP+ Module Connector
10/100/1000 Tri-Speed Ethernet PHY
SGMII GTX Transceiver Clock Generation
USB-to-UART Bridge
HDMI Video Output
LCD Character Display (16 x 2)
I2C Bus
Status LEDs
User I/O
Switches
VITA 57.1 FMC1 HPC Connector (Partially Populated)
VITA 57.1 FMC2 HPC Connector (Partially Populated)
Power Management
XADC Analog-to-Digital Converter
Configuration Options
Appx. A: Default Switch and Jumper Settings
GPIO DIP Switch SW2
Configuration DIP Switch SW11
Default Jumper Settings
Appx. B: VITA 57.1 FMC Connector Pinouts
Appx. C: Master Constraints File Listing
VC707 Board XDC Listing
Appx. D: Board Setup
Installing VC707 Board in a PC Chassis
Appx. E: Board Specifications
Dimensions
Environmental
Temperature
Humidity
Operating Voltage
Appx. F: Additional Resources
Xilinx Resources
Solution Centers
References
Appx. G: Regulatory and Compliance Information
Declaration of Conformity
Directives
Standards
Electromagnetic Compatibility
Safety
Markings
VC707 Evaluation
Board for the
Virtex-7 FPGA
User Guide
UG885 (v1.7.1) August 12, 2016
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are
subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx.
Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk
and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
http://www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT
OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE
IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD
("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS,
THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A
SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING
LIMITATIONS ON PRODUCT LIABILITY.
© Copyright 2012 – 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Vivado, Virtex, Zynq, and other designated brands
included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of
PCI-SIG. HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks of HDMI Licensing LLC. All other trademarks are the
property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date
Version
03/05/12
10/08/12
1.0
1.1
Revision
Initial Xilinx release.
Chapter 1, VC707 Evaluation Board Features: In Table 1-1, notes for J37 changed to
Samtec ASP_134486_01. The board photo in Figure 1-2 was replaced. In Table 1-3, GPGA
(U1) Bank 32 was deleted. A note was added about the user clock for Figure 1-10. In
Table 1-15, FPGA pin AN1 changed to AM4 and pin AN2 changed to AM3. In SGMII
GTX Transceiver Clock Generation, page 42, 25 MHz LVDS clock changed to 125 MHz
LVDS clock. The Figure 1-10 title also changed from 25 MHz to 125 MHz. In Table 1-23,
pin AR42 changed to AT42. In Figure 1-33, switching regulator supply voltage UG63 for
MGTVCCAUX was updated. In Table 1-29, device type PTD08D021W (VOUT A) power
rail voltage changed to 1.80V. In Table 1-32, values for rail number 3 changed. In
Appendix C, Master Constraints File Listing, the entire listing was replaced.
Appendix G, Regulatory and Compliance Information now includes a link to the
Declaration of Conformity and markings for waste electrical and electronic equipment
(WEEE), restriction of hazardous substances (RoHS), and CE compliance.
VC707 Evaluation Board
www.xilinx.com
UG885 (v1.7.1) August 12, 2016
Date
Version
02/01/13
1.2
08/22/13
05/12/14
09/20/14
1.3
1.4
1.5
04/07/15
1.6
09/01/15
03/26/16
1.6.1
1.7
08/12/16
1.7.1
Revision
Updated VC707 Board Features, Table 1-1, Virtex-7 XC7VX485T-2FFG1761C FPGA,
FPGA Configuration, USB JTAG, System Clock (SYSCLK_P and SYSCLK_N), HDMI
Video Output, I2C Bus, Table 1-15, User I/O, Table 1-26, Power Management, and VITA
57.1 FMC2 HPC Connector (Partially Populated). Updated Figure 1-5, Figure 1-16, and
Figure 1-25. Updated paragraph following Table 1-4, Figure 1-7, Figure 1-19, Figure 1-20,
and Table 1-24. Added CPU Reset Pushbutton, User Rotary Switch, User SMA, and PCIe
Form Factor Board TI Power System Cooling. Added Table 1-27 and Table 1-28.
Replaced PTD08D021W with PTD08D210W in Table 1-29. Added third paragraph to the
introduction in Appendix C, Master Constraints File Listing. Added UG483 and
removed NXP Semiconductors in Appendix F, Additional Resources. Added second
paragraph to the introduction in Appendix G, Regulatory and Compliance Information.
Updated Figure 1-2, Table 1-1, Table 1-12, Table 1-13, and Table 1-14. Updated Linear BPI
Flash Memory. Replaced Master UCF Listing with Appendix C, Master Constraints File
Listing.
Updated disclaimer and copyright. In Table 1-27, changed U1 FPGA pin N39 to M39, B36
to A35, and B37 to A36.
Added note to Table 1-1 and Table 1-27. Updated Table 1-7. Changed Net Name column
heading to FHG1761 Placement in Table 1-11. Added I/O standard information to
Table 1-4, Table 1-5, Table 1-8, Table 1-10, Table 1-18, Table 1-21, Table 1-23, Table 1-26,
Table 1-27 and Table 1-28. Updated schematic net name for pins C34 and D35 in
Table 1-27 and Table 1-28. Updated GTX Transceivers. Added Figure A-3.
Added notes to Jitter Attenuated Clock and I2C Bus. Updated Table 1-24. Deleted
redundant Figure B-2 FMC2 HPC Connector Pinout in Appendix B, VITA 57.1 FMC
Connector Pinouts. Added information for ordering the ATX power supply adapter
cable.
Made typographical edits.
Updated transceiver bank MGT_BANK_119 in Table 1-11. Updated GPIO pin for CPU
reset pushbutton switch in Table 1-26. Updated U1 FPGA pins for J37 FMC2 HPC pins
B12, B13, B32, and B33 in Table 1-28. Added thickness information in Appendix E, Board
Specifications.
Made a typographical edit.
UG885 (v1.7.1) August 12, 2016
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VC707 Evaluation Board
VC707 Evaluation Board
www.xilinx.com
UG885 (v1.7.1) August 12, 2016
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: VC707 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VC707 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Virtex-7 XC7VX485T-2FFG1761C FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DDR3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Linear BPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
USB 2.0 ULPI Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SFP/SFP+ Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SGMII GTX Transceiver Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
HDMI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LCD Character Display (16 x 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VITA 57.1 FMC1 HPC Connector (Partially Populated) . . . . . . . . . . . . . . . . . . . . . . . . 58
VITA 57.1 FMC2 HPC Connector (Partially Populated) . . . . . . . . . . . . . . . . . . . . . . . . 58
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
XADC Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Appendix A: Default Switch and Jumper Settings
GPIO DIP Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Configuration DIP Switch SW11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Default Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Master Constraints File Listing
VC707 Board XDC Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Appendix D: Board Setup
Installing VC707 Board in a PC Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Appendix E: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Appendix F: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Solution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Appendix G: Regulatory and Compliance Information
Declaration of Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6
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Chapter 1
VC707 Evaluation Board Features
Overview
The VC707 evaluation board for the Virtex®-7 FPGA provides a hardware environment for
developing and evaluating designs targeting the Virtex-7 XC7VX485T-2FFG1761C FPGA.
The VC707 board provides features common to many embedded processing systems,
including a DDR3 SODIMM memory, an 8-lane PCI Express® interface, a tri-mode
Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can be
added by using mezzanine cards attached to either of two VITA-57 FPGA mezzanine
connectors (FMC) provided on the board. Two high pin count (HPC) FMCs are provided.
See VC707 Board Features for a complete list of features. The details for each feature are
described in Feature Descriptions, page 10.
Additional Information
See Appendix F, Additional Resources for references to documents, files and resources
relevant to the VC707 board.
VC707 Board Features
Virtex-7 XC7VX485T-2FFG1761C FPGA
1 GB DDR3 memory SODIMM
128 MB Linear byte peripheral interface (BPI) Flash memory
USB 2.0 ULPI Transceiver
Secure Digital (SD) connector
USB JTAG through Digilent module
Clock Generation
Fixed 200 MHz LVDS oscillator (differential)
I2C programmable LVDS oscillator (differential)
SMA connectors (differential)
SMA connectors for GTX transceiver clocking
GTX transceivers
FMC1 HPC connector (eight GTX transceivers)
FMC2 HPC connector (eight GTX transceiver)
SMA connectors (one pair each for TX, RX, and REFCLK)
PCI Express (eight lanes)
Small form-factor pluggable plus (SFP+) connector
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Chapter 1: VC707 Evaluation Board Features
Ethernet PHY SGMII interface (RJ-45 connector)
PCI Express endpoint connectivity
Gen1 8-lane (x8)
Gen2 8-lane (x8)
SFP+ Connector
10/100/1000 tri-speed Ethernet PHY
USB-to-UART bridge
HDMI™ codec
I2C bus
I2C MUX
I2C EEPROM (1 KB)
USER I2C programmable LVDS oscillator
DDR3 SODIMM socket
HDMI codec
FMC1 HPC connector
FMC2 HPC connector
SFP+ connector
I2C programmable jitter-attenuating precision clock multiplier
Status LEDs
Ethernet status
Power good
FPGA INIT
FPGA DONE
User I/O
User LEDs (eight GPIO)
User pushbuttons (five directional)
CPU reset pushbutton
User DIP switch (8-pole GPIO)
User SMA GPIO connectors (one pair)
LCD character display (16 characters x 2 lines)
Switches
Power on/off slide switch
FPGA_PROB_B pushbutton
Configuration mode DIP switch
VITA 57.1 FMC1 HPC Connector
VITA 57.1 FMC2 HPC Connector
Power management
PMBus voltage and current monitoring through TI power controller
XADC header
Configuration options
8
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