library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED; entity parallel_tap is generic( iInDataWidth : integer := 3; iOutDataWidth : integer := 7; iOverSampleRate : integer := 4 ); port( InCode : in std_logic; InData : in std_logic_vector (iInDataWidth-1 downto 0); PrevTap : in std_logic_vector (iOutDataWidth-1 downto 0); SysClk : in std_logic; SysRst : in std_logic; OutCode : out std_logic; Result : out std_logic_vector (iOutDataWidth-1 downto 0) ); end parallel_tap ; architecture Virtex of parallel_tap is type PipeLineArray is array (iOverSampleRate-2 downto 0) of signed(iOutDataWidth-1 downto 0); signal sInData : signed(iInDataWidth-1 downto 0); signal sPrevTap : signed(iOutDataWidth-1 downto 0); signal sAddSubOut : signed(iOutDataWidth-1 downto 0); signal sPipe : PipeLineArray; signal lCodeData : std_logic; begin sInData <= signed(InData); sPrevTap <= signed(PrevTap); SingleTap : process (SysClk,SysRst) begin 

if (SysRst = '1') then sAddSubOut <= (others => '0'); lCodeData <= '0'; elsif (SysClk'event and SysClk ='1') then lCodeData <= InCode; if (lCodeData = '0') then sAddSubOut <= sPrevTap + sInData; else sAddSubOut <= sPrevTap - sInData; end if; end if; end process SingleTap; GeneratePipeline : process (SysClk) begin if (SysClk'event and SysClk = '1') then sPipe <= sPipe(iOverSampleRate-3 downto sPipe'low) & sAddSubOut; end if; end process GeneratePipeline; --Source output data FeedThruCode : OutCode <= lCodeData; GenerateResult : Result <= std_logic_vector(sPipe(iOverSampleRate-2)); end Virtex; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED; entity mf is generic( iInDataWidth : integer := 3; iOutDataWidth : integer :=7; iOverSampleRate : integer := 4; iNumOfChips : integer := 4 

); port( InCode : in std_logic; InData : in std_logic_vector (iInDataWidth-1 downto 0); SysClk: in std_logic; SysRst : in std_logic; Result : out std_logic_vector (iOutDataWidth-1 downto 0) ); end mf; architecture virtex of mf is type ResultArray is array (iNumOfChips-1 downto 0) of std_logic_vector (iOutDataWidth-1 downto 0); signal Zero : std_logic_vector (iOutDataWidth-1 downto 0); signal lOutCode : std_logic_vector (iNumOfChips-1 downto 0); signal lResult : ResultArray; component parallel_tap generic ( iInDataWidth : integer := 8; iOutDataWidth : integer := 16; iOverSampleRate : integer := 16 ); port ( InCode : in std_logic; InData : in std_logic_vector (iInDataWidth-1 downto 0); PrevTap : in std_logic_vector (iOutDataWidth-1 downto 0); SysClk : in std_logic; SysRst : in std_logic; OutCode : out std_logic; Result : out std_logic_vector (iOutDataWidth-1 downto 0) ); end component; begin Zero <= (others =>'0'); FirstTap : parallel_tap 

generic map ( iInDataWidth => iInDataWidth, iOutDataWidth => iOutDataWidth, iOverSampleRate => iOverSampleRate ) port map ( InCode => InCode, InData => InData, PrevTap => Zero, SysClk => SysClk, SysRst => SysRst, OutCode => lOutCode(0), Result => lResult(0) ); InstTaps: for I in 1 to iNumOfChips-1 generate Taps : parallel_tap generic map( iInDataWidth => iInDataWidth, iOutDataWidth => iOutDataWidth, iOverSampleRate => iOverSampleRate ) port map ( InCode => lOutCode(I-1), InData => InData, PrevTap => lResult(I-1), SysClk => SysClk, SysRst => SysRst, OutCode => lOutCode(I), Result => lResult(I) ); end generate InstTaps; GenerateResult : Result <= lResult(iNumOfChips-1); end virtex;