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dw_apb_ssi_db.pdf
Documentation Overview
DW_apb_ssi Release Notes
Contents
Preface
About This Manual
Related Documents
Manual Overview
Typographical and Symbol Conventions
Table 1: Documentation Conventions
Getting Help
Additional Information
Comments?
1 Product Overview
DesignWare AMBA System Overview
DesignWare AMBA System Block Diagram
Figure 1: Example of DW_apb_ssi in a Complete System
General Product Description
DW_apb_ssi Block Diagram
Figure 2: DW_apb_ssi Block Diagram
Features
Standards Compliance
Verification Environment Overview
Licenses
Where to Go From Here
Table 2: Tool Comparison
2 Building and Verifying a Subsystem
Setting up Your Environment
Overview of the Configuration and Integration Process
Figure 3: Connect Usage Flow
Table 3: Connect Workspace Directory Contents
Start Connect
Check Your Environment
Add DW_apb_ssi to the Subsystem
Figure 4: DW_apb_ssi in Simple Subsystem
Configure DW_apb_ssi
Complete Signal Connections
Generate Subsystem RTL
Create Gate-Level Netlist
Checking Synthesis Status and Results
Synthesis Output Files
Running Synthesis from Command Line
Create Component GTECH Simulation Model
Verify Component
Checking Simulation Status and Results
Applying Default Verification Attributes
Verify the Subsystem
Formal Verification
Simulate Subsystem
Checking Subsystem Verification Status and Results
Create a Batch Script
Export the Subsystem
3 Functional Description
DW_apb_ssi Overview
Figure 5: Hardware/Software Slave Selection
Clock Ratios
Figure 6: Maximum sclk_out/ssi_clk Ratio
Figure 7: Slave ssi_clk/sclk_in Ratio
Transmit and Receive FIFO Buffers
SSI Interrupts
Transfer Modes
Transmit and Receive
Transmit Only
Receive Only
EEPROM Read
Operation Modes
Serial-Master Mode
Figure 8: DW_apb_ssi Configured as Master Device
Figure 9: Arbitration Between Multiple Serial Masters
Figure 10: Glue Logic for Controlling Logic Level on Master ss_in_n Input
Figure 11: DW_apb_ssi Master SPI/SSP Transfer Flow
Figure 12: DW_apb_ssi Master Microwire Transfer Flow
Serial-Slave Mode
Figure 13: DW_apb_ssi Configured as Slave Device
Figure 14: DW_apb_ssi Slave SPI/SSP Transfer Flow
Partner Connection Interfaces
Motorola Serial Peripheral Interface (SPI)
Figure 15: SPI Serial Format (SCPH = 0)
Figure 16: SPI Serial Format Continuous Transfers (SCPH = 0)
Figure 17: SPI Serial Format (SCPH = 1)
Figure 18: SPI Serial Format Continuous Transfer (SCPH = 1)
Figure 19: FIFO Status for Transmit & Receive SPI and SSP Transfers
Figure 20: FIFO Status for Transmit Only SPI and SSP Transfers
Figure 21: FIFO Status for Receive Only SPI and SSP Transfers
Figure 22: FIFO Status for EEPROM Read Transfer Mode
Texas Instruments Synchronous Serial Protocol (SSP)
Figure 23: SSP Serial Format
Figure 24: SSP Serial Format Continuous Transfer
National Semiconductor Microwire
Figure 25: Single DW_apb_ssi Master Microwire Serial Transfer (MDD=0)
Figure 26: FIFO Status for Single Microwire Transfer (receiving data frame)
Figure 27: Continuous Nonsequential Microwire Transfer (receiving data frame)
Figure 28: FIFO Status for Nonsequential Microwire Transfer (receiving data frame)
Figure 29: Continuous Sequential Microwire Transfer (receiving data frame)
Figure 30: FIFO Status for Sequential Microwire Transfer (receiving data frame)
Figure 31: Single Microwire Transfer (transmitting data frame)
Figure 32: FIFO Status for Single Microwire Transfer (transmitting data frame)
Figure 33: Continuous Microwire Transfer (transmitting data frame)
Figure 34: FIFO Status for Continuous Microwire Transfer (transmitting data frame)
Figure 35: Continuous Microwire Transfer with Handshaking (transmitting data frame)
Figure 36: FIFO Status for Microwire Control Word Transfer
Figure 37: Microwire Control Word
Figure 38: Single DW_apb_ssi Slave Microwire Serial Transfer (MDD=0)
Figure 39: FIFO Status for Single Microwire Transfer (receiving data frame)
Figure 40: Single DW_apb_ssi Slave Microwire Serial Transfer (MDD=1)
Figure 41: FIFO Status for Single Microwire Transfer (transmitting data frame)
DMA Controller Interface
Overview of Operation
Figure 42: Breakdown of DMA Transfer into Burst Transactions
Figure 43: Breakdown of DMA Transfer into Single and Burst Transactions
Transmit Watermark Level and Transmit FIFO Underflow
Choosing the Transmit Watermark Level
Figure 44: Case 1 Watermark Levels
Figure 45: Case 2 Watermark Levels
Selecting DEST_MSIZE and Transmit FIFO Overflow
Receive Watermark Level and Receive FIFO Overflow
Choosing the Receive Watermark level
Selecting SRC_MSIZE and Receive FIFO Underflow
Figure 46: SSI Receive FIFO
Handshaking Interface Operation
Figure 47: Burst Transaction - pclk = hclk
Figure 48: Back-to-Back Burst Transactions - hclk = 2*pclk
Figure 49: Single Transaction
Figure 50: Burst Transaction + 3 Back-to-Back Singles - hclk = 2*pclk
APB Interface
Control and Status Register APB Access
Data Register APB Access
4 Parameters
Parameter Descriptions
Table 4: Top-Level Parameters
Table 5: Derived Configuration Parameters
5 Signals
DW_apb_ssi Interface Diagram
Figure 51: DW_apb_ssi Interface Diagram
DW_apb_ssi Signal Descriptions
Table 6: DW_apb_ssi Signal Description
6 Registers
Register Memory Map
Table 7: Memory Map of DW_apb_ssi
Register and Field Descriptions
Table 8: DFS Decode
Table 9: CFS Decode
Table 10: TFT Decode
Table 11: RFT
Table 12: DMA Transmit Data Level
Table 13: DMATDL Decode Value
Table 14: DMARDL Decode Value
7 Programming the DW_apb_ssi
Programming Considerations
8 Verification
Overview of Vera Tests
APB Interface
DW_apb_ssi as Master
DW_apb_ssi as Slave
DW_apb_ssi with DMA Interface
Interrupts
Overview of DW_apb_ssi Testbench
Figure 52: DW_apb_ssi Testbench
Figure 53:
9 Integration Considerations
Reading and Writing from an APB Slave
Reading From Unused Locations
Figure 54: Read/Write Locations for Different APB Bus Data Widths
32-bit Bus System
16-bit Bus System
8-bit Bus System
Write Timing Operation
Figure 55: APB Write Transaction
Read Timing Operation
Figure 56: APB Read Transaction
Accessing Top-level Constraints
Coherency
Writing Coherently
Table 15: Upper Byte Generation
Figure 57: Coherent Loading - Identical Synchronous Clocks
Figure 58: Coherent Loading - Identical Synchronous Clocks
Figure 59: Coherent Loading - Synchronous Clocks
Figure 60: Coherent Loading - Synchronous Clocks
Figure 61: Coherent Loading - Asynchronous Clocks
Figure 62: Coherent Loading - Asynchronous Clocks
Reading Coherently
Table 16: Lower Byte Generation
Figure 63: Coherent Registering - Synchronous Clocks
Figure 64: Coherent Registering - Synchronous Clocks
Figure 65: Coherency and Shadow Registering - Asynchronous Clocks
Figure 66: Transfer to Shadowing Registers- Asynchronous Clocks
A Building and Verifying Your DW_apb_ssi
Setting up Your Environment
Starting coreConsultant
Checking Your Environment
Configuring the DW_apb_ssi
Synthesizing the DW_apb_ssi
Checking Synthesis Status and Results
Synthesis Output Files
Running Synthesis from Command Line
Verifying the DW_apb_ssi
Creating GTECH Simulation Models
Verifying the Simulation Model
Checking Simulation Status and Results
Creating a Batch Script
Applying Default Verification Attributes
B Application Notes
Interfacing DW_apb_ssi and Atmel SPI Devices
Synopsys SPI Operation
Figure 67: DW_apb_ssi SPI: Continuous Transfer where SCPH = 0 and SCPOL = 0
Figure 68: DW_apb_ssi SPI: Continuous Transfer where SCPH=1 and SCPOL=1
Atmel SPI Operation
Figure 69: Atmel SPI: Continuous Transfer with SCPH=0 and SCPOL=0
Interoperability between DW_apb_ssi and Atmel Devices
C Database Description
Design/HDL Files
RTL-Level Files
Table 17: RTL-Level Files
Simulation Model Files
Table 18: Simulation Model Files
Register Map Files
Table 19: Header Files
Synthesis Files
Table 20: Synthesis Files
Verification Reference Files
Table 21: Verification Reference Files
D DesignWare QuickStart Designs
QuickStart Example Designs
E Glossary
Index
A
B
C
D
E
F
G
H
I
L
M
N
O
P
R
S
T
U
V
W
Z
DesignWare DW_apb_ssi Databook
DesignWare Synthesizable Components for AMBA2
DW_apb_ssi
Version 3.10a
May 22, 2006
DesignWare DW_apb_ssi Databook
Copyright Notice and Proprietary Information
Copyright © 2005 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is
the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in
accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or
translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys,
Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to
nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the
applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD
TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.
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Compiler, DesignPower, DesignWare, EPIC, Formality, HSPICE, Hypermodel, I, iN-Phase, in-Sync, Leda, MAST, Meta, Meta-
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System Simulator, VirSim, and VMC are trademarks of Synopsys, Inc.
Service Marks (SM)
MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.
SystemC is a trademark of the Open SystemC Initiative and is used under license.
ARM and AMBA are registered trademarks of ARM Limited.
All other product or company names may be trademarks of their respective owners.
2
Synopsys, Inc.
May 22, 2006
DesignWare DW_apb_ssi Databook
Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Manual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typographical and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Comments? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DesignWare AMBA System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DesignWare AMBA System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DW_apb_ssi Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Verification Environment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Where to Go From Here . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 2
Building and Verifying a Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting up Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overview of the Configuration and Integration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Start Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Check Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Add DW_apb_ssi to the Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configure DW_apb_ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Complete Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Generate Subsystem RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Create Gate-Level Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Checking Synthesis Status and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Synthesis Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Running Synthesis from Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Create Component GTECH Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Verify Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Checking Simulation Status and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Applying Default Verification Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Verify the Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Simulate Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
May 22, 2006
Synopsys, Inc.
3
Contents
DesignWare DW_apb_ssi Databook
Checking Subsystem Verification Status and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Create a Batch Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Export the Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DW_apb_ssi Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Transmit and Receive FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SSI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Transmit and Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Transmit Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Receive Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
EEPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Serial-Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Serial-Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Partner Connection Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Motorola Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Texas Instruments Synchronous Serial Protocol (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
National Semiconductor Microwire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DMA Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Overview of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Transmit Watermark Level and Transmit FIFO Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Choosing the Transmit Watermark Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Selecting DEST_MSIZE and Transmit FIFO Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Receive Watermark Level and Receive FIFO Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Choosing the Receive Watermark level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Selecting SRC_MSIZE and Receive FIFO Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Handshaking Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
APB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Control and Status Register APB Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Data Register APB Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Chapter 4
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chapter 5
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
DW_apb_ssi Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DW_apb_ssi Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Register and Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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Synopsys, Inc.
May 22, 2006
DesignWare DW_apb_ssi Databook
Contents
Chapter 7
Programming the DW_apb_ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Chapter 8
Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Overview of Vera Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
APB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
DW_apb_ssi as Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DW_apb_ssi as Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DW_apb_ssi with DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Overview of DW_apb_ssi Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Chapter 9
Integration Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Reading and Writing from an APB Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Reading From Unused Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
32-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
16-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Write Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Read Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Accessing Top-level Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Writing Coherently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Reading Coherently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Appendix A
Building and Verifying Your DW_apb_ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Setting up Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Starting coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Checking Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Configuring the DW_apb_ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Synthesizing the DW_apb_ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Checking Synthesis Status and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Synthesis Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Running Synthesis from Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Verifying the DW_apb_ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Creating GTECH Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Verifying the Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Checking Simulation Status and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Creating a Batch Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Applying Default Verification Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Appendix B
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Interfacing DW_apb_ssi and Atmel SPI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
May 22, 2006
Synopsys, Inc.
5
Contents
DesignWare DW_apb_ssi Databook
Synopsys SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Atmel SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Interoperability between DW_apb_ssi and Atmel Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Appendix C
Database Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Design/HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
RTL-Level Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Simulation Model Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Register Map Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Synthesis Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Verification Reference Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Appendix D
DesignWare QuickStart Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
QuickStart Example Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Appendix E
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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Synopsys, Inc.
May 22, 2006
DesignWare DW_apb_ssi Databook
Preface
Preface
About This Manual
This databook provides information that you need to interface the DesignWare Synchronous Serial
Interface (SSI), referred to as DW_apb_ssi throughout the remainder of this databook. This component
conforms to the AMBA Specification, Revision 2.0 from ARM.
The information in this databook includes a functional description, signal and parameter descriptions,
and a memory map. Also provided are an overview of the component testbench, a description of the
tests that are run to verify the coreKit, and synthesis information for the coreKit.
Related Documents
To see a complete listing of documentation within the DesignWare Synthesizable Components for
AMBA 2, refer to the Guide to DesignWare AMBA IP Component Documentation.
Manual Overview
This manual contains the following chapters and appendixes:
Chapter 1
“Product Overview”
Provides a DesignWare AMBA System Overview, a component block
diagram, basic features, and an overview of the verification
environment.
Chapter 2
“Building and Verifying a Subsystem”
Provides getting started information that allows you to walk through
the process of using the DW_apb_ssi with Synopsys’ DesignWare
Connect tool.
Chapter 3
“Functional Description”
Describes the functional operation of the DW_apb_ssi.
Chapter 4
“Parameters”
Chapter 5
“Signals”
Chapter 6
“Registers”
Identifies the configurable parameters supported by the DW_apb_ssi
Provides a list and description of the DW_apb_ssi signals.
Describes the programmable registers of the DW_apb_ssi.
Chapter 7
“Programming the DW_apb_ssi”
Chapter 8
“Verification”
Provides information needed to program the configured DW_apb_ssi.
Provides information on verifying the configured DW_apb_ssi.
May 22, 2006
Synopsys, Inc.
7
Preface
DesignWare DW_apb_ssi Databook
Chapter 9
“Integration Considerations”
Appendix A
“Building and Verifying Your
DW_apb_ssi”
Appendix B
“Application Notes” on page 165
Includes information you need to integrate the configured DW_apb_ssi
into your design.
Provides an application note about interfacing a DW_apb_ssi SPI
device with an Atmel SPI peripheral.
Provides getting started information that allows you to walk through
the process of using the DW_apb_ssi with Synopsys coreConsultant
tool.
Appendix C
“Database Description”
Provides deliverables and reference files generated from the
coreConsultant flow.
Appendix D
“DesignWare QuickStart Designs”
Provides the locations of QuickStart examples that integrate most
DesignWare AMBA Synthesizable Components into an SoC design
that you can simulate.
Appendix E
“Glossary”
Provides a glossary of general terms.
Typographical and Symbol Conventions
The following conventions are used throughout this document:
Table 1: Documentation Conventions
Convention
Description and Example
%
Bold
Monospace
Represents the UNIX prompt.
User input (text entered by the user).
% cd $LMC_HOME/hdl
System-generated text (prompts, messages, files, reports).
No Mismatches: 66 Vectors processed: 66 Possible"
Italic or Italic
Variables for which you supply a specific value. As a command line example:
% setenv LMC_HOME prod_dir
In body text:
In the previous example, prod_dir is the directory where your product must be
installed.
| (Vertical rule)
Choice among alternatives, as in the following syntax example:
-effort_level low | medium | high
[ ] (Square brackets)
Enclose optional parameters:
pin1 [pin2 ... pinN]
In this example, you must enter at least one signal name (pin1), but others are
optional ([pin2 … pinN]).
TopMenu > SubMenu
Pulldown menu paths, such as:
File > Save As …
8
Synopsys, Inc.
May 22, 2006
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