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EMMC 5.1 协议标准.pdf
Cover
Contents
Figures
Tables
Foreword
Introduction
1 Scope
2 Normative reference
3 Terms and definitions
4 System Features
5 e•MMC Device and System
5.1 e•MMC System Overview
5.2 Memory Addressing
5.3 e•MMC Device Overview
5.3.1 Bus Protocol
5.3.2 Bus Speed Modes
5.3.3 HS200 Bus Speed Mode
5.3.4 HS200 System Block Diagram
5.3.5 HS200 Adjustable Sampling Host
5.3.6 HS400 Bus Speed Mode
5.3.7 HS400 System Block Diagram
6 e•MMC functional description
6.1 e•MMC Overview
6.2 Partition Management
6.2.1 General
6.2.2 Command restrictions
6.2.3 Extended Partitions Attribute
6.2.4 Configure partitions
6.2.5 Access partitions
6.3 Boot operation mode
6.3.1 Device reset to Pre-idle state
6.3.2 Boot partition
6.3.3 Boot operation
6.3.4 Alternative boot operation
6.3.5 Access to boot partition
6.3.6 Boot bus width and data access configuration
6.3.7 Boot Partition Write Protection
6.4 Device identification mode
6.4.1 Device reset
6.4.2 Access mode validation (higher than 2GB of densities)
6.4.3 From busy to ready
6.4.4 Device identification process
6.5 Interrupt mode
6.6 Data transfer mode
6.6.1 Command sets and extended settings
6.6.2 High-speed modes selection
6.6.2.1 “High-speed” mode selection
6.6.2.2 “HS200” timing mode selection
6.6.2.3 “HS400” timing mode selection
6.6.3 Power class selection
6.6.4 Bus testing procedure
6.6.5 Bus Sampling Tuning Concept
6.6.5.1 Sampling Tuning Sequence for HS200
6.6.6 Bus width selection
6.6.7 Data read
6.6.7.1 Block read
6.6.8 Data write
6.6.8.1 Block write
6.6.9 Erase
6.6.10 TRIM
6.6.11 Sanitize
6.6.12 Discard
6.6.13 Secure Erase
6.6.14 Secure Trim
6.6.15 Write protect management
6.6.16 Extended Security Protocols Pass Through Commands
6.6.16.1 PROTOCOL_RD - CMD53
6.6.16.2 PROTOCOL_WR - CMD54
6.6.16.3 Security Protocol Type
6.6.16.4 Security Protocol Information
6.6.16.5 Error handling
6.6.17 Production State Awareness
6.6.17.1 Manual Mode
6.6.17.2 Auto Mode
6.6.18 Field Firmware Update
6.6.19 Device lock/unlock operation
6.6.20 Application-specific commands
6.6.21 Sleep (CMD5)
6.6.22 Replay Protected Memory Block
6.6.22.1 The Data Frame for Replay Protected Memory Block Access
6.6.22.2 Memory Map of the Replay Protected Memory Block
6.6.22.3 Message Authentication Code Calculation
6.6.22.4 Accesses to the Replay Protected Memory Block
6.6.22.4.1 Programming of the Authentication Key
6.6.22.4.2 Reading of the Counter Value
6.6.22.4.3 Authenticated Data Write
6.6.22.4.4 Authenticated Data Read
6.6.22.4.5 Authenticated Device Configuration Write
6.6.22.4.6 Authenticated Device Configuration Read
6.6.23 Dual Data Rate mode selection
6.6.24 Dual Data Rate mode operation
6.6.25 Background Operations
6.6.26 High Priority Interrupt (HPI)
6.6.27 Context Management
6.6.27.1 Context configuration
6.6.27.2 Context direction
6.6.27.3 Large-Unit
6.6.27.4 Context Writing Interruption
6.6.27.5 Large-Unit Multipliers
6.6.28 Data Tag Mechanism
6.6.29 Packed Commands
6.6.29.1 Packed Command Header
6.6.29.2 Packed Commands Error Handling
6.6.30 Exception Events
6.6.31 Cache
6.6.32 Features cross matrix
6.6.33 Dynamic Capacity Management
6.6.34 Large sector size
6.6.34.1 Disabling emulation mode
6.6.34.2 Native 4KB sector behavior
6.6.35 Real Time Clock Information
6.6.35.1 Periodic Wake-up
6.6.36 Power Off Notification
6.6.37 Cache Enhancement Barrier
6.6.38 Cache Flushing Policy
6.6.39 Command Queuing
6.6.39.1 Overview
6.6.39.2 QUEUED_TASK_PARAMS - CMD44
6.6.39.3 QUEUED_TASK_ADDRESS - CMD45
6.6.39.4 EXECUTE_READ_TASK - CMD46
6.6.39.5 EXECUTE_WRITE_TASK - CMD47
6.6.39.6 CMDQ_TASK_MGMT - CMD48
6.6.39.7 SEND_STATUS - CMD13
6.6.39.8 Error handling
6.6.39.9 Supported Commands
6.6.40 Secure Write Protect Mode
6.7 Clock control
6.8 Error conditions
6.8.1 CRC and illegal command
6.8.2 Time-out conditions
6.8.3 Read ahead in multiple block read operation
6.9 Minimum performance
6.9.1 Speed class definition
6.9.2 Measurement of the performance
6.10 Commands
6.10.1 Command types
6.10.2 Command format
6.10.3 Command classes
6.10.4 Detailed command description
6.11 Device state transition table
6.12 Responses
6.13 Device status
6.14 Memory array partitioning
6.15 Timings
6.15.1 Command and response
6.15.2 Data read
6.15.3 Data write
6.15.4 Bus test procedure timing
6.15.5 Boot operation
6.15.6 Alternative boot operation
6.15.7 Timing Values
6.15.8 Timing changes in HS200 and HS400 mode
6.15.8.1 Timing values
6.15.8.2 Read Block Gap
6.15.8.3 CMD12 Timing Modification in Write Operation
6.15.8.4 CMD12 Timing Modification in Read Operation
6.15.8.5 R1b Timing
6.15.8.6 Reselecting a Busy Device
6.15.9 Enhanced Strobe in HS400 Mode
6.15.10 H/W Reset Operation
6.15.11 Noise filtering timing for H/W Reset
6.15.12 Additional Timing changes in HS400 mode
6.15.12.1 Write Timing
6.15.12.2 Read Timing
7 Device Registers
7.1 OCR register
7.2 CID register
7.2.1 MID [127:120]
7.2.2 CBX [113:112]
7.2.3 OID [111:104]
7.2.4 PNM [103:56]
7.2.5 PRV [55:48]
7.2.6 PSN [47:16]
7.2.7 MDT [15:8]
7.2.8 CRC [7:1]
7.3 CSD register
7.3.1 CSD_STRUCTURE [127:126]
7.3.2 SPEC_VERS [125:122]
7.3.3 TAAC [119:112]
7.3.4 NSAC [111:104]
7.3.5 TRAN_SPEED [103:96]
7.3.6 CCC [95:84]
7.3.7 READ_BL_LEN [83:80]
7.3.8 READ_BL_PARTIAL [79]
7.3.9 WRITE_BLK_MISALIGN [78]
7.3.10 READ_BLK_MISALIGN [77]
7.3.11 DSR_IMP [76]
7.3.12 C_SIZE [73:62]
7.3.13 VDD_R_CURR_MIN [61:59] and VDD_W_CURR_MIN [55:53]
7.3.14 VDD_R_CURR_MAX [58:56] and VDD_W_CURR_MAX [52:50]
7.3.15 C_SIZE_MULT [49:47]
7.3.16 ERASE_GRP_SIZE [46:42]
7.3.17 ERASE_GRP_MULT [41:37]
7.3.18 WP_GRP_SIZE [36:32]
7.3.19 WP_GRP_ENABLE [31]
7.3.20 DEFAULT_ECC [30:29]
7.3.21 R2W_FACTOR [28:26]
7.3.22 WRITE_BL_LEN [25:22]
7.3.23 WRITE_BL_PARTIAL[21]
7.3.24 CONTENT_PROT_APP [16]
7.3.25 FILE_FORMAT_GRP [15]
7.3.26 COPY [14]
7.3.27 PERM_WRITE_PROTECT [13]
7.3.28 TMP_WRITE_PROTECT [12]
7.3.29 FILE_FORMAT [11:10]
7.3.30 ECC [9:8]
7.3.31 CRC [7:1]
7.4 Extended CSD register
7.4.1 EXT_SECURITY_ERR [505]
7.4.2 S_CMD_SET [504]
7.4.3 HPI_FEATURES [503]
7.4.4 BKOPS_SUPPORT [502]
7.4.5 MAX_PACKED_READS [501]
7.4.6 MAX_PACKED_WRITES [500]
7.4.7 DATA_TAG_SUPPORT [499]
7.4.8 TAG_UNIT_SIZE [498]
7.4.9 TAG_RES_SIZE [497]
7.4.10 CONTEXT_CAPABILITIES [496]
7.4.11 LARGE_UNIT_SIZE_M1 [495]
7.4.12 EXT_SUPPORT [494]
7.4.13 SUPPORTED_MODES [493]
7.4.14 FFU_FEATURES [492]
7.4.15 OPERATION_CODES_TIMEOUT [491]
7.4.16 FFU_ARG [490-487]
7.4.17 BARRIER_SUPPORT [486]
7.4.18 CMDQ_SUPPORT [308]
7.4.19 CMDQ_DEPTH [307]
7.4.20 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305-302]
7.4.21 VENDOR_PROPRIETARY_HEALTH_REPORT [301-270]
7.4.22 DEVICE_LIFE_TIME_EST_TYP_B [269]
7.4.23 DEVICE_LIFE_TIME_EST_TYP_A [268]
7.4.24 PRE_EOL_INFO [267]
7.4.25 OPTIMAL_READ_SIZE [266]
7.4.26 OPTIMAL_WRITE_SIZE [265]
7.4.27 OPTIMAL_TRIM_UNIT_SIZE [264]
7.4.28 DEVICE_VERSION [263-262]
7.4.29 FIRMWARE_VERSION [261-254]
7.4.30 CACHE_SIZE [252:249]
7.4.31 GENERIC_CMD6_TIME [248]
7.4.32 POWER_OFF_LONG_TIME [247]
7.4.33 BKOPS_STATUS [246]
7.4.34 CORRECTLY_PRG_SECTORS_NUM [245:242]
7.4.35 INI_TIMEOUT_AP [241]
7.4.36 CACHE_FLUSH_POLICY [240]
7.4.37 TRIM_MULT [232]
7.4.38 SEC_FEATURE_SUPPORT [231]
7.4.39 SEC_ERASE_MULT [230]
7.4.40 SEC_TRIM_MULT [229]
7.4.41 BOOT_INFO [228]
7.4.42 BOOT_SIZE_MULT [226]
7.4.43 ACC_SIZE [225]
7.4.44 HC_ERASE_GRP_SIZE [224]
7.4.45 ERASE_TIMEOUT_MULT [223]
7.4.46 REL_WR_SEC_C [222]
7.4.47 HC_WP_GRP_SIZE [221]
7.4.48 S_C_VCC[220] and S_C_VCCQ[219]
7.4.49 PRODUCTION_STATE_AWARENESS_TIMEOUT [218]
7.4.50 S_A_TIMEOUT [217]
7.4.51 SLEEP_NOTIFICATION_TIME [216]
7.4.52 SEC_COUNT [215:212]
7.4.53 SECURE_WP_INFO[211]
7.4.54 MIN_PERF_a_b_ff [210/:205] and MIN_PERF_DDR_a_b_ff [235:234]
7.4.55 PWR_CL_ff_vvv [203:200] , PWR_CL_ff_vvv[237:236] , PWR_CL_DDR_ff_vvv [239:238] and PWR_CL_DDR_ff_vvv[253]
7.4.56 PARTITION_SWITCH_TIME [199]
7.4.57 OUT_OF_INTERRUPT_TIME [198]
7.4.58 DRIVER_STRENGTH [197]
7.4.59 DEVICE_TYPE [196]
7.4.60 CSD_STRUCTURE [194]
7.4.61 EXT_CSD_REV [192]
7.4.62 CMD_SET [191]
7.4.63 CMD_SET_REV [189]
7.4.64 POWER_CLASS [187]
7.4.65 HS_TIMING [185]
7.4.66 STROBE_SUPPORT [184]
7.4.67 BUS_WIDTH [183]
7.4.68 ERASED_MEM_CONT [181]
7.4.69 PARTITION_CONFIG (before BOOT_CONFIG) [179]
7.4.70 BOOT_CONFIG_PROT[178]
7.4.71 BOOT_BUS_CONDITIONS [177]
7.4.72 ERASE_GROUP_DEF [175]
7.4.73 BOOT_WP_STATUS [174]
7.4.74 BOOT_WP [173]
7.4.75 USER_WP [171]
7.4.76 FW_CONFIG [169]
7.4.77 RPMB_SIZE_MULT [168]
7.4.78 WR_REL_SET [167]
7.4.79 WR_REL_PARAM [166]
7.4.80 SANITIZE_START[165]
7.4.81 BKOPS_START [164]
7.4.82 BKOPS_EN [163]
7.4.83 RST_n_FUNCTION [162]
7.4.84 HPI_MGMT [161]
7.4.85 PARTITIONING_SUPPORT [160]
7.4.86 MAX_ENH_SIZE_MULT [159:157]
7.4.87 PARTITIONS_ATTRIBUTE [156]
7.4.88 PARTITION_SETTING_COMPLETED [155]
7.4.89 GP_SIZE_MULT_GP0 - GP_SIZE_MULT_GP3 [154:143]
7.4.90 ENH_SIZE_MULT [142:140]
7.4.91 ENH_START_ADDR [139:136]
7.4.92 SEC_BAD_BLK_MGMNT [134]
7.4.93 PRODUCTION_STATE_AWARENESS [133]
7.4.94 TCASE_SUPPORT [132]
7.4.95 PERIODIC_WAKEUP [131]
7.4.96 PROGRAM_CID_CSD_DDR_SUPPORT [130]
7.4.97 VENDOR_SPECIFIC_FIELD [127:64]
7.4.98 NATIVE_SECTOR_SIZE [63]
7.4.99 USE_NATIVE_SECTOR [62]
7.4.100 DATA_SECTOR_SIZE [61]
7.4.101 INI_TIMEOUT_EMU [60]
7.4.102 CLASS_6_CTRL[59]
7.4.103 DYNCAP_NEEDED [58]
7.4.104 EXCEPTION_EVENTS_CTRL [57:56]
7.4.105 EXCEPTION_EVENTS_STATUS [55:54]
7.4.106 EXT_PARTITIONS_ATTRIBUTE [53:52]
7.4.107 CONTEXT_CONF [51:37]
7.4.108 PACKED_COMMAND_STATUS [36]
7.4.109 PACKED_FAILURE_INDEX [35]
7.4.110 POWER_OFF_NOTIFICATION [34]
7.4.111 CACHE_CTRL [33]
7.4.112 FLUSH_CACHE [32]
7.4.113 BARRIER_CTRL [31]
7.4.114 MODE_CONFIG [30]
7.4.115 MODE_OPERATION_CODES [29]
7.4.116 FFU_STATUS [26]
7.4.117 PRE_LOADING_DATA_SIZE [25-22]
7.4.118 MAX_PRE_LOADING_DATA_SIZE [21-18]
7.4.119 PRODUCT_STATE_AWARENESS_ENABLEMENT [17]
7.4.120 SECURE_REMOVAL_TYPE [16]
7.4.121 CMDQ_MODE_EN [15]
7.5 RCA register
7.6 DSR register
7.7 QSR
7.8 Authenticated Device Configuration Area
7.8.1 Authenticated Device Configuration Area[1] : SECURE_WP_MODE_ENABLE
7.8.2 Authenticated Device Configuration Area[2] : SECURE _WP_MODE_CONFIG
8 Error protection
8.1 Error correction codes (ECC)
8.2 Cyclic redundancy codes (CRC)
8.2.1 CRC7
8.2.2 CRC16
9 e•MMC mechanical standard
10 The e•MMC bus
10.1 Power-up
10.1.1 e•MMC power-up
10.1.2 e•MMC power-up guidelines
10.1.3 e•MMC power cycling
10.2 Programmable Device output driver
10.3 Bus operating conditions
10.3.1 Power supply: e•MMC
10.3.2 Power supply: e2•MMC
10.3.3 Power supply Voltages
10.3.4 Bus signal line load
10.3.5 HS400 reference load
10.4 Overshoot/Undershoot Specification
10.5 Bus signal levels
10.5.1 Open-drain mode bus signal level
10.5.2 Push-pull mode bus signal level— e•MMC
10.5.3 Bus Operating Conditions for HS200 and HS400
10.5.4 Device Output Driver Requirements for HS200 and HS400
10.5.4.1 Driver Types Definition
10.5.4.2 Driver Type-0 AC Characteristics
10.5.4.3 Driver Type-0 Test Circuit
10.5.4.4 Driver Type Selection
10.6 Bus timing
10.6.1 Device interface timings
10.7 Bus timing for DAT signals during 2x data rate operation
10.7.1 Dual data rate interface timings
10.8 Bus Timing Specification in HS200 mode
10.8.1 HS200 Clock Timing
10.8.2 HS200 Device Input Timing
10.8.3 HS200 Device Output Timing
10.9 Temperature Conditions
10.10 Bus Timing Specification in HS400 mode
10.10.1 HS400 Device Input Timing
10.10.2 HS400 Device Output Timing
10.10.3 HS400 Device Command Output Timing
11 e•MMC standard compliance
Annex A (informative) Application Notes
A.1 Device Payload block length and ECC types handling
A.2 Description of method for storing passwords on the Device
A.3 e•MMC macro commands
A.4 Host interface timing
A.5 Handling of passwords
A.5.1 Changing the password
A.5.2 Removal of the password
A.6 High-speed e•MMC bus functions
A.6.1 Bus initialization
A.6.2 Switching to high-speed mode
A.6.3 Changing the data bus width
A.7 Erase-unit size selection flow
A.8 HPI background and one of possible solutions
A.9 Stop transmission timing
A.10 Temperature Conditions per Power Classes (Tcase controlled)
A.11 Handling write protection for each boot area individually
A.12 Field Firmware Update
A.13 Command Queue: Command Flows (Informative)
A.13.1 Queuing a Transaction (CMD44+CMD45)
A.13.2 Checking the Queue Status (SEND_STATUS - CMD13)
A.13.3 Execution of a Queued Task (CMD46/CMD47)
Annex B (Normative) Host Controller Interface for Command Queuing
B.1. Introduction
B.1.1. Background
B.1.2. Overview and Scope
B.1.3. Feature Summary
B.1.4. Outside of Scope
B.1.5. Acronyms and Conventions
B.1.5.1. Acronyms
B.1.5.2. Conventions
B.2. Architecture Overview
B.2.1. Task Issuance: Task Descriptor List / Doorbell Register
B.2.2. Task Processing by Host Hardware
B.2.3. Task Selection and Execution
B.2.4. Task Completion: Interrupts and Interrupt Coalescing
B.2.5. Direct Command (DCMD) Submission
B.2.6. Queue-Barrier (QBR) Tasks
B.2.7. Halt Feature
B.2.8. Error Detection and Recovery
B.3. Data Structures
B.3.1. Task Descriptor for Data Transfer Tasks
B.3.2. Transfer Descriptors
B.3.3. Task Descriptor for Direct-Command (DCMD) Tasks
B.3.4. Task Descriptor for Queue-Barrier Task (QBR)
B.3.5. Task List
B.4. CQE Registers
B.4.1. Register Map
B.4.2. CQBASE+00h: CQVER – Command Queuing Version
B.4.3. CQBASE+04h: CQCAP – Command Queuing Capabilities
B.4.4. CQBASE+08h: CQCFG – Command Queuing Configuration
B.4.5. CQBASE+0Ch: CQCTL – Command Queuing Control
B.4.6. CQBASE+10h: CQIS – Command Queuing Interrupt Status
B.4.7. CQBASE+14h: CQISTE – Command Queuing Interrupt Status Enable
B.4.8. CQBASE+18h: CQISGE – Command Queuing Interrupt Signal Enable
B.4.9. CQBASE+1Ch: CQIC – Interrupt Coalescing
B.4.10. CQBASE+20h: CQTDLBA – Command Queuing Task Descriptor List Base Address
B.4.11. CQBASE+24h: CQTDLBAU – Command Queuing Task Descriptor List Base Address Upper 32 Bits
B.4.12. CQBASE+28h: CQTDBR – Command Queuing Task Doorbell
B.4.13. CQBASE+2Ch: CQTCN – Task Completion Notification
B.4.14. CQBASE+30h: CQDQS – Device Queue Status
B.4.15. CQBASE+34h: CQDPT – Device Pending Tasks
B.4.16. CQBASE+38h: CQTCLR – Task Clear
B.4.17. CQBASE+40h: CQSSC1 – Send Status Configuration 1
B.4.18. CQBASE+44h: CQSSC2 – Send Status Configuration 2
B.4.19. CQBASE+48h: CQCRDCT – Command Response for Direct-Command Task
B.4.20. CQBASE+50h: CQRMEM – Response Mode Error Mask
B.4.21. CQBASE+54h: CQTERRI - Task Error Information
B.4.22. CQBASE+58h: CQCRI – Command Response Index
B.4.23. CQBASE+5Ch: CQCRA – Command Response Argument
B.5. Command Queuing Interrupt in e•MMC Host Controller
B.5.1. Normal Interrupt Status Register (Offset 030h)
B.5.2. Normal Interrupt Status Enable Register (Offset 034h)
B.5.3. Normal Interrupt Signal Enable Register (Offset 038h)
B.6. Theory of Operation (Informative)
B.6.1. Command Queuing Initialization Sequence
B.6.2. Task Issuance Sequence
B.6.3. Task Completion Sequence
B.6.4. Task Discard Sequence (inc. Halting CQE)
B.6.5. Error Detect and Recovery
Annex C (informative) Changes between system specification versions
C.1. Version 4.1, the first version of this standard
C.2. Changes from version 4.1 to 4.2
C.3. Changes from version 4.2 to 4.3
C.4. Changes from version 4.3 to 4.4
C.5. Changes from version 4.4 to 4.41
C.6. Changes from version 4.41 to 4.5
C.7. Changes from version 4.5 to 4.51
C.8. Changes from version 4.51 to 5.0
C.9. Changes from version 5.0 to 5.01
C.10. Changes from version 5.01 to 5.1
Standards Improvement Form
JEDEC
STANDARD
Embedded Multi-Media Card
(e•MMC) Electrical Standard (5.1)
JESD84-B51
(Revision of JESD84-B50.1, July 2014)
FEBRUARY 2015
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
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JEDEC Standard No. 84-B51
EMBEDDED MULTI-MEDIA CARD (e•MMC) 5.1 DEVICE
Contents
Page
Foreword..................................................................................................................................................................... xvi
Introduction ................................................................................................................................................................ xvi
Scope ............................................................................................................................................................... 1
1
Normative reference ........................................................................................................................................ 1
2
3
Terms and definitions ...................................................................................................................................... 1
System Features............................................................................................................................................... 4
4
e•MMC Device and System ............................................................................................................................ 6
5
e•MMC System Overview .............................................................................................................................. 6
5.1
5.2
Memory Addressing ........................................................................................................................................ 6
e•MMC Device Overview ............................................................................................................................... 7
5.3
Bus Protocol .................................................................................................................................................... 8
5.3.1
5.3.2
Bus Speed Modes .......................................................................................................................................... 15
5.3.3 HS200 Bus Speed Mode................................................................................................................................ 15
5.3.4 HS200 System Block Diagram ...................................................................................................................... 16
5.3.5 HS200 Adjustable Sampling Host ................................................................................................................. 16
5.3.6 HS400 Bus Speed Mode................................................................................................................................ 16
5.3.7 HS400 System Block Diagram ...................................................................................................................... 17
e•MMC functional description ...................................................................................................................... 18
6
e•MMC Overview ......................................................................................................................................... 18
6.1
6.2
Partition Management ................................................................................................................................... 19
6.2.1 General .......................................................................................................................................................... 19
6.2.2
Command restrictions.................................................................................................................................... 21
Extended Partitions Attribute ........................................................................................................................ 21
6.2.3
6.2.4
Configure partitions ....................................................................................................................................... 22
6.2.5 Access partitions ........................................................................................................................................... 25
6.3
Boot operation mode ..................................................................................................................................... 25
6.3.1 Device reset to Pre-idle state ......................................................................................................................... 25
Boot partition................................................................................................................................................. 27
6.3.2
6.3.3
Boot operation ............................................................................................................................................... 28
6.3.4 Alternative boot operation ............................................................................................................................. 29
6.3.5 Access to boot partition ................................................................................................................................. 33
Boot bus width and data access configuration ............................................................................................... 33
6.3.6
Boot Partition Write Protection ..................................................................................................................... 34
6.3.7
6.4
Device identification mode ........................................................................................................................... 36
6.4.1 Device reset ................................................................................................................................................... 36
6.4.2 Access mode validation (higher than 2GB of densities) ............................................................................... 37
6.4.3
From busy to ready ........................................................................................................................................ 37
6.4.4 Device identification process ........................................................................................................................ 38
Interrupt mode ............................................................................................................................................... 38
6.5
6.6
Data transfer mode ........................................................................................................................................ 40
6.6.1
Command sets and extended settings ............................................................................................................ 42
6.6.2 High-speed modes selection .......................................................................................................................... 43
Power class selection ..................................................................................................................................... 49
6.6.3
6.6.4
Bus testing procedure .................................................................................................................................... 50
Bus Sampling Tuning Concept ...................................................................................................................... 51
6.6.5
6.6.6
Bus width selection ....................................................................................................................................... 54
6.6.7 Data read ....................................................................................................................................................... 54
6.6.8 Data write ...................................................................................................................................................... 56
6.6.9
Erase 59
6.6.10 TRIM 61
6.6.11 Sanitize .......................................................................................................................................................... 62
-i-
JEDEC Standard No. 84-B51
6.6.12 Discard .......................................................................................................................................................... 62
6.6.13 Secure Erase .................................................................................................................................................. 64
6.6.14 Secure Trim ................................................................................................................................................... 65
6.6.15 Write protect management ............................................................................................................................ 66
6.6.16 Extended Security Protocols Pass Through Commands ................................................................................ 68
6.6.17 Production State Awareness .......................................................................................................................... 69
6.6.18 Field Firmware Update .................................................................................................................................. 72
6.6.19 Device lock/unlock operation ........................................................................................................................ 73
6.6.20 Application-specific commands .................................................................................................................... 76
6.6.21 Sleep (CMD5) ............................................................................................................................................... 77
6.6.22 Replay Protected Memory Block .................................................................................................................. 78
6.6.23 Dual Data Rate mode selection ..................................................................................................................... 92
6.6.24 Dual Data Rate mode operation .................................................................................................................... 92
6.6.25 Background Operations ................................................................................................................................. 93
6.6.26 High Priority Interrupt (HPI) ......................................................................................................................... 94
6.6.27 Context Management .................................................................................................................................... 95
6.6.28 Data Tag Mechanism..................................................................................................................................... 99
6.6.29 Packed Commands ...................................................................................................................................... 100
6.6.30 Exception Events ......................................................................................................................................... 102
6.6.31 Cache ......................................................................................................................................................... 103
6.6.32 Features cross matrix ................................................................................................................................... 105
6.6.33 Dynamic Capacity Management ................................................................................................................. 106
6.6.34 Large sector size .......................................................................................................................................... 107
6.6.35 Real Time Clock Information ...................................................................................................................... 111
6.6.36 Power Off Notification ................................................................................................................................ 112
6.6.37 Cache Enhancement Barrier ........................................................................................................................ 113
6.6.38 Cache Flushing Policy ................................................................................................................................. 114
6.6.39 Command Queuing ..................................................................................................................................... 115
6.6.40 Secure Write Protect Mode ......................................................................................................................... 120
Clock control ............................................................................................................................................... 121
6.7
Error conditions ........................................................................................................................................... 121
6.8
6.8.1
CRC and illegal command .......................................................................................................................... 121
Time-out conditions .................................................................................................................................... 122
6.8.2
Read ahead in multiple block read operation .............................................................................................. 123
6.8.3
Minimum performance ................................................................................................................................ 123
6.9
6.9.1
Speed class definition .................................................................................................................................. 123
6.9.2 Measurement of the performance ................................................................................................................ 124
6.10
Commands ................................................................................................................................................... 124
6.10.1 Command types ........................................................................................................................................... 124
6.10.2 Command format ......................................................................................................................................... 124
6.10.3 Command classes ........................................................................................................................................ 125
6.10.4 Detailed command description .................................................................................................................... 126
Device state transition table ........................................................................................................................ 134
6.11
6.12
Responses .................................................................................................................................................... 136
6.13
Device status ............................................................................................................................................... 138
6.14 Memory array partitioning .......................................................................................................................... 142
6.15
Timings ....................................................................................................................................................... 144
6.15.1 Command and response............................................................................................................................... 144
6.15.2 Data read ..................................................................................................................................................... 146
6.15.3 Data write .................................................................................................................................................... 147
6.15.4 Bus test procedure timing ............................................................................................................................ 151
6.15.5 Boot operation ............................................................................................................................................. 152
6.15.6 Alternative boot operation ........................................................................................................................... 153
6.15.7 Timing Values ............................................................................................................................................. 154
6.15.8 Timing changes in HS200 and HS400 mode ............................................................................................... 155
6.15.9 Enhanced Strobe in HS400 Mode ............................................................................................................... 158
-ii-
JEDEC Standard No. 84-B51
6.15.10 H/W Reset Operation .................................................................................................................................. 159
6.15.11 Noise filtering timing for H/W Reset .......................................................................................................... 159
6.15.12 Additional Timing changes in HS400 mode ............................................................................................... 160
Device Registers .......................................................................................................................................... 161
7
7.1
OCR register ................................................................................................................................................ 161
7.2
CID register ................................................................................................................................................. 162
7.2.1 MID [127:120] ............................................................................................................................................ 162
7.2.2
CBX [113:112] ............................................................................................................................................ 162
7.2.3 OID [111:104] ............................................................................................................................................. 162
7.2.4
PNM [103:56] ............................................................................................................................................. 162
PRV [55:48] ................................................................................................................................................ 162
7.2.5
7.2.6
PSN [47:16] ................................................................................................................................................. 162
7.2.7 MDT [15:8] ................................................................................................................................................. 163
7.2.8
CRC [7:1] .................................................................................................................................................... 163
CSD register ................................................................................................................................................ 163
7.3
CSD_STRUCTURE [127:126] ................................................................................................................... 165
7.3.1
SPEC_VERS [125:122] .............................................................................................................................. 165
7.3.2
7.3.3
TAAC [119:112] ......................................................................................................................................... 165
7.3.4 NSAC [111:104] ......................................................................................................................................... 165
TRAN_SPEED [103:96] ............................................................................................................................. 166
7.3.5
CCC [95:84] ................................................................................................................................................ 166
7.3.6
READ_BL_LEN [83:80] ............................................................................................................................ 166
7.3.7
7.3.8
READ_BL_PARTIAL [79] ........................................................................................................................ 167
7.3.9 WRITE_BLK_MISALIGN [78] ................................................................................................................. 167
7.3.10 READ_BLK_MISALIGN [77] ................................................................................................................... 167
7.3.11 DSR_IMP [76] ............................................................................................................................................ 167
7.3.12 C_SIZE [73:62] ........................................................................................................................................... 168
7.3.13 VDD_R_CURR_MIN [61:59] and VDD_W_CURR_MIN [55:53] ........................................................... 168
7.3.14 VDD_R_CURR_MAX [58:56] and VDD_W_CURR_MAX [52:50] ........................................................ 168
7.3.15 C_SIZE_MULT [49:47] .............................................................................................................................. 169
7.3.16 ERASE_GRP_SIZE [46:42] ....................................................................................................................... 169
7.3.17 ERASE_GRP_MULT [41:37] .................................................................................................................... 169
7.3.18 WP_GRP_SIZE [36:32] .............................................................................................................................. 169
7.3.19 WP_GRP_ENABLE [31] ............................................................................................................................ 169
7.3.20 DEFAULT_ECC [30:29] ............................................................................................................................ 169
7.3.21 R2W_FACTOR [28:26] .............................................................................................................................. 170
7.3.22 WRITE_BL_LEN [25:22] ........................................................................................................................... 170
7.3.23 WRITE_BL_PARTIAL[21] ........................................................................................................................ 170
7.3.24 CONTENT_PROT_APP [16] ..................................................................................................................... 170
7.3.25 FILE_FORMAT_GRP [15] ........................................................................................................................ 170
7.3.26 COPY [14] .................................................................................................................................................. 170
7.3.27 PERM_WRITE_PROTECT [13] ................................................................................................................ 171
7.3.28 TMP_WRITE_PROTECT [12] ................................................................................................................... 171
7.3.29 FILE_FORMAT [11:10] ............................................................................................................................. 171
7.3.30 ECC [9:8] .................................................................................................................................................... 171
7.3.31 CRC [7:1] .................................................................................................................................................... 172
Extended CSD register ................................................................................................................................ 173
7.4
EXT_SECURITY_ERR [505] .................................................................................................................... 178
7.4.1
7.4.2
S_CMD_SET [504] ..................................................................................................................................... 178
7.4.3 HPI_FEATURES [503] ............................................................................................................................... 178
7.4.4
BKOPS_SUPPORT [502] ........................................................................................................................... 179
7.4.5 MAX_PACKED_READS [501] ................................................................................................................. 179
7.4.6 MAX_PACKED_WRITES [500] ............................................................................................................... 179
7.4.7 DATA_TAG_SUPPORT [499]................................................................................................................... 179
TAG_UNIT_SIZE [498] ............................................................................................................................. 179
7.4.8
7.4.9
TAG_RES_SIZE [497] ............................................................................................................................... 179
-iii-
JEDEC Standard No. 84-B51
7.4.10 CONTEXT_CAPABILITIES [496] ............................................................................................................ 180
7.4.11 LARGE_UNIT_SIZE_M1 [495]................................................................................................................. 180
7.4.12 EXT_SUPPORT [494] ................................................................................................................................ 180
7.4.13 SUPPORTED_MODES [493] .................................................................................................................... 180
7.4.14 FFU_FEATURES [492] .............................................................................................................................. 180
7.4.15 OPERATION_CODES_TIMEOUT [491] .................................................................................................. 181
7.4.16 FFU_ARG [490-487] .................................................................................................................................. 181
7.4.17 BARRIER_SUPPORT [486] ...................................................................................................................... 181
7.4.18 CMDQ_SUPPORT [308] ............................................................................................................................ 181
7.4.19 CMDQ_DEPTH [307] ................................................................................................................................ 182
7.4.20 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305-302] ........................................ 182
7.4.21 VENDOR_PROPRIETARY_HEALTH_REPORT [301-270] ................................................................... 182
7.4.22 DEVICE_LIFE_TIME_EST_TYP_B [269] ............................................................................................... 182
7.4.23 DEVICE_LIFE_TIME_EST_TYP_A [268] ............................................................................................... 183
7.4.24 PRE_EOL_INFO [267] ............................................................................................................................... 183
7.4.25 OPTIMAL_READ_SIZE [266] .................................................................................................................. 184
7.4.26 OPTIMAL_WRITE_SIZE [265]................................................................................................................. 184
7.4.27 OPTIMAL_TRIM_UNIT_SIZE [264] ........................................................................................................ 184
7.4.28 DEVICE_VERSION [263-262] .................................................................................................................. 184
7.4.29 FIRMWARE_VERSION [261-254] ........................................................................................................... 185
7.4.30 CACHE_SIZE [252:249] ............................................................................................................................ 185
7.4.31 GENERIC_CMD6_TIME [248] ................................................................................................................. 185
7.4.32 POWER_OFF_LONG_TIME [247] ........................................................................................................... 185
7.4.33 BKOPS_STATUS [246] ............................................................................................................................. 186
7.4.34 CORRECTLY_PRG_SECTORS_NUM [245:242] .................................................................................... 186
7.4.35
INI_TIMEOUT_AP [241] ........................................................................................................................... 186
7.4.36 CACHE_FLUSH_POLICY [240] ............................................................................................................... 187
7.4.37 TRIM_MULT [232] .................................................................................................................................... 187
7.4.38 SEC_FEATURE_SUPPORT [231]............................................................................................................. 188
7.4.39 SEC_ERASE_MULT [230] ........................................................................................................................ 189
7.4.40 SEC_TRIM_MULT [229] ........................................................................................................................... 189
7.4.41 BOOT_INFO [228] ..................................................................................................................................... 190
7.4.42 BOOT_SIZE_MULT [226] ......................................................................................................................... 190
7.4.43 ACC_SIZE [225] ......................................................................................................................................... 191
7.4.44 HC_ERASE_GRP_SIZE [224] ................................................................................................................... 191
7.4.45 ERASE_TIMEOUT_MULT [223] ............................................................................................................. 192
7.4.46 REL_WR_SEC_C [222] ............................................................................................................................. 192
7.4.47 HC_WP_GRP_SIZE [221] .......................................................................................................................... 192
7.4.48 S_C_VCC[220] and S_C_VCCQ[219] ....................................................................................................... 193
7.4.49 PRODUCTION_STATE_AWARENESS_TIMEOUT [218] ..................................................................... 193
7.4.50 S_A_TIMEOUT [217] ................................................................................................................................ 194
7.4.51 SLEEP_NOTIFICATION_TIME [216] ...................................................................................................... 194
7.4.52 SEC_COUNT [215:212] ............................................................................................................................. 194
7.4.53 SECURE_WP_INFO[211] .......................................................................................................................... 195
7.4.54 MIN_PERF_a_b_ff [210/:205] and MIN_PERF_DDR_a_b_ff [235:234] ................................................. 196
7.4.55 PWR_CL_ff_vvv [203:200] , PWR_CL_ff_vvv[237:236] , PWR_CL_DDR_ff_vvv [239:238] and
PWR_CL_DDR_ff_vvv[253] ..................................................................................................................... 196
7.4.56 PARTITION_SWITCH_TIME [199] ......................................................................................................... 198
7.4.57 OUT_OF_INTERRUPT_TIME [198] ........................................................................................................ 198
7.4.58 DRIVER_STRENGTH [197] ...................................................................................................................... 199
7.4.59 DEVICE_TYPE [196] ................................................................................................................................. 200
7.4.60 CSD_STRUCTURE [194] .......................................................................................................................... 200
7.4.61 EXT_CSD_REV [192] ................................................................................................................................ 201
7.4.62 CMD_SET [191] ......................................................................................................................................... 201
7.4.63 CMD_SET_REV [189] ............................................................................................................................... 201
7.4.64 POWER_CLASS [187] ............................................................................................................................... 201
-iv-
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