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主要讲verilog可综合性的coding style，还不错.pdf
Nonblocking Assignments in Verilog Synthesis, Coding
Styles That Kill!
Clifford E. Cummings
Sunburst Design, Inc.
SNUG-2000
San Jose, CA
Voted Best Paper
1st Place
ABSTRACT
One of the most misunderstood constructs in the Verilog language is the nonblocking
assignment. Even very experienced Verilog designers do not fully understand how nonblocking
assignments are scheduled in an IEEE compliant Verilog simulator and do not understand when
and why nonblocking assignments should be used. This paper details how Verilog blocking and
nonblocking assignments are scheduled, gives important coding guidelines to infer correct
synthesizable logic and details coding styles to avoid Verilog simulation race conditions.
1.0 Introduction
Two well known Verilog coding guidelines for modeling logic are:
• Guideline: Use blocking assignments in always blocks that are written to generate
combinational logic [1].
• Guideline: Use nonblocking assignments in always blocks that are written to generate
sequential logic [1].
But why? In general, the answer is simulation related. Ignoring the above guidelines can still
infer the correct synthesized logic, but the pre-synthesis simulation might not match the behavior
of the synthesized circuit.
To understand the reasons behind the above guidelines, one needs to have a full understanding of
the functionality and scheduling of Verilog blocking and nonblocking assignments. This paper
will detail the functionality and scheduling of blocking and nonblocking assignments.
Throughout this paper, the following abbreviations will be used:
RHS - the expression or variable on the right-hand-side of an equation will be abbreviated as
RHS equation, RHS expression or RHS variable.
LHS - the expression or variable on the left-hand-side of an equation will be abbreviated as LHS
equation, LHS expression or LHS variable.
2.0 Verilog race conditions
The IEEE Verilog Standard [2] defines: which statements have a guaranteed order of execution
("Determinism", section 5.4.1), and which statements do not have a guaranteed order of
execution ("Nondeterminism", section 5.4.2 & "Race conditions", section 5.5).
A Verilog race condition occurs when two or more statements that are scheduled to execute in
the same simulation time-step, would give different results when the order of statement execution
is changed, as permitted by the IEEE Verilog Standard.
To avoid race conditions, it is important to understand the scheduling of Verilog blocking and
nonblocking assignments.
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3.0 Blocking assignments
The blocking assignment operator is an equal sign ("="). A blocking assignment gets its name
because a blocking assignment must evaluate the RHS arguments and complete the assignment
without interruption from any other Verilog statement. The assignment is said to "block" other
assignments until the current assignment has completed. The one exception is a blocking
assignment with timing delays on the RHS of the blocking operator, which is considered to be a
poor coding style [3].
Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression)
of the blocking assignment without interruption from any other Verilog statement.
A blocking assignment "blocks" trailing assignments in the same always block from occurring
until after the current assignment has been completed
A problem with blocking assignments occurs when the RHS variable of one assignment in one
procedural block is also the LHS variable of another assignment in another procedural block and
both equations are scheduled to execute in the same simulation time step, such as on the same
clock edge. If blocking assignments are not properly ordered, a race condition can occur. When
blocking assignments are scheduled to execute in the same time step, the order execution is
unknown.
To illustrate this point, look at the Verilog code in Example 1.
module fbosc1 (y1, y2, clk, rst);
output y1, y2;
input clk, rst;
reg y1, y2;
always @(posedge clk or posedge rst)
if (rst) y1 = 0; // reset
else y1 = y2;
always @(posedge clk or posedge rst)
if (rst) y2 = 1; // preset
else y2 = y1;
endmodule
Example 1 - Feedback oscillator with blocking assignments
According to the IEEE Verilog Standard, the two always blocks can be scheduled in any order. If
the first always block executes first after a reset, both y1 and y2 will take on the value of 1. If the
second always block executes first after a reset, both y1 and y2 will take on the value 0. This
clearly represents a Verilog race condition.
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Synthesis, Coding Styles that Kill
4.0 Nonblocking assignments
The nonblocking assignment operator is the same as the less-than-or-equal-to operator ("<="). A
nonblocking assignment gets its name because the assignment evaluates the RHS expression of a
nonblocking statement at the beginning of a time step and schedules the LHS update to take
place at the end of the time step. Between evaluation of the RHS expression and update of the
LHS expression, other Verilog statements can be evaluated and updated and the RHS expression
of other Verilog nonblocking assignments can also be evaluated and LHS updates scheduled. The
nonblocking assignment does not block other Verilog statements from being evaluated.
Execution of nonblocking assignments can be viewed as a two-step process:
1. Evaluate the RHS of nonblocking statements at the beginning of the time step.
2. Update the LHS of nonblocking statements at the end of the time step.
Nonblocking assignments are only made to register data types and are therefore only permitted
inside of procedural blocks, such as initial blocks and always blocks. Nonblocking assignments
are not permitted in continuous assignments.
To illustrate this point, look at the Verilog code in Example 2.
module fbosc2 (y1, y2, clk, rst);
output y1, y2;
input clk, rst;
reg y1, y2;
always @(posedge clk or posedge rst)
if (rst) y1 <= 0; // reset
else y1 <= y2;
always @(posedge clk or posedge rst)
if (rst) y2 <= 1; // preset
else y2 <= y1;
endmodule
Example 2 - Feedback oscillator with nonblocking assignments
Again, according to the IEEE Verilog Standard, the two always blocks can be scheduled in any
order. No matter which always block starts first after a reset, both nonblocking RHS expressions
will be evaluated at the beginning of the time step and then both nonblocking LHS variables will
be updated at the end of the same time step. From a users perspective, the execution of these two
nonblocking statements happen in parallel.
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Nonblocking Assignments In Verilog
Synthesis, Coding Styles that Kill
5.0 Verilog coding guidelines
Before giving further explanation and examples of both blocking and nonblocking assignments,
it would be useful to outline eight guidelines that help to accurately simulate hardware, modeled
using Verilog. Adherence to these guidelines will also remove 90-100% of the Verilog race
conditions encountered by most Verilog designers.
Guideline #1: When modeling sequential logic, use nonblocking assignments.
Guideline #2: When modeling latches, use nonblocking assignments.
Guideline #3: When modeling combinational logic with an always block, use blocking
assignments.
Guideline #4: When modeling both sequential and combinational logic within the same always
block, use nonblocking assignments.
Guideline #5: Do not mix blocking and nonblocking assignments in the same always block.
Guideline #6: Do not make assignments to the same variable from more than one always block.
Guideline #7: Use $strobe to display values that have been assigned using nonblocking
assignments.
Guideline #8: Do not make assignments using #0 delays.
Reasons for these guidelines are given throughout the rest of this paper. Designers new to
Verilog are encouraged to memorize and use these guidelines until their underlying functionality
is fully understood. Following these guidelines will help to avoid "death by Verilog!"
6.0 The Verilog "stratified event queue"
An examination of the Verilog "stratified event queue" (see Figure 1) helps to explain how
Verilog blocking and nonblocking assignments function. The "stratified event queue" is a fancy
name for the different Verilog event queues that are used to schedule simulation events.
The "stratified event queue" as described in the IEEE Verilog Standard is a conceptual model.
Exactly how each vendor implements the event queues is proprietary, helps to determine the
efficiency of each vendor's simulator and is not detailed in this paper.
As defined in section 5.3 of the IEEE 1364-1995 Verilog Standard, the "stratified event queue" is
logically partitioned into four distinct queues for the current simulation time and additional
queues for future simulation times.
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Active Events
Inactive Events
These events may
be scheduled in
any order
Blocking assignments
Evaluate RHS of nonblocking
assignments
Continuous assignments
$display command execution
Evaluate inputs and change
outputs of primitives
#0 blocking assignments
Nonblocking Events
Update LHS of nonblocking assignments
Monitor Events
$monitor command execution
$strobe command execution
Other specific PLI commands
Figure 1 - Verilog "stratified event queue"
The active events queue is where most Verilog events are scheduled, including blocking
assignments, continuous assignments, $display commands, evaluation of instance and primitive
inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking
RHS expressions. The LHS of nonblocking assignments are not updated in the active events
queue.
Events are added to any of the event queues (within restrictions imposed by the IEEE Standard)
but are only removed from the active events queue. Events that are scheduled on the other event
queues will eventually become "activated," or promoted into the active events queue. Section 5.4
of the IEEE 1364-1995 Verilog Standard lists an algorithm that describes when the other event
queues are "activated."
Two other commonly used event queues in the current simulation time are the nonblocking
assign updates event queue and the monitor events queue, which are described below.
The nonblocking assign updates event queue is where updates to the LHS expression of
nonblocking assignments are scheduled. The RHS expression is evaluated in random order at the
beginning of a simulation time step along with the other active events described above.
The monitor events queue is where $strobe and $monitor display command values are scheduled.
$strobe and $monitor show the updated values of all requested variables at the end of a
simulation time step, after all other assignments for that simulation time step are complete.
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A fourth event queue described in section 5.3 of the Verilog Standard is the inactive events
queue, where #0-delayed assignments are scheduled. The practice of making #0-delay
assignments is generally a flawed practice employed by designers who try to make assignments
to the same variable from two separate procedural blocks, attempting to beat Verilog race
conditions by scheduling one of the assignments to take place slightly later in the same
simulation time step. Adding #0-delay assignments to Verilog models needlessly complicates the
analysis of scheduled events. The author knows of no condition that requires making #0-delay
assignments that could not be easily replaced with a different and more efficient coding style and
hence discourages the practice.
Guideline #8: Do not make assignments using #0 delays.
The "stratified event queue" of Figure 1 will be frequently referenced to explain the behavior of
Verilog code examples shown later in this paper. The event queues will also be referenced to
justify the eight coding guidelines given in section 5.0.
7.0 Self-triggering always blocks
In general, a Verilog always block cannot trigger itself. Consider the oscillator example in
Example 3. This oscillator uses blocking assignments. Blocking assignments evaluate their RHS
expression and update their LHS value without interruption. The blocking assignment must
complete before the @(clk) edge-trigger event can be scheduled. By the time the trigger event
has been scheduled, the blocking clk assignment has completed; therefore, there is no trigger
event from within the always block to trigger the @(clk) trigger.
module osc1 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk = ~clk;
endmodule
Example 3 - Non-self-triggering oscillator using blocking assignments
In contrast, the oscillator in Example 4 uses nonblocking assignments. After the first @(clk)
trigger, the RHS expression of the nonblocking assignment is evaluated and the LHS value
scheduled into the nonblocking assign updates event queue. Before the nonblocking assign
updates event queue is "activated," the @(clk) trigger statement is encountered and the always
block again becomes sensitive to changes on the clk signal. When the nonblocking LHS value is
updated later in the same time step, the @(clk) is again triggered. The osc2 example is self-
triggering (which is not necessarily a recommended coding style).
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Synthesis, Coding Styles that Kill
module osc2 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk <= ~clk;
endmodule
Example 4 - Self-triggering oscillator using nonblocking assignments
8.0 Pipeline modeling
Figure 2 shows a block diagram for a simple sequential pipeline register. Example 5 - Example 8
show four different ways that an engineer might choose to model this pipeline using blocking
assignments.
d
q1
q2
q3
clk
Figure 2 - Sequential pipeline register
In the pipeb1, Example 5 code, the sequentially ordered blocking assignments will cause the
input value, d, to be placed on the output of every register on the next posedge clk. On every
clock edge, the input value is transferred directly to the q3-output without delay. This clearly
does not model a pipeline register and will actually synthesize to a single register! (See Figure 3).
module pipeb1 (q3, d, clk);
output [7:0] q3;
input [7:0] d;
input clk;
reg [7:0] q3, q2, q1;
always @(posedge clk) begin
q1 = d;
q2 = q1;
q3 = q2;
end
endmodule
d
q3
clk
Example 5 - Bad blocking-assignment sequential coding style #1
Figure 3 - Actual synthesized result!
In the pipeb2 example, the blocking assignments have been carefully ordered to cause the
simulation to correctly behave like a pipeline register. This model also synthesizes to the pipeline
register shown in Figure 2.
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Nonblocking Assignments In Verilog
Synthesis, Coding Styles that Kill
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