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JESD209-4B_Low Power Double Data Rate 4 (LPDDR4).pdf

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    JESD209-4B
    1 Scope
    2 Package ballout and Pin definition
    2.5 Pad Definition and Description
    3 Functional Description
    3.1 LPDDR4 SDRAM Addressing
    3.2 Simplified LPDDR4 State Diagram
    3.3 Power-up, Initialization and Power-off Procedure
    3.4 Mode Register Definition
    MR0 Register Information
    MR1 Register Information
    MR2 Register Information
    MR3 Register Information
    MR4 Register Information
    MR5 Register Information
    MR6 Register Information
    MR7 Register Information
    MR8 Register Information
    MR11 Register Information (MA[5:0] = 0BH)
    MR12 Register Information
    MR13 Register Information
    MR22 Register Information (MA[5:0] = 16H)
    4 Command Definitions and Timing Diagrams
    4.1 Activate Command
    4.2 8-Bank Device Operation
    4.3 Core Timing
    4.4 Read and Write Access Operations
    4.5 Read Preamble and Postamble
    4.6 Burst Read Operation
    4.7 Read Timing
    4.8 tDQSCK Timing Table
    4.9 Write Preamble and Postamble
    4.10 Burst Write Operation
    4.11 Write Timing
    4.12 Read and Write Latencies
    4.13 Write and Masked Write operation DQS controls (WDQS Control)
    4.14 Postamble and Preamble merging behavior
    4.15 MASKED WRITE OPERATION
    4.16 LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) Function
    4.17 Precharge Operation
    4.18 Auto-Precharge Operation
    4.19 Refresh command
    4.20 Refresh Requirement
    4.21 Self Refresh Operation
    4.21.1 Self Refresh Entry and Exit
    4.21.2 Power Down Entry and Exit during Self Refresh
    4.21.3 Command input Timing after Power Down Exit
    4.22 Self Refresh Abort
    4.23 MRR, MRW, MPC Command during tXSR, tRFC
    4.24 MODE REGISTER READ(MRR)
    4.25 Mode Register Write (MRW) Operation
    4.26 VREF Current Generator (VRCG)
    4.27 CA VREF Training
    4.28 DQ VREF Training
    4.29 Command Bus Training
    4.29.1 Training Sequence for single-rank systems
    4.29.2 Training Sequence for multi-rank systems
    4.30 Frequency Set Point
    4.31 Mode Register Write-WR Leveling Mode
    4.43 On Die Termination for Command/Address Bus
    4.44 On-Die Termination
    4.45 On Die Termination for DQ, DQS and DMI
    4.48 Power-Down Mode
    4.49 Input Clock Stop and Frequency Change
    4.50.1 Command Truth Table
    5 Absolute Maximum DC Ratings
    6 AC and DC Operating Conditions
    7 AC and DC Input/Output Measurement levels
    8 Input/Output Capacitance
    9 IDD Specification Parameters and Test Conditions
    10 Electrical Characteristics and AC Timing
    Annex A Differences Between Revisions
    Standards Improvement Form
    JEDEC STANDARD Low Power Double Date Rate 4 (LPDDR4) JESD209-4B (Revision of JESD209-4A, November 2015) FEBRUARY 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
    NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. ©JEDEC Solid State Technology Association 2017 Published by 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved
    PLEASE! DON’T VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information.
    JEDEC Standard No. 209-4B Page 1 LOW POWER DOUBLE DATA RATE (LPDDR) 4 From JEDEC Board Ballot JCB-16-51, formulated under the cognizance of the JC-42.6 Subcommittee on Low Power Memories.) 1 Scope This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3). Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the LPDDR4 standard.
    2 Package ballout and Pin definition JEDEC Standard No. 209-4B Page 2 Pad Order 141 VDD2 142 CKE_B 143 CS_B 144 VSS 145 CA1_B 146 CA0_B 147 VDD2 148 ODT(ca)_B 149 VSS 150 VDD1 151 VSSQ 152 DQ7_B 153 VDDQ 154 DQ6_B 155 VSSQ 156 DQ5_B 157 VDDQ 158 DQ4_B 159 VSSQ 160 DMI0_B 161 VDDQ 162 DQS0_c_B 163 DQS0_t_B 164 VSSQ 165 DQ3_B 166 VDDQ 167 DQ2_B 168 VSSQ 169 DQ1_B 170 VDDQ 171 DQ0_B 172 VSSQ 173 VSS 174 VDD2 175 VDD1 176 VSS 177 VDD2 Ch. B Bottom 2.1 2.1.1 Pad Order for dual channel Ch. A Top 1 VDD2 2 VSS 3 VDD1 4 VDD2 5 VSS 6 VSSQ 7 DQ8_A 8 VDDQ 9 DQ9_A 10 VSSQ 11 DQ10_A 12 VDDQ 13 DQ11_A 14 VSSQ 15 DQS1_t_A 16 DQS1_c_A 17 VDDQ 18 DMI1_A 19 VSSQ 20 DQ12_A 21 VDDQ 22 DQ13_A 23 VSSQ 24 DQ14_A 25 VDDQ 26 DQ15_A 27 VSSQ 28 ZQ 29 VDDQ 30 VDD2 31 VDD1 32 VSS 33 CA5_A 34 CA4_A 35 VDD2 36 CA3_A 37 CA2_A 38 VSS 39 CK_c_A 40 CK_t_A NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes. Ch. B Top 101 VDD2 102 VSS 103 VDD1 104 VDD2 105 VSS 106 VSSQ 107 DQ8_B 108 VDDQ 109 DQ9_B 110 VSSQ 111 DQ10_B 112 VDDQ 113 DQ11_B 114 VSSQ 115 DQS1_t_B 116 DQS1_c_B 117 VDDQ 118 DMI1_B 119 VSSQ 120 DQ12_B 121 VDDQ 122 DQ13_B 123 VSSQ 124 DQ14_B 125 VDDQ 126 DQ15_B 127 VSSQ 128 RESET_n 129 VDDQ 130 VDD2 131 VDD1 132 VSS 133 CA5_B 134 CA4_B 135 VDD2 136 CA3_B 137 CA2_B 138 VSS 139 CK_c_B 140 CK_t_B 41 VDD2 42 CKE_A 43 CS_A 44 VSS 45 CA1_A 46 CA0_A 47 VDD2 48 ODT(ca)_A 49 VSS 50 VDD1 51 VSSQ 52 DQ7_A 53 VDDQ 54 DQ6_A 55 VSSQ 56 DQ5_A 57 VDDQ 58 DQ4_A 59 VSSQ 60 DMI0_A 61 VDDQ 62 DQS0_c_A 63 DQS0_t_A 64 VSSQ 65 DQ3_A 66 VDDQ 67 DQ2_A 68 VSSQ 69 DQ1_A 70 VDDQ 71 DQ0_A 72 VSSQ 73 VSS 74 VDD2 75 VDD1 76 VSS 77 VDD2 Ch. A Bottom NOTE 2 Additional pads are allowed for DRAM mfg-specific pads (“DNU”), or additional power pads as long as the extra pads are grouped with like-named pads.
    Pad Order (cont’d) 2.1 2.1.2 Pad Order for single channel JEDEC Standard No. 209-4B Page 3 VDDQ VDD2 VSS VDD1 VDD2 VSS VSSQ TOP 1 2 3 4 5 6 7 DQ8 8 9 DQ9 10 VSSQ 11 DQ10 12 VDDQ 13 DQ11 14 VSSQ 15 DQS1_t 16 DQS1_c 17 VDDQ 18 DMI1 19 VSSQ 20 DQ12 21 VDDQ 22 DQ13 23 VSSQ 24 DQ14 25 VDDQ 26 DQ15 27 VSSQ 28 ZQ 29 VDDQ 30 VDD2 31 RESET_n 32 VDD1 33 VSS 34 CA5 35 CA4 36 VDD2 37 CA3 38 CA2 39 VSS 40 CK_c 41 CK_t 42 VDD2 43 CKE 44 CS 45 VSS 46 CA1 47 CA0 48 VDD2 49 ODT(ca) 50 VSS 51 VDD1 52 VSSQ 53 DQ7 54 VDDQ 55 DQ6 56 VSSQ 57 DQ5 58 VDDQ 59 DQ4 60 VSSQ 61 DMI0 62 VDDQ 63 DQS0_c 64 DQS0_t 65 VSSQ 66 DQ3 67 VDDQ 68 DQ2 69 VSSQ 70 DQ1 71 VDDQ 72 DQ0 73 VSSQ 74 VSS 75 VDD2 76 VDD1 77 VSS 78 VDD2 Bottom NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes. NOTE 2 Additional pads are allowed for DRAM mfg-specific pads (“DNU”), or additional power pads as long as the extra pads are grouped with like-named pads. NOTE 3 A RESET_n pad is added. The RESET_n pad location is vendor specific. See vendor device datasheets for details about RESET_n pad location.
    2.2 2.2.1 1 2 Package Ballout 272 ball 15 mm x 15 mm 0.4 mm pitch, Quad-Channel POP FBGA (top view) Using Variation VFFCDB for MO-273 35 12 11 10 17 18 19 23 24 26 27 28 33 34 30 13 21 22 25 32 15 31 14 16 20 29 6 7 8 9 3 4 5 36 DNU VSS P a g e 4 t J E D E C S a n d a r d N o . 2 0 9 - 4 B VSS VSS VSS VSS VSS VSS VSS DNU VDD2 VDD1 VDDQ VDDQ CS1_a CA0_a CS0_a DQ0_a DQ2_a DQ7_a DQ4_a DQ6_a CK_t_a DMI0_a CK_c_a ODTca_a A B C CA2_a D VDD2 E CKE0_a F CKE1_a G VDD2 H CA1_a J K L M DQ5_a N VDDQ P DQS0_c_a R DQ3_a DQS0_t_a T U DQ1_a V W DQ0_b Y DQ1_b AA VDDQ AB DQ3_b DQS0_t_b AC DQS0_c_b AD VDDQ AE DQ5_b AF DQ6_b AG VDDQ AH CA0_b AJ AK VDD2 AL CKE1_b AM CKE0_b AN VDD2 AP CA2_b AR VSS AT ODTca_b CK_c_b DMI0_b CK_t_b DQ4_b DQ2_b DQ7_b CS0_b CA1_b CS1_b VDD2 VDD2 DNU VSS VSS VSS VSS VSS VSS VDD1 CA4_a VDDQ ZQ1_a VDDQ DQ15_a VDD2 DQ13_a VDD2 DMI1_a VDDQ DQS1_c_a VDDQ DQ10_a VSS DQ8_a DQ0_c VDD1 DQ2_c VDDQ DQS0_c_c VDDQ DQ4_c VDD2 DQ5_c VDD2 DQ7_c VDDQ CA0_c VDDQ CS1_c VDD1 VSS CA3_a VSS CA5_a VSS ZQ0_a VSS DQ14_a VSS DQ12_a VSS DQS1_t_a VSS DQ11_a VSS DQ9_a VDD2 VSS DQ1_c VSS DQ3_c VSS DQS0_t_c VSS DMI0_c VSS DQ6_c VSS ODTca_c VSS CA1_c VSS CS0_c VDD2 VDD1 VDD2 VDDQ VSS CK_t, CK_c DMI DQ, CA, CS, DNU, NC DQS_t, DQS_c RESET_n, ZQ, NOTE 1 15 mm x 15 mm, 0.4 mm pitch. NOTE 2 272 ball count, 36 rows. NOTE 3 Top View, A1 in top left corner. NOTE 4 ODT(ca)_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if present) are disabled in the package. NOTE 5 Package Channel a and Channel c shall be assigned to die Channel A of different DRAM die. NOTE 6 Die pad VSS and VSSQ signals are combined to VSS package balls. NOTE 7 Package requires dual channel die or functional equivalent of single channel die-stack. CKE0_c CKE1_c CK_t_c VDD2 VSS CK_c_c CA2_c CA3_c CA4_c VDD2 VSS CA5_c ZQ0_c ZQ1_c DQ15_c VDDQ VSS DQ14_c DQ12_c DQ13_c DMI1_c VDDQ VSS DQS1_c_c DQS1_t_c DQ11_c DQ10_c VDDQ VSS DQ9_c DQ8_c VDD1 VDD2 DQ8_d VSS DQ9_d DQ10_d VDDQ DQS1_t_d DQ11_d VSS DQS1_c_d DMI1_d VDDQ DQ12_d DQ13_d VSS DQ14_d DQ15_d VDDQ NC NC VSS CA5_d CA4_d VDD2 CA2_d CA3_d VSS CK_c_d CK_t_d VDD2 CKE0_d CKE1_d CA3_b VSS CA5_b VDD1 CA4_b VDDQ VSS RESET_n VSS DQ14_b VSS DMI1_b VSS DQS1_t_b VSS DQ11_b VSS DQ9_b VDD2 VSS DQ1_d VSS DQ3_d VSS DQS0_t_d VSS DQ4_d VSS DQ6_d VSS ODTca_d VSS CA1_d VSS CS0_d VDD2 NC VDDQ DQ15_b VDD2 DQ13_b VDD2 DQ12_b VDDQ DQS1_c_b VDDQ DQ10_b VSS DQ8_b DQ0_d VDD1 DQ2_d VDDQ DQS0_c_d VDDQ DMI0_d VDD2 DQ5_d VDD2 DQ7_d VDDQ CA0_d VDDQ CS1_d VDD1 VSS VSS DNU
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