verilog and systemverilog 101 gotchas.pdf

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Title Page

Dedication

About the Authors

Acknowledgments

Table of Contents

List of Gotchas

Foreword by Steve Golson

Chapter 1 Introduction, What Is A Gotcha?

What are Verilog and System Verilog?

What is a Gotcha?

The Verilog and System Verilog standards

Chapter 2 Declaration and Literal Number Gotchas

Gotcha 1: Case sensitivity

Gotcha 2: Implicit net declarations

Gotcba 3: Default of 1-bit internal nets

Gotcha 4: Single file versus multi-file compilation of $unit declarations

Gotcha 5: Local variable declarations

Gotcha 6: Escaped names in hierarchical paths

Gotcha 7: Hierarchical references to automatic variables

Gotcha 8: Hierarchical references to variables in unnamed blocks

Gotcha 9: Hierarchical references to imported package items

Gotcha 10: Importing enumerated types from packages

Gotcha 11: Importing from multiple packages

Gotcha 12: Default base of literal integers

Gotcha 13: Signedness of literal integers

Gotcha 14: Signed literal integers zero extend to their specified size

Gotcha 15: Literal integersize mismatch in assignments

Gotcha 16: Filling vectors with all ones

Gotcha 17: Array literals versus concatenations

Gotcha 18: Port connection rules

Gotcha 19: Back-driven ports

Gotcha 20: Passing real (floating point) numbers through ports

Chapter 3 RTL Modeling Gotchas

Gotcha 21: Combinational logic sensitivity lists with function calls

Gotcha 22: Arrays in sensitivity lists

Gotcha 23: Vectors in sequential logic sensitivity lists

Gotcha 24: Operations in sensitivity lists

Gotcha 25: Sequential logic blocks with begin...end groups

Gotcha 26: Sequential logic blocks with resets

Gotcha 27: Asynchronous set/reset flip-flop for simulation and synthesis

Gotcha 28: Blocking assignments in sequential procedural blocks

Gotcha 29: Sequential logic that requires blocking assignments

Gotcha 30: Nonblocking assignments in combinational logic

Gotcha 31: Combinational logic assignments in the wrong order

Gotcha 32: Casez/casex masks in case expressions

Gotcha 33: Incomplete decision statements

Gotcha 34: Overlapped decision statements

Gotcha 35: Inappropriate use of unique case statements

Gotcha 36: Resetting 2-state models

Gotcha 37: Locked state machines modeled with enumerated types

Gotcha 38: Hidden design problems with 4-state logic

Gotcha 39: Hidden design problems using 2-state types

Gotcha 40: Hidden problems with out-or-bounds array access

Gotcha 41: Out-or-bounds assignments to enumerated types

Gotcha 42: Undetected shared variables in modules

Gotcha 43: Undetected shared variables in interfaces and packages

Chapter 4 Operator Gotchas

Gotcha 44: Assignments in expressions

Gotcha 45: Self-determined versus context-determined operators

Gotcha 46: Operation size and sign extension in assignment statements

Gotcha 47: Signed arithmetic rules

Gotcha 48: Bit-select and part-select operations

Gotcha 49: Increment, decrement and assignment operators

Gotcha 50: Pre-increment versus post-increment operations

Gotcha 51: Modifying a variable multiple times in onestatement

Gotcha 52: Operator evaluation short circuiting

Gotcha 53: The not operator ( ! ) versus the invert operator ( ~ )

Gotcha 54: Array method operations

Gotcha 55: Array method operations on an array subset

Chapter 5 General Programming Gotchas

Gotcha 56: Verifying asynchronous and synchronous reset at time zero

Gotcha 57: Nested if ...else blocks

Gotcha 58: Evaluation of equality with 4-state values

Gotcha 59: Event trigger race conditions

Gotcha 60: Using semaphores for synchronization

Gotcha 61: Using mailboxes for synchronization

Gotcha 62: Triggering on clocking blocks

Gotcha 63: Misplaced semicolons after decision statements

Gotcha 64: Misplaced semicolons in for loops

Gotcha 65: Infinite for loops

Gotcha 66: Locked simulation due to concurrent for loops

Gotcha 67: Referencing for loop control variables

Gotcha 68: Default function return size

Gotcha 69: Task/function arguments with default values

Gotcha 70: Continuous assignments with delays cancel glitches

Chapter 6 Object Oriented and Multi-Threaded Programming Gotchas

Gotcha 71: Programming statements in a class

Gotcha 72: Using interfaces with object-oriented testbenches

Gotcha 73: All objects in mailbox come out with the same values

Gotcha 74: Passing handles to methods using input versus ref arguments

Gotcha 75: Constructing an array of objects

Gotcha 76: Static tasks and functions are not re-entrant

Gotcha 77: Static versus automatic variable initialization

Gotcha 78: Forked programming threads need automatic variables

Gotcha 79: Disable fork kills too many threads

Gotcha 80: Disabling a statement block stops more than intended

Gotcha 81: Simulation exits prematurely, before tests complete

Chapter 7 Randomization, Coverage and Assertion Gotchas

Gotcha 82: Variables declared with rand are not getting randomized

Gotcha 83: Undetected randomization failures

Gotcha 84: $assertoff could disable randomization

Gotcha 85: Boolean constraints on more than two random variables

Gotcha 86: Unwanted negative values in random values

Gotcha 87: Coverage reports default to groups, not bins

Gotcha 88: Coverage is always reported as 0%

Gotcha 89: The coverage report lumps all instances together

Gotcha 90: Covergroup argument directions are sticky

Gotcha 91: Assertion pass statements execute with a vacuous success

Gotcha 92: Concurrent assertions in procedural blocks

Gotcha 93: Mismatch in assert...else statements

Gotcha 94: Assertions that cannot fail

Chapter 8 Tool Compatibility Gotchas

Gotcha 95: Default simulation time units and precision

Gotcha 96: Package chaining

Gotcha 97: Random number generator is not consistent across tools

Gotcha 98: Loading memories modeled with aIways_latch/always_ff

Gotcha 99: Non-standard language extensions

Gotcha 100: Array literals versus concatenations

Gotcha 101: Module ports that pass floating point values (real types)

Index

Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them

Stuart Sutherland Don Mills Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them ~ Springer

StuartSutherland Sutherland HDL, Inc. Tualatin, OR USA Don Mills LCDM Engineering Chandler, AZ USA Libraryof CongressControlNumber: 2007926706 ISBN978-0-387-71714-2 e-ISBN978-0-387-71715-9 Printedon acid-freepaper. © 2007SpringerScience+Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the writtenpermissionof the publisher(SpringerScience-BusinessMedia,LLC, 233 Spring Street,New York, NY 10013,USA),except for brief excerptsin connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now know or hereafter developed is forbidden. The use in this publication of trade names, trademarks, servicemarks and similarterms, even if they are not identifiedas such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. 9 8 7 6 5 432 1 springer.com

Dedication To my wonderful wife, LeeAnn, and my children, Ammon, Tamara, Hannah, Sethand Samuel- you toleratedwhile this bookwas beingwritten. thankyoufor yourpatienceduringthe many longhoursand late nights Stu Sutherland Portland, Oregon To my wife and sweetheart GeriJean, and my children, Sara, Kirsten, Adam, Alex, Dillan, Donnelle, Grantand Gina- thanks to each ofyoufor thepatienceyou have had withme as I havedealtwithdebugging manyofthesegotchason designs overthe years. Don Mills Chandler, Arizona

About the Authors Mr. Stuart Sutherland is a member of the IEEE 1800 working group that oversees both the Verilog and SystemVerilog standards. He has been involved with the definition of the Verilog standard since its inception in 1993, and the SystemVerilog standard since work began in 200I. In addition, Stuart is the technical editor of the official IEEE Verilog and SystemVerilog Language Reference Manuals (LRMs). Stuart is an independent Verilog consultant, specializing in providing comprehensive expert training on the Verilog HDL, SystemVerilog and PLI. Stuart is a co-authorof the books "SystemVerilog for Design", "Verilog-2001: A Guide to the New Features in the Verilog Hardware Description Language" and is the author of "The Verilog PLl Handbook", as well as the popular "Verilog HDL Quick Reference Guide" and"Verilog PLl QuickReference Guide". He has also authored a number of technical papers on Verilog and SystemVerilog, which are available at www.sutherland-hdl.com/papers. You can contact Stuart at stuart@sutherland-hdl.com. visitthe authorswebpage at www.sutherland-hdl.com Mr. Don Mills has been involved in ASIC design since 1986. During that time, he has worked on morethan 30 ASIC projects. Don started using top-down design methodology in 1991 (Synopsys Design Compiler 1.2). Don has developed and implemented top-down ASIC design flows at several companies. His specialty is integrating tools and automating the flow. Don works as an internal SystemVerilog and Verilog consultant. Don is a member of the IEEE Verilog and System Verilog committees that are working on language issues and enhancements. Don has authored and co-authored numerous papers, such as "SystemVerilog Assertions are for Design Engineers Too!" and "RTL Coding Styles that Yield Simulation and Synthesis Mismatches". Copies of these papers can be found at www.lcdm-eng.com.Mr. Mills can be reached at mills@lcdm-eng.comor don.mills@microchip.com. for Microchip Technology Inc. visit the authorswebpage at www.lcdm-eng.com

Acknowledgments The authors express their sincere appreciation to the contributions of several Verilog and SystemVerilog experts. Chris Spear of Synopsys, Inc. suggested several of the verification related gotchas, provided the general descriptions of these gotchas, and ran countless testsforus. Shalom Bresticker of Intelalsosuggested several gotchas. Jonathan Bromley of Doulos, Ltd., Clifford Cummings of Sunburst Design, Tom Fitzpatrick of Mentor Graphics, Steve Golson of Trilobyte Systems, Gregg Lahti of Microchip Technology, Inc. and Chris Spear of Synopsys, Inc. provided thorough technical reviews of this book, and offered invaluable comments on how to improve the gotcha descriptions. Steve Golson of Trilobyte Systems provided a wonderful foreword to thisbook Lastly, we acknowledge and express our gratitude to our wives, LeeAnn Sutherland and Geri Jean Mills, for meticulously reviewing this book for grammar and punctuation. If any sucherrataremain in the book, it could onlybe due to changes we madeaftertheirreviews.

Table ofContents List of Gotchas...•••.••..•....•••....•..•.•..•..••.....•...••..•.........••................•..•.........•..•.............•..... xv Foreword by SteveGolson...••..•.......••...•......................•.....•...................•.................•..••................•.•.•. 1 Chapter 1: Introduction, What Is A Gotcha? Implicitnet declarations Chapter 2: Declaration and Literal Number Gotchas Gotcha 1: Case sensitivity Gotcha 2: Gotcha 3: Default of l-bit internal nets Gotcha 4: Single file versus multi-file compilation of $unit declarations Gotcha 5: Local variable declarations Gotcha 6: Escapednames in hierarchical paths Gotcha 7: Hierarchical references to automatic variables Gotcha 8: Hierarchical references to variables in unnamedblocks Gotcha9: Hierarchical references to importedpackage items Gotcha 10: Importingenumerated types from packages Gotcha 11: Importing from multiplepackages Gotcha 12: Default base of literal integers Gotcha 13: Signedness of literal integers Gotcha 14: Signed literal integerszero extend to their specifiedsize Gotcha 15: Literal integer size mismatch in assignments Gotcha 16: Filling vectors with all ones Gotcha 17: Array literals versus concatenations Gotcha 18: Port connectionrules Gotcha 19: Back-driven ports 3 7 7 10 13 15 17 19 22 25 27 28 29 30 32 33 35 37 38 39 43

Table of Contents Gotcha 20: Passing real (floating point)numbers through ports Chapter 3: RTL Modeling Gotchas Gotcha21: Combinational logicsensitivity listswith function calls Gotcha22: Arraysin sensitivity lists Gotcha23: Vectors in sequential logic sensitivity lists Gotcha24: Operations in sensitivity lists Gotcha25: Sequential logicblocks with begin end groups Gotcha26: Sequential logicblockswith resets Gotcha 27: Asynchronous set/reset flip-flop for simulation and synthesis Gotcha28: Blocking assignments in sequential procedural blocks Gotcha29: Sequential logicthat requires blocking assignments Gotcha30: Nonblocking assignments in combinational logic Gotcha31: Combinational logicassignments in the wrongorder Gotcha32: Casez/casex masksin case expressions Gotcha33: Incomplete decision statements Gotcha34: Overlapped decision statements Gotcha35: Inappropriate use of unique case statements Gotcha36: Resetting 2-statemodels Gotcha 37: Lockedstate machines modeled with enumerated types Gotcha38: Hidden design problems with 4-statelogic Gotcha39: Hiddendesign problems using2-statetypes Gotcha40: Hidden problems with out-of-bounds arrayaccess Gotcha 41: Out-of-bounds assignments to enumerated types Gotcha 42: Undetected sharedvariables in modules Gotcha43: Undetected sharedvariables in interfaces and packages Chapter 4: Operator Gotchas Gotcha 44: Assignments in expressions Gotcha 45: Self-determined versuscontext-determined operators Gotcha46: Operation size and sign extension in assignment statements Gotcha47: Signedarithmetic rules xii 46 49 49 52 54 56 57 59 60 62 64 66 70 72 74 77 79 82 84 86 88 90 92 94 96 99 99 101 105 108

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