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MIT Computation structures.pdf

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    Computation Structures (ISBN:0262231395)
    Front Matter
    cover
    Copyright
    Contents
    Preface
    1 The Digital Abstraction
    1.1 Information and the Digital Abstraction
    1.2 Representation of Discrete Variables
    1.3 Combinational Devices
    1.4 The Static Discipline: Logic Levels
    1.5 Rate of Information Flow
    1.6 Transitions and Validity
    1.7 Logic Families
    1.8 DigitalCircuit Implementation
    1.9 Summary
    1.10 Context
    1.11 Problems
    2 Binary Representations and Notation
    2.1 Representation of Numbers
    2.2 FloatingPoint Representations
    2.3 Other Representations
    2.4 HeXadecimal Notation
    2.5 *Unrepresentable Values
    2.6 Error Detection and Correction
    2.7 Context
    2.8 Problems
    3 Combinational Devices and Circuits
    3.1 Boolean Functions and Truth Tables
    3.2 Elementary Gate Circuits
    3.3 Synthesis of Logic Circuits
    3.4 Temporal Considerations in Combinational Circuits
    3.5 Context
    3.6 Problems
    4 Sequences and State
    4.1 Feedback and State
    4.2 Latches, FlipFlops, and Registers
    4.3 Edge-Triggered Flip-Flops and Registers
    4.4 Register Timing
    4.5 Models of Sequential Circuits
    4.6 Synchronization and State
    4.7 Context
    4.8 Problems
    5 Synthesis of Digital Systems
    5.1 Building Blocks for Logic Design
    5.2 Regular Structures
    5.3 Design Example: A Combinational Multiplier
    5.4 Context
    5.5 Problems
    6 FiniteState Machines
    6.1 Synthesis of FiniteState Machines
    6.2 Synchronous FSM Circuit Models
    6.3 States and Bits
    6.4 *Equivalence of FSMs
    6.5 *Regular Expressions and Nondeterministic FSMs
    6.6 Context
    6.7 Problems
    7 Control Structures and Disciplines
    7.1 Timing Disciplines
    7.2 Degrees of Synchrony
    7.3 Constraints on Control Structure
    7.4 Synchronous GloballyTimed Control
    7.5 Synchronous Locally Timed Control
    7.6 Asynchronous Locally Timed Control
    7.7 Context
    7.8 Problems
    8 Performance Measures and Trade-offs
    8.1 Pipelining
    8.2 Systematic Pipeline Construction
    8.3 Cost-Performance Trade-offs and Options
    8.4 Implementations of Bubble Sort
    8.5 More Efficient Sorting Algorithms
    8.6 Summary
    8.7 Context
    8.8 Problems
    9 Communication: Issues and Structures
    9.1 Physical Limits and Constraints
    9.2 Communication Buses
    9.3 Serial Communication
    9.4 Context
    9.5 Problems
    10 Interpretation
    10.1 Turing Machines and Computability
    10.2 Universality
    10.3 Uncomputable Functions
    10.4 Interpretation versus Compilation
    10.5 Context
    10.6 Problems
    11 Microinterpreter Architecture
    11.1 Data Paths versus Control
    11.2 A Basic Data-Path Architecture
    11.3 Typical Data-Path Subsystems and Uses
    11.4 Control Subsystem
    11.5 The Control Machine as an Interpreter
    11.6 Context
    11.7 Problems
    12 Microprogramming and Microcode
    12.1 Microcode Semantics
    12.2 Symbolic Microprogramming
    12.3 Microcoding Examples
    12.4 Summary
    12.5 Context
    12.6 Problems
    13 Single-Sequence Machines
    13.1 Machine Language as an Abstraction
    13.2 Gross Organization of the Single-Sequence Machine
    13.3 Influences on Machine-Language Design
    13.4 Implementation Considerations
    13.5 The von Neumann Machine
    13.6 Perspectives and Trends
    13.7 Context
    13.8 Problems
    14 Stack Architectures: The S Machine
    14.1 Basic Instructions
    14.2 S-Machine Instruction Coding
    14.3 *MAYBE Implementation
    14.4 Compilation Techniques for Stack Machines
    14.5 Flow of Control on the S Machine
    14.6 *Relative Addressing and Position-Independent Code
    14.7 Stack Frames and Procedure Linkage
    14.8 *LexicalScoping Support
    14.9 Traps
    14.10 Summary
    14.11 Context
    14.12 Problems
    15 Register Architectures: The G Machine
    15.1 Addressing Modes
    15.2 The G Machine
    15.3 *MAYBE Implementation
    15.4 Other GeneralRegister Architectures
    15.5 Procedure Linkage
    15.6 Register Allocation by Compilers
    15.7 Traps
    15.8 High-Performance Implementation Considerations
    15.9 Summary
    15.10 Context
    15.11 Problems
    16 Memory Architectures
    16.1 Locality of Reference and Other Regularities of Memory Access
    16.2 Interleaved Memory Modules
    16.3 Instruction Prefetch
    16.4 Top-of-Stack Cache
    16.5 Multilevel Memory
    16.6 Cache Memory
    16.7 Paging and Virtual Memory
    16.8 Summary
    16.9 Context
    16.10 Problems
    17 ReducedInstructionSet Computers
    17.1 Basic Data Pipeline
    17.2 Pipeline Timing
    17.3 Interface Issues
    17.4 Instruction-Stream Constants
    17.5 Instruction Fetch and Branch Control
    17.6 Main-Memory Timing Conflict
    17.7 Impact of Lengthened Pipeline
    17.8 Alternatives and Issues
    17.9 Summary
    17.10 Context
    17.11 Problems
    18 Processes and Processor Multiplexing
    18.1 The Process Abstraction
    18.2 Process Management
    18.3 Operating-System Services
    18.4 Memory Mapping
    18.5 Protection
    18.6 Summary
    18.7 Context
    18.8 Problems
    19 Process Synchronization
    19.1 ProcessSynchronization Constraints
    19.2 Semaphores and Precedence Constraints
    19.3 Semaphores for Precedence
    19.4 Semaphores for Mutual Exclusion
    19.5 Producer-Consumer Synchronization
    19.6 Binary Semaphores
    19.7 Implementing Semaphores
    19.8 Deadlock
    19.9 Summary
    19.10 Context
    19.11 Problems
    20 Interrupts, Priorities, and Real Time
    20.1 Mutual-Exclusion Requirements
    20.2 Enable/Disable Mechanism
    20.3 Interrupts and Stack Discipline
    20.4 Implementation of Interrupts
    20.5 Weak Priorities
    20.6 Processor Priorities
    20.7 Scheduling and Priority Assignments
    20.8 Summary
    20.9 Context
    20.10 Problems
    21 Architectural Horizons
    21.1 Models of Computation
    21.2 The Multiprocessor Challenge
    21.3 Taxonomy of Multiprocessors
    21.4 Hiding Parallelism: Concurrent SSM EXecution
    21.5 Data Parallelism
    21.6 Other SIMD Approaches
    21.7 SharedMemory Multiprocessors
    21.8 Distribution of Subcomputations
    21.9 Summary
    21.10 Context
    A1 The C Language: A Brief Overview
    A1.1 Simple Data Types and Declarations
    A1.2 Expressions
    A1.3 Statements and Programs
    A1.4 Arrays and Pointers
    A1.5 Structures
    A2 MAYBE Microarchitecture Summary
    A2.1 Control-ROM Bit Fields
    A2.2 Circuit Details
    A2.3 Microinstruction Set
    A2.4 Control-ROM Listing
    A2.5 Macro Definitions for Microinstructions
    A3 MAYBE Microcode Support for Interpreters
    A3.1 Switch Console
    A3.2 Microsubroutines
    A4 S Machine Summary
    A4.1 Instruction-Set Details
    A4.2 Language Definition
    A4.3 Sample S-Machine Program
    A4.4 Complete MAYBE S-Machine Microcode
    A5 G Machine Summary
    A5.1 Instruction-Set Details
    A5.2 Language Definition
    A5.3 Sample G-Machine Program
    A5.4 Complete MAYBE G-Machine Microcode
    Bibliography
    Index
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