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SATA Storage
Technology
MINDSHARE, INC.
Donovan (Don) Anderson
Contributions by:
Mike Jackson
Duncan Penman
MINDSHARE PRESS
The authors and publishers have taken care in preparation of this book, but make no
expressed or implied warranty of any kind and assume no responsibility for errors or
omissions. No liability is assumed for incidental or consequential damages in connec-
tion with or arising out of the use of the information or programs contained herein.
Visit MindShare, Inc. on the web: www.mindshare.com
Library of Congress Control Number: 2006934887
Copyright ©2007 by MindShare, Inc.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means, electronic, mechanical, photocopy-
ing, recording, or otherwise, without the prior written permission of the publisher.
Printed in the United States of America.
For information on obtaining permission for use of material from this work, please sub-
mit a written request to:
MindShare Press
Attn: Maryanne Daves
4285 Slash Pine Dr.
Colorado Springs, CO 80908
Fax: 719-487-1434
Set in 10-point Palatino by MindShare, Inc.
ISBN 978-0-9770878-1-5
First Printing April 2007
Contents
About This Book
Scope............................................................................................................................................. 1
The MindShare Architecture Series ....................................................................................... 1
Cautionary Note ......................................................................................................................... 3
The Standard Is the Final Word .............................................................................................. 3
Documentation Conventions................................................................................................... 3
Hexadecimal Notation ........................................................................................................ 3
Binary Notation.................................................................................................................... 4
Decimal Notation ................................................................................................................. 4
Bits Versus Bytes Notation ................................................................................................. 4
Bit Fields ................................................................................................................................ 4
Other Terminology and Abbreviations ................................................................................. 5
Visit Our Web Site (www.mindshare.com) .......................................................................... 5
We Want Your Feedback........................................................................................................... 6
Part One
SATA Overview
Chapter 1: The Evolution of Parallel ATA
ATA transitions to Serial Interface......................................................................................... 9
Origins of ATA ......................................................................................................................... 10
Emergence of IDE (Integrated Disc Electronics) Drives................................................... 11
Support for Two Drives .................................................................................................... 11
Compatibility Problems .................................................................................................... 12
The ATA Standard ................................................................................................................... 12
The ATA Signalling Interface........................................................................................... 13
ATA Protocol/Performance Review............................................................................... 17
ATA............................................................................................................................... 17
ATA-2/3....................................................................................................................... 17
ATA-4 ........................................................................................................................... 18
ATA-5 ........................................................................................................................... 18
ATA-6 ........................................................................................................................... 18
ATA-7 ........................................................................................................................... 18
The Legacy Programming Interface...................................................................................... 19
HBA Register Descriptions............................................................................................... 20
Device Register - Selecting the Target ATA Device............................................... 21
Start Sector Address ................................................................................................... 21
Physical Disc Address Registers........................................................................ 22
Logical Block Addressing................................................................................... 24
Logical Block Address Registers (28 bits) ........................................................ 24
ix
Contents
Logical Block Address Registers (48 bits) ........................................................ 24
Transfer Size Register................................................................................................. 25
Feature Register .......................................................................................................... 25
Command Register..................................................................................................... 26
Data Register ............................................................................................................... 26
Status Register ............................................................................................................. 26
Error Register .............................................................................................................. 28
Device Control Register ............................................................................................. 28
Alternate Status Register ........................................................................................... 29
Support for Multiple ATA Interfaces.............................................................................. 29
The ATA Packet Interface (ATAPI)...................................................................................... 30
Device Signature ...................................................................................................................... 31
Performing Commands........................................................................................................... 31
Setting Up Data Transfers ......................................................................................... 32
Commands without Data Transfer ................................................................... 32
Data Transfer Commands. ................................................................................. 32
Command Execution.................................................................................................. 32
Overlap and Command Queuing.................................................................................... 34
Overlap......................................................................................................................... 34
Queuing........................................................................................................................ 35
Drives Capabilities - The Device Identify Command................................................... 35
Summary of ATA Standards.................................................................................................. 36
Chapter 2: The Motivation for SATA
Motivation and Design Goals for SATA............................................................................. 37
Lower Pin Count....................................................................................................................... 38
Performance............................................................................................................................... 38
No Drive Configuration Required........................................................................................ 39
Cables and Connectors............................................................................................................ 39
Reliability .................................................................................................................................. 41
Lower Voltages ......................................................................................................................... 41
Migration to Servers ................................................................................................................ 41
Software Compatibility with Parallel ATA ........................................................................ 42
Chapter 3: SATA Overview
The SATA Specification ......................................................................................................... 43
Summary of SATA Features .................................................................................................. 44
The Serial Interconnect ........................................................................................................... 45
SATA Compatibility with Parallel ATA ............................................................................. 46
The Legacy Programming Interface................................................................................ 46
Legacy Drive Addressing with SATA ............................................................................ 48
x
Contents
Drive Addressing Based on Single Drive Interfaces.............................................. 49
Port Selection Based on Master/Slave Emulation ................................................. 49
SATA-Specific Registers ........................................................................................................ 51
SATA Protocol Layer Overview ............................................................................................ 52
Application Layer .............................................................................................................. 53
Host Software Issues each Command ..................................................................... 54
The SATA Drive Receives and Processes the Command ..................................... 55
Command Layer ................................................................................................................ 55
Transport Layer.................................................................................................................. 55
Link Layer.................................................................................................................................. 57
Physical Layer ........................................................................................................................... 58
Establishing Link Communications ................................................................................ 59
OOB Signaling............................................................................................................. 59
Link initialization........................................................................................................ 61
Normal FIS Communications........................................................................................... 61
SATA Command Protocol ...................................................................................................... 61
Example Non-Data Command......................................................................................... 62
Example DMA Read Command ...................................................................................... 63
Example DMA Write Command ..................................................................................... 64
Major Features of SATA II ..................................................................................................... 65
Native Command Queuing .............................................................................................. 65
Port Multipliers .................................................................................................................. 66
Port Selectors ...................................................................................................................... 67
Enclosure Services.............................................................................................................. 68
Hot Plug Support ............................................................................................................... 69
Higher Transmission Rate ................................................................................................ 69
The AHCI Programming Interface ....................................................................................... 69
Chapter 4: Introduction to FIS Transfers
General ....................................................................................................................................... 71
FIS Transfers ............................................................................................................................. 72
Application Layer (HBA).................................................................................................. 73
Transport Layer (HBA) ..................................................................................................... 73
Frame Information Structures................................................................................... 75
FIS Ready for Transfer ............................................................................................... 75
Flow Control During FIS Transmission .................................................................. 76
Link Layer (Transmit) ....................................................................................................... 76
CRC Generation .......................................................................................................... 77
Framing the FIS ........................................................................................................... 78
Scrambler ..................................................................................................................... 78
Perform 8b-to-10b encoding...................................................................................... 79
Physical Layer (Transmit)................................................................................................. 79
xi