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pg058-blk-mem-gen.pdf
Block Memory Generator v8.3
Table of Contents
IP Facts
Ch. 1: Overview
Feature Summary
Features Common to the Native Interface and AXI4 BMG Cores
Native Block Memory Generator Specific Features
AXI4 Interface Block Memory Generator Specific Features
Native Block Memory Generator Feature Summary
Memory Types
Selectable Memory Algorithm
Configurable Width and Depth
Selectable Operating Mode per Port
Selectable Port Aspect Ratios
Optional Byte-Write Enable
Optional Output Registers
Optional Pipeline Stages
Optional Enable Pin
Optional Set/Reset Pin
Memory Initialization
Hamming Error Correction Capability
AXI4 Interface Block Memory Generator Feature Summary
Overview
Applications
AXI4 Block Memories–Memory Slave Mode
AXI4-Lite Block Memories–Memory Slave Mode
AXI4 Block Memories–Peripheral Slave Mode
AXI4-Lite Block Memories–Peripheral Slave Mode
AXI4 BMG Core Channel Handshake Sequence
AXI4-Lite Single Burst Transactions
AXI4 Incremental Burst Support
AXI4 Wrap Burst Support
AXI4 Narrow Transactions
AXI4 Unaligned Transactions
Configurable Width and Depth
AXI4 Interface Block Memory Addressing
Throughput and Performance
Selectable Port Aspect Ratios
Optional Output Register
Optional Pipeline Stages
Memory Initialization Capability
Applications
Licensing and Ordering Information
Ch. 2: Product Specification
Performance
Resource Utilization
Latency
Port Descriptions
Native Block Memory Generator Signals
AXI4 Interface Block Memory Generator Signals
AXI4 Interface - Global Signals
AXI4-Interface Signals
AXI4-Lite Interface Signals
Ch. 3: Designing with the Core
General Design Guidelines
Memory Type
Selectable Memory Algorithm
Minimum Area Algorithm
Low Power Algorithm
Fixed Primitive Algorithm
Selectable Width and Depth
Operating Mode
Data Width Aspect Ratios
Port Aspect Ratios
Port Aspect Ratio Example
Read-to-Write Aspect Ratios
Aspect Ratio Limitations
Byte-Writes
Byte-Write Example
Write First Mode Considerations
Collision Behavior
Collisions and Asynchronous Clocks: General Guidelines
Collisions and Synchronous Clocks: General Guidelines
Collisions and Simple Dual-port RAM
Additional Memory Collision Restrictions: Address Space Overlap
Optional Output Registers
Optional Pipeline Stages
Optional Register Clock Enable Pins
Optional Set/Reset Pins
Memory Output Flow Control
Read Data and Read Enable Latency
Reset Priority
Special Reset Behavior
Controlling Reset Operations
Built-in Error Correction Capability and Error Injection
Error Injection
Soft Error Correction Capability and Error injection
Overview
Details
Timing Diagrams
Device Utilization and Performance Benchmarks
Lower Data Widths in SDP Configurations
UltraScale Architecture-Based Device Features
Standard DOUT Block RAM Cascading
Pipe Line Register Addition in the Built ECC Mode
Clocking
Resets
Ch. 4: Design Flow Steps
Customizing and Generating the Core
Native Block Memory Generator Basic Tab
Port Options Tab
Other Options Tab
Specifying Initial Memory Contents
Summary Tab
Power Estimate Options Tab
Block RAM Usage
LUT Utilization and Performance
Generating the AXI4 Interface Block Memory Generator Core
Basic Tab
AXI4 Tab
Customizing the Core with IP Integrator
User Parameters
Constraining the Core
Simulation
Synthesis and Implementation
Ch. 5: Detailed Example Design
Ch. 6: Test Bench
Core with Native Interface
Core with AXI4 Interface
Messages and Warnings
Appx. A: Verification, Compliance, and Interoperability
Simulation
Appx. B: Migrating and Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Auto Upgrade Feature
Appx. C: Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Simulation Debug
Hardware Debug
General Checks
Appx. D: Native Block Memory Generator Supplemental Information
Low Power Designs
Native Block Memory Generator SIM Parameters
AXI4 Interface Block Memory Generator SIM Parameters
Output Register Configurations
Memory with Primitive and Core Output Registers
Memory with Primitive Output Registers and without Special Reset Behavior Option
Memory with Primitive Output Registers and with Special Reset Behavior Option
Memory with Core Output Registers
Memory with No Output Registers
Appx. E: Additional Resources and Legal Notices
Xilinx Resources
References
Revision History
Please Read: Important Legal Notices
Block Memory
Generator v8.3
LogiCORE IP Product Guide
Vivado Design Suite
PG058 April 5, 2017
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Native Block Memory Generator Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AXI4 Interface Block Memory Generator Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Licensing and Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
UltraScale Architecture-Based Device Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 5: Detailed Example Design
Chapter 6: Test Bench
Core with Native Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Core with AXI4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Messages and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Appendix A: Verification, Compliance, and Interoperability
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Appendix B: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Appendix D: Native Block Memory Generator Supplemental Information
Appendix E: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Introduction
The Xilinx® LogiCORE ™ IP Block Memory
Generator (BMG) core is an advanced memory
constructor that generates area and
performance-optimized memories using
embedded block RAM resources in Xilinx
FPGAs.
The BMG core supports both Native and AXI4
interfaces.
The AXI4 interface configuration of the BMG
core is derived from the Native interface BMG
configuration and adds an industry-standard
bus protocol interface to the core. Two AXI4
interface styles are available: AXI4 and
AXI4-Lite.
Features
For details on the features of each interface, see
Feature Summary in Chapter 1.
IP Facts
LogiCORE™ IP Facts Table
Core Specifics
Supported
Device
Family(1)
Supported
User Interfaces
Resources
UltraScale+™ Families,
UltraScale™ Architecture, Zynq®-7000, 7 Series
AXI4, AXI4-Lite
Performance and Resource Utilization web page.
Provided with Core
Design Files
Example
Design
Test Bench
Constraints
File
Simulation
Model
Supported
S/W Driver
Design Entry
Simulation
Synthesis
Encrypted RTL
VHDL
VHDL
XDC
Verilog Behavioral(2)
N/A
Tested Design Flows(3)
Vivado® Design Suite
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. Behavioral models do not precisely model collision behavior.
See Collision Behavior, page 51 for details.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
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Chapter 1
Overview
The Block Memory Generator core uses embedded Block Memory primitives in Xilinx®
FPGAs to extend the functionality and capability of a single primitive to memories of
arbitrary widths and depths. Sophisticated algorithms within the Block Memory Generator
core produce optimized solutions to provide convenient access to memories for a wide
range of configurations.
This core has two fully independent ports that access a shared memory space. Both A and
B ports have a write and a read interface. In UltraScale™, Zynq®-7000 and 7 series FPGA
architectures, each of the four interfaces can be uniquely configured with a different data
width. When not using all four interfaces, you can select a simplified memory configuration
(for example, a Single-Port Memory or Simple Dual-Port Memory) to reduce FPGA resource
utilization.
This core is not completely backward-compatible with the discontinued legacy Single-Port
Block Memory and Dual-Port Block Memory cores; for information about the differences,
see Appendix B, Migrating and Upgrading.
Feature Summary
Features Common to the Native Interface and AXI4 BMG Cores
• Optimized algorithms for minimum block RAM resource utilization or low power
utilization
• Configurable memory initialization
•
Individual Write enable per byte in UltraScale™, Zynq -7000, Kintex ®-7, and Virtex ®-7
devices with or without parity
• Optimized Verilog behavioral model for fast simulation times; structural simulation
models for precise simulation of memory behaviors
Selectable operating mode per port: WRITE_FIRST, READ_FIRST, or NO_CHANGE
Lower data widths for UltraScale™, Zynq-7000 and 7 series devices in SDP mode
•
•
• VHDL example design and demonstration test bench demonstrating the IP core design
flow, including how to instantiate and simulate it
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•
Standard DOUT block RAM Cascading
Chapter 1: Overview
Native Block Memory Generator Specific Features
• Generates Single-port RAM, Simple Dual-port RAM, True Dual-port RAM, Single-port
ROM, and Dual-port ROM
Supports memory sizes up to a maximum of 16 MBytes (byte size 8 or 9) (limited only
by memory resources on selected part)
•
• Configurable port aspect ratios for dual-port configurations and Read-to-Write aspect
•
ratios
Supports the built-in Hamming Error Correction Capability (ECC). Error injection pins
allow insertion of single and double-bit errors
Supports soft Hamming Error Correction (Soft ECC) for data widths less than 64 bits
•
• Option to pipeline DOUT bus for improved performance in specific configurations
• Choice of reset priority for output registers between priority of SR (Set Reset) or CE
(Clock Enable)
Performance up to 450 MHz
•
Supports AXI4 and AXI4-Lite interface protocols
AXI4 Interface Block Memory Generator Specific Features
•
• AXI4 compliant Memory and Peripheral Slave types
Independent Read and Write Channels
•
Zero delay datapath
•
Supports registered outputs for handshake signals
•
•
INCR burst sizes up to 256 data transfers
• WRAP bursts of 2, 4, 8, and 16 data beats
• AXI narrow and unaligned burst transfers
•
•
•
Simple Dual-port RAM primitive configurations
Performance up to 300 MHz
Supports data widths up to 256 bits and memory depths from 1 to 1M words (limited
only by memory resources on selected part)
Symmetric aspect ratios
•
• Asynchronous active-Low reset
• UltraRAM support in IP Integrator for UltraScale+™ devices
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Chapter 1: Overview
Native Block Memory Generator Feature Summary
Memory Types
The Block Memory Generator core uses embedded block RAM to generate five types of
memories:
Single-port RAM
Simple Dual-port RAM
True Dual-port RAM
Single-port ROM
•
•
•
•
• Dual-port ROM
For dual-port memories, each port operates independently. Operating mode, clock
frequency, optional output registers, and optional pins are selectable per port. For Simple
Dual-port RAM, the operating modes are not selectable. See Collision Behavior, page 51 for
additional information.
Selectable Memory Algorithm
The core configures block RAM primitives and connects them together using one of the
following algorithms:
• Minimum Area Algorithm: The memory is generated using the minimum number of
•
•
block RAM primitives. Both data and parity bits are utilized.
Low Power Algorithm: The memory is generated such that the minimum number of
block RAM primitives are enabled during a Read or Write operation.
Fixed Primitive Algorithm: The memory is generated using only one type of block
RAM primitive. For a complete list of primitives available for each device family, see the
data sheet for that family.
Configurable Width and Depth
The Block Memory Generator core can generate memory structures from 1 to 4608 bits
wide, and at least two locations deep. The maximum depth of the memory is limited only by
the number of block RAM primitives in the target device, as shown in Table 1-1 through
Table 1-3.
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Chapter 1: Overview
Table 1-1: BMG Width and Depth (without Byte Write Enable)
Memory Width (bits)
Less than or equal to 128 (≤128)
Greater than 128 and less than or equal to 256
(>128 and ≤256)
Greater than 256 and less than or equal to 512
(>256 and ≤512)
Greater than 512 and less than or equal to 1024
(>512 and ≤1024)
Greater than 1024 and less than or equal to 2048
(>1024 and ≤2048)
Greater than 2048 and less than or equal to 4608
(>2048 and ≤4608)
Memory Depth (words)
Less than or equal to 1M (≤1M)
Less than or equal to 512k (≤512k)
Less than or equal to 256k (≤256k)
Less than or equal to 128k (≤128k)
Less than or equal to 64k (≤64k)
Less than or equal to 32k (32k)
Table 1-2: BMG Width and Depth: Byte Size 8 (with Byte Write Enable)
Memory Width (bits)
Less than or equal to 128 (≤128)
Greater than 128 and less than or equal to 256
(>128 and ≤256)
Greater than 256 and less than or equal to 512
(>256 and ≤512)
Greater than 512 and less than or equal to 1024
(>512 and ≤1024)
Greater than 1024 and less than or equal to 2048
(>1024 and ≤2048)
Greater than 2048 and less than or equal to 4096
(>2048 and ≤4096)
Memory Depth (words)
Less than or equal to 1M (≤1M)
Less than or equal to 512k (≤512k)
Less than or equal to 256k (≤256k)
Less than or equal to 128k (≤128k)
Less than or equal to 64k (≤64k)
Less than or equal to 32k (32k)
Table 1-3: BMG Width and Depth: Byte Size 9 (with Byte Write Enable)
Memory Width (bits)
Less than or equal to 144 (≤144)
Greater than 128 and less than or equal to 288
(>144 and ≤288)
Greater than 288 and less than or equal to 576
(>288 and ≤576)
Greater than 576 and less than or equal to 1152
(>576 and ≤1152)
Greater than 1152 and less than or equal to 2304
(>1152 and ≤2304)
Greater than 2304 and less than or equal to 4608
(>2304 and ≤4608)
Memory Depth (words)
Less than or equal to 1M (≤1M)
Less than or equal to 512k (≤512k)
Less than or equal to 256k (≤256k)
Less than or equal to 128k (≤128k)
Less than or equal to 64k (≤64k)
Less than or equal to 32k (32k)
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