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riscv-debug-spec-0.13 Riscv 调试V13.pdf
Preface
Introduction
Terminology
Context
About This Document
Structure
Register Definition Format
Long Name (shortname, at 0x123)
Background
Supported Features
System Overview
Debug Module (DM)
Debug Module Interface (DMI)
Reset Control
Selecting Harts
Selecting a Single Hart
Selecting Multiple Harts
Run Control
Abstract Commands
Abstract Command Listing
Access Register
Quick Access
Program Buffer
Overview of States
System Bus Access
Quick Access
Security
Debug Module DMI Registers
Debug Module Status (dmstatus, at 0x11)
Debug Module Control (dmcontrol, at 0x10)
Hart Info (hartinfo, at 0x12)
Halt Summary (haltsum, at 0x13)
Hart Array Window Select (hawindowsel, at 0x14)
Hart Array Window (hawindow, at 0x15)
Abstract Control and Status (abstractcs, at 0x16)
Abstract Command (command, at 0x17)
Abstract Command Autoexec (abstractauto, at 0x18)
Device Tree Addr 0 (devtreeaddr0, at 0x19)
Abstract Data 0 (data0, at 0x04)
Program Buffer 0 (progbuf0, at 0x20)
Authentication Data (authdata, at 0x30)
System Bus Access Control and Status (sbcs, at 0x38)
System Bus Address 31:0 (sbaddress0, at 0x39)
System Bus Address 63:32 (sbaddress1, at 0x3a)
System Bus Address 95:64 (sbaddress2, at 0x3b)
System Bus Data 31:0 (sbdata0, at 0x3c)
System Bus Data 63:32 (sbdata1, at 0x3d)
System Bus Data 95:64 (sbdata2, at 0x3e)
System Bus Data 127:96 (sbdata3, at 0x3f)
RISC-V Debug
Debug Mode
Load-Reserved/Store-Conditional Instructions
Single Step
Reset
dret Instruction
Core Debug Registers
Debug Control and Status (dcsr, at 0x7b0)
Debug PC (dpc, at 0x7b1)
Debug Scratch Register 0 (dscratch0, at 0x7b2)
Debug Scratch Register 1 (dscratch1, at 0x7b3)
Virtual Debug Registers
Privilege Level (priv, at virtual)
Trigger Module
Trigger Registers
Trigger Select (tselect, at 0x7a0)
Trigger Data 1 (tdata1, at 0x7a1)
Trigger Data 2 (tdata2, at 0x7a2)
Trigger Data 3 (tdata3, at 0x7a3)
Match Control (mcontrol, at 0x7a1)
Instruction Count (icount, at 0x7a1)
Debug Transport Module (DTM)
JTAG Debug Transport Module
JTAG Background
JTAG DTM Registers
IDCODE (at 0x01)
DTM Control and Status (dtmcs, at 0x10)
Debug Module Interface Access (dmi, at 0x11)
BYPASS (at 0x1f)
Recommended JTAG Connector
Hardware Implementations
Abstract Command Based
Execution Based
Debugger Implementation
Debug Module Interface Access
Main Loop
Halting
Running
Single Step
Accessing Registers
Using Abstract Command
Using Program Buffer
Reading Memory
Using System Bus Access
Using Program Buffer
Writing Memory
Using System Bus Access
Using Program Buffer
Handling Exceptions
Quick Access
Future Ideas
Serial Ports
Serial Control and Status (sercs, at 0x34)
Serial TX Data (sertx, at 0x35)
Serial RX Data (serrx, at 0x36)
Index
Change Log
RISC-V External Debug Support
Version 0.13
f7f3277d78d5b72dbba7d718d40892c469ca22ba
Tim Newsome
Tue Nov 28 07:54:42 2017 -0800
Preface
Warning! This draft specification will change before being accepted as standard, so
implementations made to this draft specification will likely not conform to the future
standard.
Acknowledgments
I would like to thank the following people for their time, feedback, and ideas: Bruce Ablei-
dinger, Krste Asanovic, Mark Beal, Alex Bradbury, Zhong-Ho Chen, Monte Dalrymple, Vyacheslav
Dyanchenco, Peter Egold, Richard Herveille, Po-wei Huang, Scott Johnson, Aram Nahidipour,
Rishiyur Nikhil, Gajinder Panesar, Klaus Kruse Pedersen, Antony Pavlov, Ken Pettit, Wesley
Terpstra, Megan Wachs, Stefan Wallentowitz, Ray Van De Walker, Andrew Waterman, and Andy
Wright.
i
ii
RISC-V External Debug Support Version 0.13
Contents
Preface
1 Introduction
1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2 Register Definition Format
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2.1
Long Name (shortname, at 0x123) . . . . . . . . . . . . . . . . . . .
1.3 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 System Overview
3 Debug Module (DM)
3.1 Debug Module Interface (DMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Selecting Harts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Selecting a Single Hart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
Selecting Multiple Harts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
1
1
1
2
2
2
2
3
3
5
7
7
8
8
9
9
9
3.5 Abstract Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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RISC-V External Debug Support Version 0.13
3.5.1 Abstract Command Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.1.1 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.1.2 Quick Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Program Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Overview of States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 System Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Quick Access
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.11 Debug Module DMI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.11.1 Debug Module Status (dmstatus, at 0x11)
. . . . . . . . . . . . . . . . . . . 15
3.11.2 Debug Module Control (dmcontrol, at 0x10) . . . . . . . . . . . . . . . . . . 19
3.11.3 Hart Info (hartinfo, at 0x12)
. . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.4 Halt Summary (haltsum, at 0x13) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11.5 Hart Array Window Select (hawindowsel, at 0x14) . . . . . . . . . . . . . . . 22
3.11.6 Hart Array Window (hawindow, at 0x15)
. . . . . . . . . . . . . . . . . . . . 23
3.11.7 Abstract Control and Status (abstractcs, at 0x16)
. . . . . . . . . . . . . . 23
3.11.8 Abstract Command (command, at 0x17)
. . . . . . . . . . . . . . . . . . . . . 24
3.11.9 Abstract Command Autoexec (abstractauto, at 0x18)
. . . . . . . . . . . . 26
3.11.10 Device Tree Addr 0 (devtreeaddr0, at 0x19) . . . . . . . . . . . . . . . . . . 26
3.11.11 Abstract Data 0 (data0, at 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.12 Program Buffer 0 (progbuf0, at 0x20) . . . . . . . . . . . . . . . . . . . . . . 27
3.11.13 Authentication Data (authdata, at 0x30) . . . . . . . . . . . . . . . . . . . . 27
3.11.14 System Bus Access Control and Status (sbcs, at 0x38)
. . . . . . . . . . . . 27
3.11.15 System Bus Address 31:0 (sbaddress0, at 0x39) . . . . . . . . . . . . . . . . 29
3.11.16 System Bus Address 63:32 (sbaddress1, at 0x3a)
. . . . . . . . . . . . . . . 29
3.11.17 System Bus Address 95:64 (sbaddress2, at 0x3b)
. . . . . . . . . . . . . . . 29
3.11.18 System Bus Data 31:0 (sbdata0, at 0x3c) . . . . . . . . . . . . . . . . . . . . 30
3.11.19 System Bus Data 63:32 (sbdata1, at 0x3d) . . . . . . . . . . . . . . . . . . . 31
RISC-V External Debug Support Version 0.13
v
3.11.20 System Bus Data 95:64 (sbdata2, at 0x3e)
. . . . . . . . . . . . . . . . . . . 31
3.11.21 System Bus Data 127:96 (sbdata3, at 0x3f) . . . . . . . . . . . . . . . . . . . 31
4 RISC-V Debug
33
4.1 Debug Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2 Load-Reserved/Store-Conditional Instructions . . . . . . . . . . . . . . . . . . . . . . 34
4.3 Single Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.1
dret Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5 Core Debug Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5.1 Debug Control and Status (dcsr, at 0x7b0) . . . . . . . . . . . . . . . . . . . 35
4.5.2 Debug PC (dpc, at 0x7b1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.5.3 Debug Scratch Register 0 (dscratch0, at 0x7b2) . . . . . . . . . . . . . . . . 38
4.5.4 Debug Scratch Register 1 (dscratch1, at 0x7b3) . . . . . . . . . . . . . . . . 38
4.6 Virtual Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6.1 Privilege Level (priv, at virtual) . . . . . . . . . . . . . . . . . . . . . . . . . 38
5 Trigger Module
41
5.1 Trigger Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.1 Trigger Select (tselect, at 0x7a0) . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1.2 Trigger Data 1 (tdata1, at 0x7a1) . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1.3 Trigger Data 2 (tdata2, at 0x7a2) . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.4 Trigger Data 3 (tdata3, at 0x7a3) . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.5 Match Control (mcontrol, at 0x7a1) . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.6
Instruction Count (icount, at 0x7a1)
. . . . . . . . . . . . . . . . . . . . . . 47
6 Debug Transport Module (DTM)
49
6.1 JTAG Debug Transport Module
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.1
JTAG Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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RISC-V External Debug Support Version 0.13
6.1.2
JTAG DTM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.3
IDCODE (at 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.4 DTM Control and Status (dtmcs, at 0x10)
. . . . . . . . . . . . . . . . . . . 51
6.1.5 Debug Module Interface Access (dmi, at 0x11)
. . . . . . . . . . . . . . . . . 52
6.1.6 BYPASS (at 0x1f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.1.7 Recommended JTAG Connector
. . . . . . . . . . . . . . . . . . . . . . . . . 54
A Hardware Implementations
57
A.1 Abstract Command Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
A.2 Execution Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
B Debugger Implementation
59
B.1 Debug Module Interface Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B.2 Main Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.3 Halting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.4 Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.5 Single Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.6 Accessing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.6.1 Using Abstract Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.6.2 Using Program Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
B.7 Reading Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
B.7.1 Using System Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
B.7.2 Using Program Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
B.8 Writing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
B.8.1 Using System Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
B.8.2 Using Program Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
B.9 Handling Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
B.10 Quick Access
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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