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PI7C9X2G404SL datasheet.pdf
PI7C9X2G404SL
PCI EXPRESS GEN 2 PACKET SWITCH
DATASHEET
REVISION 1.1
November 2012
3545 North 1ST Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
FAX: 408-435-1100
Internet: http://www.pericom.com
PI7C9X2G404SL
4Port-4Lane PCI Express Gen 2 Switch
SlimPacketTM Family
Datasheet
DISCLAIMER
The information contained in this document is proprietary and confidential to Pericom Semiconductor Cooperation (PSC). No part of this
document may be copied or reproduced in any form or by any means without prior written consent of PSC.
The information in this document is subjected to change without notice. PSC retains the right to make changes to this document at any time
without notice. While the information contained in this document has been checked for accuracy, such information is preliminary, and PSC does
not warrant the accuracy and completeness of such information. PSC does not assume any liability or responsibility for damages arising from any
use of the information contained in this document.
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a
specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1) Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b)
Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury to the user.
2) A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to
make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best
possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry
embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent
infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent, patent rights or other rights, of Pericom Semiconductor Corporation.
All other trademarks are of their respective companies.
November 2012 – Revision 1.1
Confidential - Pericom Semiconductor
Page 2 of 88
PI7C9X2G404SL
4Port-4Lane PCI Express Gen 2 Switch
SlimPacketTM Family
Datasheet
REVISION HISTORY
Date
6/9/10
10/19/10
Revision Number
0.1
0.2
Description
Preliminary Datasheet
Added Section 6 EEPROM Interface And System Management Bus
Added Section 7 Register Description
Added Industrial Temperature Support (Section 1 Features, Section 11.1
Absolute Maximum Ratings, Section 13 Ordering Information)
Updated Section 1 Features (integrated reference clock)
Updated Section 3.1 PCI Express Interface Signals (Added REFCLKI_P,
REFCLKI_N, REFCLKO_P[3:0], REFCLKO_N[3:0], and IREF)
Updated Section 3.2 Port Configuration Signals (RXPOLINV_DIS)
Updated Section 3.3 Miscellaneous Signals (TEST4 and TEST5)
Updated Section 1 Features (OBFF and LTR support)
Updated Section 3 Pin Description (RXPOLINV_DIS, PRSNT[3:1], TEST4,
TEST5, and CVDDR)
Updated Section 6 EEPROM Interface And System Management Bus
Updated Section 7 Register Description
Updated Table 8-1 Clock Requirement
Updated Table 3.5 Power Pins
Updated Table 4.1 Pin List of 129-Pin LQFP
7/12/11
11/23/11
6/27/12
7/25/12
0.3
0.4
0.5
1.0
11/7/12
1.1
November 2012 – Revision 1.1
Confidential - Pericom Semiconductor
Page 3 of 88
PI7C9X2G404SL
4Port-4Lane PCI Express Gen 2 Switch
SlimPacketTM Family
Datasheet
TABLE OF CONTENTS
1 FEATURES ...................................................................................................................................................................... 9
2 GENERAL DESCRIPTION ......................................................................................................................................... 10
3 PIN DESCRIPTION ...................................................................................................................................................... 12
PCI EXPRESS INTERFACE SIGNALS .................................................................................................... 12
3.1
3.2
PORT CONFIGURATION SIGNALS ....................................................................................................... 13
3.3 MISCELLANEOUS SIGNALS .................................................................................................................. 13
JTAG BOUNDARY SCAN SIGNALS ...................................................................................................... 14
3.4
3.5
POWER PINS ............................................................................................................................................. 14
4 PIN ASSIGNMENTS .................................................................................................................................................... 15
4.1
PIN LIST OF 128-PIN LQFP ....................................................................................................................... 15
5 FUNCTIONAL DESCRIPTION .................................................................................................................................. 16
5.1
5.2
5.3
5.4
5.5
5.6
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
PHYSICAL LAYER CIRCUIT .................................................................................................................. 16
RECEIVER DETECTION ................................................................................................................... 16
RECEIVER SIGNAL DETECTION ..................................................................................................... 17
RECEIVER EQUALIZATION ............................................................................................................. 17
TRANSMITTER SWING ...................................................................................................................... 17
DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS .................................................................... 17
DRIVE AMPLITUDE .......................................................................................................................... 18
DRIVE DE-EMPHASIS ...................................................................................................................... 19
TRANSMITTER ELECTRICAL IDLE LATENCY ............................................................................... 19
DATA LINK LAYER (DLL) ...................................................................................................................... 19
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) .............................................. 20
ROUTING .................................................................................................................................................. 20
TC/VC MAPPING ...................................................................................................................................... 20
QUEUE ....................................................................................................................................................... 21
PH ....................................................................................................................................................... 21
PD ....................................................................................................................................................... 21
NPHD ................................................................................................................................................. 21
CPLH .................................................................................................................................................. 21
CPLD .................................................................................................................................................. 21
TRANSACTION ORDERING ................................................................................................................... 21
5.7
PORT ARBITRATION .............................................................................................................................. 22
5.8
VC ARBITRATION ................................................................................................................................... 23
5.9
5.10 FLOW CONTROL ..................................................................................................................................... 23
5.11 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) ............................................. 23
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS ............................................................................. 24
6.1
6.1.1
6.1.2
6.1.3
6.1.4
EEPROM INTERFACE ............................................................................................................................. 24
AUTO MODE EERPOM ACCESS ..................................................................................................... 24
EEPROM MODE AT RESET .............................................................................................................. 24
EEPROM SPACE ADDRESS MAP .................................................................................................... 24
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS .......................................... 27
SMBUS INTERFACE ................................................................................................................................. 35
6.2
7 REGISTER DESCRIPTION ........................................................................................................................................ 36
November 2012 – Revision 1.1
Confidential - Pericom Semiconductor
Page 4 of 88
7.1
7.2
PI7C9X2G404SL
4Port-4Lane PCI Express Gen 2 Switch
SlimPacketTM Family
Datasheet
REGISTER TYPES .................................................................................................................................... 36
TRANSPARENT MODE CONFIGURATION REGISTERS .................................................................... 36
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 38
7.2.1
DEVICE ID REGISTER – OFFSET 00h ............................................................................................. 38
7.2.2
COMMAND REGISTER – OFFSET 04h ............................................................................................ 38
7.2.3
PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................. 39
7.2.4
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 40
7.2.5
CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 40
7.2.6
CACHE LINE REGISTER – OFFSET 0Ch ......................................................................................... 40
7.2.7
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................ 40
7.2.8
HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................................... 40
7.2.9
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ...................................................................... 40
7.2.10
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................ 41
7.2.11
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................ 41
7.2.12
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................................... 41
7.2.13
I/O BASE ADDRESS REGISTER – OFFSET 1Ch .............................................................................. 41
7.2.14
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ............................................................................. 41
7.2.15
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch .......................................................................... 42
7.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h ................................................................... 42
7.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .................................................................. 42
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ..................................... 43
7.2.19
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h .................................... 43
7.2.20
7.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ......... 43
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ....... 43
7.2.22
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ................................................... 43
7.2.23
7.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .................................................. 44
7.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h ......................................................................... 44
7.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................. 44
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 44
7.2.27
BRIDGE CONTROL REGISTER – OFFSET 3Ch .............................................................................. 44
7.2.28
7.2.29
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 40h ........................................... 45
7.2.30 NEXT ITEM POINTER REGISTER – OFFSET 40h ........................................................................... 45
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 40h ............................................. 45
7.2.31
POWER MANAGEMENT DATA REGISTER – OFFSET 44h ............................................................ 46
7.2.32
7.2.33
PPB SUPPORT EXTENSIONS – OFFSET 44h .................................................................................. 46
7.2.34 DATA REGISTER – OFFSET 44h ...................................................................................................... 46
7.2.35 MSI CAPABILITY ID REGISTER – OFFSET 4Ch (Downstream Port Only) .................................... 47
7.2.36 NEXT ITEM POINTER REGISTER – OFFSET 4Ch (Downstream Port Only) ................................. 47
7.2.37 MESSAGE CONTROL REGISTER – OFFSET 4Ch (Downstream Port Only) .................................. 47
7.2.38 MESSAGE ADDRESS REGISTER – OFFSET 50h (Downstream Port Only) .................................... 47
7.2.39 MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h (Downstream Port Only) ...................... 47
7.2.40 MESSAGE DATA REGISTER – OFFSET 58h (Downstream Port Only) ........................................... 48
7.2.41
VPD CAPABILITY ID REGISTER – OFFSET 5Ch (Upstream Port Only) ........................................ 48
7.2.42 NEXT ITEM POINTER REGISTER – OFFSET 5Ch (Upstream Port Only) ...................................... 48
VPD REGISTER – OFFSET 5Ch (Upstream Port Only) .................................................................... 48
7.2.43
7.2.44
VPD DATA REGISTER – OFFSET 60h (Upstream Port Only) ......................................................... 48
7.2.45
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET 64h .................................................. 48
7.2.46 NEXT ITEM POINTER REGISTER – OFFSET 64h ........................................................................... 49
LENGTH REGISTER – OFFSET 64h ................................................................................................. 49
7.2.47
7.2.48
XPIP CSR0 – OFFSET 68h (Test Purpose Only) ............................................................................... 49
XPIP CSR1 – OFFSET 6Ch (Test Purpose Only) ............................................................................... 49
7.2.49
REPLAY TIME-OUT COUNTER – OFFSET 70h .............................................................................. 49
7.2.50
7.2.51
ACKNOWLEDGE LATENCY TIMER – OFFSET 70h ....................................................................... 50
November 2012 – Revision 1.1
Confidential - Pericom Semiconductor
Page 5 of 88
PI7C9X2G404SL
4Port-4Lane PCI Express Gen 2 Switch
SlimPacketTM Family
Datasheet
SWITCH OPERATION MODE – OFFSET 74h (Upstream Port) ...................................................... 50
7.2.52
SWITCH OPERATION MODE – OFFSET 74h (Downstream Port) .................................................. 51
7.2.53
XPIP_CSR2 – OFFSET 78h ............................................................................................................... 51
7.2.54
PHY PARAMETER 1 – OFFSET 7Ah ................................................................................................. 52
7.2.55
PHY PARAMETER 2 – OFFSET 7Ch ................................................................................................ 52
7.2.56
XPIP_CSR3 – OFFSET 80h ............................................................................................................... 53
7.2.57
XPIP_CSR4 – OFFSET 84h ............................................................................................................... 53
7.2.58
XPIP_CSR5 – OFFSET 88h ............................................................................................................... 53
7.2.59
TL_CSR – OFFSET 8Ch ..................................................................................................................... 53
7.2.60
PHY parameter 3 – OFFSET 90h ....................................................................................................... 54
7.2.61
7.2.62
PHY parameter 4 - OFFSET 94h ........................................................................................................ 54
7.2.63 Operation Mode –OFFSET 98h .......................................................................................................... 54
7.2.64
SSID/SSVID CAPABILITY ID REGISTER – OFFSET B0h ................................................................ 55
7.2.65 NEXT ITEM POINTER REGISTER – OFFSET B0h .......................................................................... 55
SUBSYSTEM VENDOR ID REGISTER – OFFSET B4h .................................................................... 55
7.2.66
7.2.67
SUBSYSTEM ID REGISTER – OFFSET B4h ..................................................................................... 55
7.2.68 GPIO CONTROL REGISTER – OFFSET B8h (Upstream Port Only) ............................................... 55
EEPROM CONTROL REGISTER – OFFSET BCh (Upstream Port Only) ........................................ 57
7.2.69
7.2.70
EEPROM ADDRESS REGISTER – OFFSET BCh (Upstream Port Only) ......................................... 57
EEPROM DATA REGISTER – OFFSET BCh (Upstream Port Only) ................................................ 57
7.2.71
7.2.72
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET C0h ............................................................ 58
7.2.73 NEXT ITEM POINTER REGISTER – OFFSET C0h .......................................................................... 58
7.2.74
PCI EXPRESS CAPABILITIES REGISTER – OFFSET C0h .............................................................. 58
7.2.75 DEVICE CAPABILITIES REGISTER – OFFSET C4h ....................................................................... 58
7.2.76 DEVICE CONTROL REGISTER – OFFSET C8h .............................................................................. 59
7.2.77 DEVICE STATUS REGISTER – OFFSET C8h ................................................................................... 60
LINK CAPABILITIES REGISTER – OFFSET CCh ............................................................................ 60
7.2.78
7.2.79
LINK CONTROL REGISTER – OFFSET D0h ................................................................................... 61
LINK STATUS REGISTER – OFFSET D0h ........................................................................................ 62
7.2.80
SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET D4h ................................... 63
7.2.81
7.2.82
SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET D8h .......................................... 63
7.2.83
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET D8h............................................... 64
7.2.84 DEVICE CAPABILITIES REGISTER 2 – OFFSET E4h .................................................................... 65
7.2.85 DEVICE CONTROL REGISTER 2 – OFFSET E8h ............................................................................ 65
7.2.86 DEVIDE STATUS REGISTER 2 – OFFSET EAh ............................................................................... 65
LINK CAPABILITIES REGISTER 2 – OFFSET ECh ......................................................................... 66
7.2.87
7.2.88
LINK CONTROL REGISTER 2 – OFFSET F0h ................................................................................. 66
LINK STATUS REGISTER 2 – OFFSET F2h ..................................................................................... 66
7.2.89
SLOT CAPABILITIES REGISTER 2 – OFFSET F4h ......................................................................... 66
7.2.90
SLOT CONTORL REGISTER 2 – OFFSET F8h ................................................................................ 66
7.2.91
7.2.92
SLOT STATUS REGISTER 2 – OFFSET FAh .................................................................................... 66
7.2.93
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h . 66
7.2.94 CAPABILITY VERSION – OFFSET 100h .......................................................................................... 67
7.2.95 NEXT ITEM POINTER REGISTER – OFFSET 100h ......................................................................... 67
7.2.96 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 67
7.2.97 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 68
7.2.98 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ............................................. 68
7.2.99 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h ...................................................... 69
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ..................................................... 70
7.2.100
7.2.101
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h ..................... 70
HEADER LOG REGISTER – OFFSET From 11Ch to 128h .......................................................... 71
7.2.102
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET 140h ................... 71
7.2.103
7.2.104
CAPABILITY VERSION – OFFSET 140h ...................................................................................... 71
November 2012 – Revision 1.1
Confidential - Pericom Semiconductor
Page 6 of 88
PI7C9X2G404SL
4Port-4Lane PCI Express Gen 2 Switch
SlimPacketTM Family
Datasheet
NEXT ITEM POINTER REGISTER – OFFSET 140h ..................................................................... 71
7.2.105
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h ................................................................ 71
7.2.106
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h ................................................................ 72
7.2.107
PORT VC CONTROL REGISTER – OFFSET 14Ch ....................................................................... 72
7.2.108
PORT VC STATUS REGISTER – OFFSET 14Ch ........................................................................... 72
7.2.109
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h .................................................... 73
7.2.110
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h ....................................................... 73
7.2.111
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h ............................................................ 74
7.2.112
VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch ................................................... 74
7.2.113
VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h ....................................................... 74
7.2.114
VC RESOURCE STATUS REGISTER (1) – OFFSET 164h ............................................................ 75
7.2.115
VC ARBITRATION TABLE REGISTER – OFFSET 170h ............................................................... 75
7.2.116
PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h ....................... 76
7.2.117
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER – OFFSET 20Ch ................ 76
7.2.118
CAPABILITY VERSION – OFFSET 20Ch ...................................................................................... 76
7.2.119
NEXT ITEM POINTER REGISTER – OFFSET 20Ch .................................................................... 76
7.2.120
DATA SELECT REGISTER – OFFSET 210h ................................................................................. 77
7.2.121
POWER BUDGETING DATA REGISTER – OFFSET 214h .......................................................... 77
7.2.122
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ..................................................... 77
7.2.123
ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port only) .................. 77
7.2.124
ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port only) ..................................... 78
7.2.125
EGRESS CONTROL VECTOR – OFFSET 228h (Downstream Port only) .................................... 78
7.2.126
LTR EXTENDED CAPABILITY HEADER – OFFSET 230h (Upstream Port only) ....................... 78
7.2.127
7.2.128 MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port only) .................................. 79
7.2.129 MAX NO-SNOOP LATENCY REGISTER – OFFSET 236h (Upstream Port only) ........................... 79
8 CLOCK SCHEME ........................................................................................................................................................ 80
9
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................................................... 81
9.1
9.2
9.3
9.4
9.5
INSTRUCTION REGISTER ...................................................................................................................... 81
BYPASS REGISTER ................................................................................................................................. 81
DEVICE ID REGISTER ............................................................................................................................. 81
BOUNDARY SCAN REGISTER ............................................................................................................... 81
JTAG BOUNDARY SCAN REGISTER ORDER ...................................................................................... 82
10 POWER MANAGEMENT ........................................................................................................................................... 83
11 ELECTRICAL AND TIMING SPECIFICATIONS .................................................................................................. 84
11.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 84
11.2 DC SPECIFICATIONS .............................................................................................................................. 84
11.3 AC SPECIFICATIONS .............................................................................................................................. 85
12 PACKAGE INFORMATION ....................................................................................................................................... 87
13 ORDERING INFORMATION ..................................................................................................................................... 88
November 2012 – Revision 1.1
Confidential - Pericom Semiconductor
Page 7 of 88
PI7C9X2G404SL
4Port-4Lane PCI Express Gen 2 Switch
SlimPacketTM Family
Datasheet
TABLE OF FIGURES
FIGURE 5-1 DRIVER OUTPUT WAVEFORM ................................................................................................................... 18
FIGURE 6-1 SMBUS ARCHITECTURE IMPLEMENTATION ON PI7C9X2G404SL ........................................................... 35
FIGURE 12-1 PACKAGE OUTLINE DRAWING ................................................................................................................. 87
LIST OF TABLES
TABLE 5-1 RECEIVER DETECTION THRESHOLD SETTINGS ........................................................................................... 16
TABLE 5-2 RECEIVER SIGNAL DETECT THRESHOLD .................................................................................................... 17
TABLE 5-3 RECEIVER EQUALIZATION SETTINGS ......................................................................................................... 17
TABLE 5-4 TRANSMITTER SWING SETTINGS ................................................................................................................ 17
TABLE 5-5 DRIVE AMPLITUDE BASE LEVEL REGISTERS.............................................................................................. 18
TABLE 5-6 DRIVE AMPLITUDE BASE LEVEL SETTINGS ................................................................................................ 18
TABLE 5-7 DRIVE DE-EMPHASIS BASE LEVEL REGISTER ............................................................................................ 19
TABLE 5-8 DRIVE DE-EMPHASIS BASE LEVEL SETTINGS ............................................................................................ 19
TABLE 5-9 SUMMARY OF PCI EXPRESS ORDERING RULES .......................................................................................... 22
TABLE 6-1 SMBUS ADDRESS PIN CONFIGURATION .................................................................................................... 35
TABLE 7-1 REGISTER ARRAY LAYOUT FOR VC ARBITRATION .................................................................................... 75
TABLE 7-2 TABLE ENTRY SIZE IN 4 BITS ..................................................................................................................... 76
TABLE 8-1 INPUT CLOCK REQUIREMENTS ................................................................................................................... 80
TABLE 9-1 INSTRUCTION REGISTER CODES .................................................................................................................. 81
TABLE 9-2 JTAG DEVICE ID REGISTER ....................................................................................................................... 81
TABLE 9-3 JTAG BOUNDARY SCAR REGISTER DEFINITION .......................................................................................... 82
TABLE 11-1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 84
TABLE 11-2 DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 84
TABLE 11-3 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (5.0 GBPS) CHARACTERISTICS . 85
TABLE 11-4 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (2.5 GBPS) CHARACTERISTICS . 85
TABLE 11-5 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (5.0 GBPS) CHARACTERISTICS ........... 86
TABLE 11-6 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (2.5 GBPS) CHARACTERISTICS ........... 86
November 2012 – Revision 1.1
Confidential - Pericom Semiconductor
Page 8 of 88
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