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RTL8211FS(I)(-VS)-CG_DataSheet_1.2.pdf
General Description
Features
System Applications
UTP (UTP((RGMII; UTP((SGMII) Application Diagram
Fiber (FIBER((RGMII) Application Diagram
UTP/Fiber to RGMII (UTP/FIBER Media Auto Detection ((RGMII) Application Diagram
SGMII to RGMII (SGMII((RGMII Bridge Mode) Application Diagram
Fiber to UTP (UTP((FIBER Media Converter) Application Diagram
PTP and Sync Ethernet Application Diagram (RTL8211FS(I)-VS O
Block Diagram
Pin Assignments
RTL8211FS(I) Pin Assignments
Package Identification
RTL8211FS(I)-VS Pin Assignments
Package Identification
Pin Descriptions
Transceiver Interface
Clock
RGMII
SerDes
Reset
Mode Selection (Hardware Configuration)
LED Default Settings
Regulator and Reference
Power and Ground
Management and PTP Application Interface
Function Description
Transmitter
Receiver
Precision Time Protocol (PTP) (RTL8211FS(I)-VS Only)
Synchronous Ethernet (Sync-E)
Energy Efficient Ethernet (EEE)
Wake-On-LAN (WOL)
Interrupt
INTB/PMEB Pin Usage
MDI Interface
Hardware Configuration
LED and PHY Address/LDO Configuration
Green Ethernet (1000/100Mbps Mode Only)
MAC/PHY Interface
Auto-Negotiation
Crossover Detection and Auto-Correction
LED Configuration
Polarity Correction
Power
PHY Reset (Hardware Reset)
Register Descriptions
UTP Register Mapping and Definitions
UTP MMD Register Mapping and Definition
Fiber Register Mapping and Definitions
SERDES Registers Mapping and Definitions
Register Tables
Switching Regulator
Power Sequence
Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Crystal Requirements
Oscillator/External Clock Requirements
DC Characteristics
SGMII Characteristics
1000Base-X Characteristics
AC Characteristics
Mechanical Dimensions
Mechanical Dimensions Notes
Ordering Information
RTL8211FS-CG RTL8211FS-VS-CG
RTL8211FSI-CG RTL8211FSI-VS-CG
INTEGRATED 10/100/1000M ETHERNET
PRECISION TRANSCEIVER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.2
25 July 2014
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8211FS(I)(-VS)
Datasheet
COPYRIGHT
©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094,
US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
Integrated 10/100/1000M Ethernet Precision Transceiver
ii
Track ID: JATR-8275-15 Rev. 1.2
REVISION HISTORY
Release Date
2014/04/09
2014/07/13
Revision
1.0
1.1
1.2
2014/07/25
RTL8211FS(I)(-VS)
Datasheet
Summary
First release.
Corrected minor typing errors.
Revised section 2 Features, page 2.
Revised section 7.13.4 Change Page, page 27.
Revised section 7.16 LED Configuration, page 33.
Revised section 7.19 PHY Reset (Hardware Reset), page 36.
Revised section 8 Register Descriptions, page 37.
Added section 8.5.24 FLCR (Fiber LED Control Register, Page 0xd04, Address 0x12),
page 54.
Revised section 9 Switching Regulator, page 75.
Revised Table 97 Oscillator/External Clock Requirements, page 78.
Revised section 10.8.2 RGMII Timing Modes, page 85.
Revised section 12 Ordering Information, page 91.
Corrected minor typing errors.
Revised section 3 System Applications, page 3.
Revised section 4 Block Diagram, page 7.
Revised section 6 Pin Descriptions, page 10.
Revised section 7.7 Interrupt, page 21.
Added section 7.13.2 SGMII, page 25.
Revised section 8 Register Descriptions, page 37.
Added section 8.5.25 MIICR (MII Control Register, Page 0xd08, Address 0x15), page 54.
Integrated 10/100/1000M Ethernet Precision Transceiver
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Track ID: JATR-8275-15 Rev. 1.2
Table of Contents
RTL8211FS(I)(-VS)
Datasheet
1. GENERAL DESCRIPTION..............................................................................................................................................1
2.
3.
4.
5.
6.
7.
FEATURES.........................................................................................................................................................................2
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
SYSTEM APPLICATIONS...............................................................................................................................................3
UTP (UTPRGMII; UTPSGMII) APPLICATION DIAGRAM ...........................................................................4
FIBER (FIBERRGMII) APPLICATION DIAGRAM ..................................................................................................4
UTP/FIBER TO RGMII (UTP/FIBER MEDIA AUTO DETECTION RGMII) APPLICATION DIAGRAM......................5
SGMII TO RGMII (SGMIIRGMII BRIDGE MODE) APPLICATION DIAGRAM.......................................................5
FIBER TO UTP (UTPFIBER MEDIA CONVERTER) APPLICATION DIAGRAM.........................................................6
PTP AND SYNC ETHERNET APPLICATION DIAGRAM (RTL8211FS(I)-VS ONLY) ........................................................6
BLOCK DIAGRAM...........................................................................................................................................................7
5.1.
5.2.
5.3.
5.4.
PIN ASSIGNMENTS .........................................................................................................................................................8
RTL8211FS(I) PIN ASSIGNMENTS...............................................................................................................................8
PACKAGE IDENTIFICATION...........................................................................................................................................8
RTL8211FS(I)-VS PIN ASSIGNMENTS ........................................................................................................................9
PACKAGE IDENTIFICATION...........................................................................................................................................9
PIN DESCRIPTIONS ......................................................................................................................................................10
TRANSCEIVER INTERFACE..........................................................................................................................................10
6.1.
CLOCK .......................................................................................................................................................................10
6.2.
RGMII.......................................................................................................................................................................11
6.3.
SERDES......................................................................................................................................................................11
6.4.
RESET ........................................................................................................................................................................11
6.5.
MODE SELECTION (HARDWARE CONFIGURATION) ....................................................................................................12
6.6.
LED DEFAULT SETTINGS...........................................................................................................................................12
6.7.
REGULATOR AND REFERENCE....................................................................................................................................13
6.8.
POWER AND GROUND ................................................................................................................................................13
6.9.
6.10. MANAGEMENT AND PTP APPLICATION INTERFACE ...................................................................................................14
FUNCTION DESCRIPTION ..........................................................................................................................................16
TRANSMITTER............................................................................................................................................................16
1000Mbps Mode...................................................................................................................................................16
7.1.1.
100Mbps Mode.....................................................................................................................................................16
7.1.2.
10Mbps Mode.......................................................................................................................................................16
7.1.3.
RECEIVER...................................................................................................................................................................16
1000Mbps Mode...................................................................................................................................................16
7.2.1.
100Mbps Mode.....................................................................................................................................................16
7.2.2.
10Mbps Mode.......................................................................................................................................................16
7.2.3.
PRECISION TIME PROTOCOL (PTP) (RTL8211FS(I)-VS ONLY).................................................................................17
Synchronized PTP Clock......................................................................................................................................17
7.3.1.
7.3.2. Packet Time Stamping..........................................................................................................................................18
7.3.3. Time Application Interface (TAI) .........................................................................................................................18
7.4.
SYNCHRONOUS ETHERNET (SYNC-E).........................................................................................................................19
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................19
7.5.
7.6. WAKE-ON-LAN (WOL)............................................................................................................................................19
7.7.
INTERRUPT.................................................................................................................................................................21
7.8.
INTB/PMEB PIN USAGE ...........................................................................................................................................21
7.1.
7.2.
7.3.
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7.17.
7.18.
7.19.
8.1.
8.2.
8.3.
8.4.
8.5.
7.16.1.
7.16.2.
7.12.1.
7.12.2.
7.13.1.
7.13.2.
7.13.3.
7.13.4.
7.13.5.
7.14.1.
7.14.2.
7.14.3.
RTL8211FS(I)(-VS)
Datasheet
7.9.
MDI INTERFACE ........................................................................................................................................................21
7.10. HARDWARE CONFIGURATION ....................................................................................................................................22
7.11.
LED AND PHY ADDRESS/LDO CONFIGURATION......................................................................................................23
7.12. GREEN ETHERNET (1000/100MBPS MODE ONLY) .....................................................................................................24
Cable Length Power Saving ............................................................................................................................24
Register Setting................................................................................................................................................24
7.13. MAC/PHY INTERFACE..............................................................................................................................................25
RGMII..............................................................................................................................................................25
SGMII ..............................................................................................................................................................25
Management Interface.....................................................................................................................................25
Change Page ...................................................................................................................................................27
Access to MDIO Manageable Device (MMD).................................................................................................27
7.14. AUTO-NEGOTIATION..................................................................................................................................................27
Auto-Negotiation Priority Resolution..............................................................................................................30
Auto-Negotiation Master/Slave Resolution .....................................................................................................31
Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution........................................................................31
7.15. CROSSOVER DETECTION AND AUTO-CORRECTION ....................................................................................................32
LED CONFIGURATION................................................................................................................................................33
7.16.
Customized LED Function...............................................................................................................................33
EEE LED Function..........................................................................................................................................35
POLARITY CORRECTION.............................................................................................................................................35
POWER .......................................................................................................................................................................35
PHY RESET (HARDWARE RESET) ..............................................................................................................................36
8. REGISTER DESCRIPTIONS.........................................................................................................................................37
UTP REGISTER MAPPING AND DEFINITIONS ..............................................................................................................37
UTP MMD REGISTER MAPPING AND DEFINITION .....................................................................................................39
FIBER REGISTER MAPPING AND DEFINITIONS ............................................................................................................39
SERDES REGISTERS MAPPING AND DEFINITIONS .....................................................................................................39
REGISTER TABLES......................................................................................................................................................40
8.5.1. BMCR (Basic Mode Control Register, Address 0x00) .........................................................................................40
8.5.2. BMSR (Basic Mode Status Register, Address 0x01).............................................................................................41
8.5.3. PHYID1 (PHY Identifier Register 1, Address 0x02) ............................................................................................42
8.5.4. PHYID2 (PHY Identifier Register 2, Address 0x03) ............................................................................................43
8.5.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04) ...........................................................................43
8.5.6. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) .........................................................44
8.5.7. ANER (Auto-Negotiation Expansion Register, Address 0x06).............................................................................44
8.5.8. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07) .........................................................45
8.5.9. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08)...........................................................45
GBCR (1000Base-T Control Register, Address 0x09).....................................................................................46
8.5.10.
GBSR (1000Base-T Status Register, Address 0x0A) .......................................................................................46
8.5.11.
8.5.12.
MACR (MMD Access Control Register, Address 0x0D) .................................................................................47
8.5.13.
MAADR (MMD Access Address Data Register, Address 0x0E)......................................................................47
GBESR (1000Base-T Extended Status Register, Address 0x0F) .....................................................................48
8.5.14.
INER (Interrupt Enable Register, Page 0xa42, Address 0x12) .......................................................................49
8.5.15.
8.5.16.
PHYCR1 (PHY Specific Control Register 1, Page 0xa43, Address 0x18).......................................................50
8.5.17.
PHYCR2 (PHY Specific Control Register 2, Page 0xa43, Address 0x19).......................................................51
8.5.18.
PHYSR (PHY Specific Status Register, Page 0xa43, Address 0x1A) ..............................................................51
INSR (Interrupt Status Register, Page 0xa43, Address 0x1D) ........................................................................52
8.5.19.
8.5.20.
PAGSR (Page Select Register, Page 0xa43, Address 0x1F) ...........................................................................53
8.5.21.
PHYSCR (PHY Special Config Register, Page 0xa46, Address 0x14)............................................................53
8.5.22.
LCR (LED Control Register, Page 0xd04, Address 0x10) ..............................................................................53
EEELCR (EEE LED Control Register, Page 0xd04, Address 0x11)...............................................................54
8.5.23.
8.5.24.
FLCR (Fiber LED Control Register, Page 0xd04, Address 0x12) ..................................................................54
Integrated 10/100/1000M Ethernet Precision Transceiver
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Track ID: JATR-8275-15 Rev. 1.2
RTL8211FS(I)(-VS)
Datasheet
MIICR (MII Control Register, Page 0xd08, Address 0x15) ............................................................................54
8.5.25.
INTBCR (INTB Pin Control Register, Page 0xd40, Address 0x16) ................................................................55
8.5.26.
PTP_CTL (PTP Control Register, Page 0xe40, Address 0x10) ......................................................................55
8.5.27.
PTP_INER (PTP Interrupt Enable Register, Page 0xe40, Address 0x11) ......................................................56
8.5.28.
PTP_INSR (PTP Interrupt Status Register, Page 0xe40, Address 0x12) ........................................................56
8.5.29.
SYNCE_CTL (Sync-E Control Register, Page 0xe40, Address 0x13) .............................................................57
8.5.30.
PTP_CLK_CFG (PTP Clock Config Register, Page 0xe41, Address 0x10) ...................................................57
8.5.31.
PTP_CFG_NS_LO (PTP Time Config Nano-Sec Low Register, Page 0xe41, Address 0x11)........................58
8.5.32.
PTP_CFG_NS_HI (PTP Time Config Nano-Sec High Register, Page 0xe41, Address 0x12)........................58
8.5.33.
PTP_CFG_S_LO (PTP Time Config Sec Low Register, Page 0xe41, Address 0x13).....................................58
8.5.34.
PTP_CFG_S_MI (PTP Time Config Sec Mid Register, Page 0xe41, Address 0x14) .....................................59
8.5.35.
PTP_ CFG_S_HI (PTP Time Config Sec High Register, Page 0xe41, Address 0x15) ...................................59
8.5.36.
PTP_TAI_CFG (PTP Application I/F Config Register, Page 0xe42, Address 0x10)......................................59
8.5.37.
PTP_TRIG_CFG (PTP Trigger Config Register, Page 0xe42, Address 0x11)...............................................60
8.5.38.
PTP_TAI_STA (PTP Application I/F Status Register, Page 0xe42, Address 0x12)........................................61
8.5.39.
PTP_TAI_TS_NS_LO (PTP TAI Timestamp Nano-Sec Low Register, Page 0xe42, Address 0x13)...............61
8.5.40.
PTP_TAI_TS_NS_HI (PTP TAI Timestamp Nano-Sec High Register, Page 0xe42, Address 0x14)...............62
8.5.41.
PTP_TAI_TS_S_LO (PTP TAI Timestamp Sec Low Register, Page 0xe42, Address 0x15)............................62
8.5.42.
PTP_TAI_TS_S_HI (PTP TAI Timestamp Sec High Register, Page 0xe42, Address 0x16) ...........................62
8.5.43.
PTP_TRX_TS_STA (PTP TxRx Timestamp Status Register, Page 0xe43, Address 0x10) ..............................62
8.5.44.
PTP_TRX_TS_INFO (PTP TxRx Timestamp Info Register, Page 0xe44, Address 0x10) ...............................63
8.5.45.
PTP_TRX_TS_SH (PTP TxRx Timestamp Source Hash Register, Page 0xe44, Address 0x11) .....................63
8.5.46.
PTP_TRX_TS_SID (PTP TxRx Timestamp Seq ID Register, Page 0xe44, Address 0x12)..............................64
8.5.47.
PTP_ TRX_TS NS_LO (PTP TxRx Timestamp Nano-Sec Low Register, Page 0xe44, Address 0x13)............64
8.5.48.
PTP_ TRX_TS NS_HI (PTP TxRx Timestamp Nano-Sec High Register, Page 0xe44, Address 0x14)............64
8.5.49.
PTP_ TRX_TS S_LO (PTP TxRx Timestamp Sec Low Register, Page 0xe44, Address 0x15) ........................64
8.5.50.
PTP_ TRX_TS S_MI (PTP TxRx Timestamp Sec Mid Register, Page 0xe44, Address 0x16) .........................65
8.5.51.
PTP_ TRX_TS S_HI (PTP TxRx Timestamp Sec High Register, Page 0xe44, Address 0x17) ........................65
8.5.52.
PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) ....................................................................65
8.5.53.
PS1R (PCS Status1 Register, MMD Device 3, Address 0x01) ........................................................................65
8.5.54.
EEECR (EEE Capability Register, MMD Device 3, Address 0x14)................................................................66
8.5.55.
EEEWER (EEE Wake Error Register, MMD Device 3, Address 0x16) ..........................................................66
8.5.56.
EEEAR (EEE Advertisement Register, MMD Device 7, Address 0x3c) ..........................................................66
8.5.57.
EEELPAR (EEE Link Partner Ability Register, MMD Device 7, Address 0x3d)............................................67
8.5.58.
Fiber BMCR (Fiber Basic Mode Control Register, Address 0x00).................................................................68
8.5.59.
Fiber BMSR (Basic Mode Status Register, Address 0x01)..............................................................................69
8.5.60.
1000Base-X ANAR (1000Base-X Auto-Negotiation Advertising Register, Address 0x04)..............................70
8.5.61.
1000Base-X ANLPAR (1000Base-X Auto-Negotiation Link Partner Ability Register, Address 0x05) ...........71
8.5.62.
Fiber ESR (Fiber Extended Status Register, Address 0x0F) ...........................................................................71
8.5.63.
SERDES INER (SERDES Interrupt Enable Register, Page 0xde1, Address 0x11) .........................................72
8.5.64.
SERDES INSR (SERDES Interrupt Status Register, Page 0xde1, Address 0x12)...........................................72
8.5.65.
SGMII ANARSEL (SGMII Auto-Negotiation Advertising Register Select, Page 0xd08, Address 0x14).........73
8.5.66.
SGMII ANAR (SGMII Auto-Negotiation Advertising Register, Page 0xd08, Address 0x10)..........................73
8.5.67.
8.5.68.
SGMII ANLPAR (SGMII Auto-Negotiation Link Partner Ability Register, Page 0xdc0, Address 0x15)........74
SWITCHING REGULATOR..........................................................................................................................................75
POWER SEQUENCE .....................................................................................................................................................75
CHARACTERISTICS.................................................................................................................................................77
10.1. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................77
10.2. RECOMMENDED OPERATING CONDITIONS .................................................................................................................77
10.3. CRYSTAL REQUIREMENTS..........................................................................................................................................78
10.4. OSCILLATOR/EXTERNAL CLOCK REQUIREMENTS ......................................................................................................78
10.5. DC CHARACTERISTICS...............................................................................................................................................79
9.1.
9.
10.
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10.6.
RTL8211FS(I)(-VS)
Datasheet
SGMII CHARACTERISTICS .........................................................................................................................................80
SGMII Differential Transmitter Characteristics .............................................................................................80
SGMII Differential Receiver Characteristics ..................................................................................................81
1000BASE-X CHARACTERISTICS................................................................................................................................82
1000Base-X Differential Transmitter Characteristics.....................................................................................82
1000Base-X Differential Receiver Characteristics..........................................................................................83
10.8. AC CHARACTERISTICS...............................................................................................................................................84
MDC/MDIO Timing ........................................................................................................................................84
RGMII Timing Modes......................................................................................................................................85
SGMII Timing Modes ......................................................................................................................................88
MECHANICAL DIMENSIONS.................................................................................................................................90
11.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................90
ORDERING INFORMATION...................................................................................................................................91
10.6.1.
10.6.2.
10.7.1.
10.7.2.
10.8.1.
10.8.2.
10.8.3.
10.7.
11.
12.
List of Tables
TABLE 1. TRANSCEIVER INTERFACE............................................................................................................................................10
TABLE 2. CLOCK..........................................................................................................................................................................10
TABLE 3. RGMII .........................................................................................................................................................................11
TABLE 4. SERDES........................................................................................................................................................................11
TABLE 5. RESET...........................................................................................................................................................................11
TABLE 6. MODE SELECTION ........................................................................................................................................................12
TABLE 7. LED DEFAULT SETTINGS .............................................................................................................................................12
TABLE 8. REGULATOR AND REFERENCE......................................................................................................................................13
TABLE 9. POWER AND GROUND...................................................................................................................................................13
TABLE 10. MANAGEMENT INTERFACE ..........................................................................................................................................14
TABLE 11. CONFIG PINS VS. CONFIGURATION REGISTER............................................................................................................22
TABLE 12. CONFIGURATION REGISTER DEFINITIONS ....................................................................................................................22
TABLE 13. MANAGEMENT FRAME FORMAT ..................................................................................................................................25
TABLE 14. MANAGEMENT FRAME DESCRIPTION...........................................................................................................................25
TABLE 15. 1000BASE-T BASE AND NEXT PAGE BIT ASSIGNMENTS..............................................................................................28
TABLE 16. LED DEFAULT DEFINITIONS........................................................................................................................................33
TABLE 17. LED REGISTER TABLE.................................................................................................................................................33
TABLE 18. LED CONFIGURATION TABLE 1 ...................................................................................................................................34
TABLE 19. LED CONFIGURATION TABLE 2 ...................................................................................................................................34
TABLE 20. REGISTER ACCESS TYPES ............................................................................................................................................37
TABLE 21. UTP REGISTER MAPPING AND DEFINITIONS................................................................................................................37
TABLE 22. MMD REGISTER MAPPING AND DEFINITION ...............................................................................................................39
TABLE 23. FIBER REGISTERS MAPPING AND DEFINITIONS ............................................................................................................39
TABLE 24. SERDES REGISTERS MAPPING AND DEFINITIONS.......................................................................................................39
TABLE 25. BMCR (BASIC MODE CONTROL REGISTER, ADDRESS 0X00) ......................................................................................40
TABLE 26. BMSR (BASIC MODE STATUS REGISTER, ADDRESS 0X01)..........................................................................................41
TABLE 27. PHYID1 (PHY IDENTIFIER REGISTER 1, ADDRESS 0X02) ...........................................................................................42
TABLE 28. PHYID2 (PHY IDENTIFIER REGISTER 2, ADDRESS 0X03) ...........................................................................................43
TABLE 29. ANAR (AUTO-NEGOTIATION ADVERTISING REGISTER, ADDRESS 0X04)....................................................................43
TABLE 30. ANLPAR (AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER, ADDRESS 0X05) ...............................................44
TABLE 31. ANER (AUTO-NEGOTIATION EXPANSION REGISTER, ADDRESS 0X06)........................................................................44
TABLE 32. ANNPTR (AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER, ADDRESS 0X07).................................................45
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RTL8211FS(I)(-VS)
Datasheet
TABLE 33. ANNPRR (AUTO-NEGOTIATION NEXT PAGE RECEIVE REGISTER, ADDRESS 0X08) ...................................................45
TABLE 34. GBCR (1000BASE-T CONTROL REGISTER, ADDRESS 0X09) .......................................................................................46
TABLE 35. GBSR (1000BASE-T STATUS REGISTER, ADDRESS 0X0A)..........................................................................................46
TABLE 36. MACR (MMD ACCESS CONTROL REGISTER, ADDRESS 0X0D) ..................................................................................47
TABLE 37. MAADR (MMD ACCESS ADDRESS DATA REGISTER, ADDRESS 0X0E) ......................................................................47
TABLE 38. GBESR (1000BASE-T EXTENDED STATUS REGISTER, ADDRESS 0X0F)......................................................................48
TABLE 39. INER (INTERRUPT ENABLE REGISTER, PAGE 0XA42, ADDRESS 0X12)........................................................................49
TABLE 40. PHYCR1 (PHY SPECIFIC CONTROL REGISTER 1, PAGE 0XA43, ADDRESS 0X18)........................................................50
TABLE 41. PHYCR2 (PHY SPECIFIC CONTROL REGISTER 2, PAGE 0XA43, ADDRESS 0X19)........................................................51
TABLE 42. PHYSR (PHY SPECIFIC STATUS REGISTER, PAGE 0XA43, ADDRESS 0X1A) ...............................................................51
TABLE 43. INSR (INTERRUPT STATUS REGISTER, PAGE 0XA43, ADDRESS 0X1D)........................................................................52
TABLE 44. PAGSR (PAGE SELECT REGISTER, PAGE 0XA43, ADDRESS 0X1F) ..............................................................................53
TABLE 45. PHYSCR (PHY SPECIAL CONFIG REGISTER, PAGE 0XA46, ADDRESS 0X14) ..............................................................53
TABLE 46. LCR (LED CONTROL REGISTER, PAGE 0XD04, ADDRESS 0X10) .................................................................................53
TABLE 47. EEELCR (EEE LED CONTROL REGISTER, PAGE 0XD04, ADDRESS 0X11) .................................................................54
TABLE 48. FLCR (FIBER LED CONTROL REGISTER, PAGE 0XD04, ADDRESS 0X12).....................................................................54
TABLE 49. MIICR (MII CONTROL REGISTER, PAGE 0XD08, ADDRESS 0X15)...............................................................................54
TABLE 50. INTBCR (INTB PIN CONTROL REGISTER, PAGE 0XD40, ADDRESS 0X16) ..................................................................55
TABLE 51. PTP_CTL (PTP CONTROL REGISTER, PAGE 0XE40, ADDRESS 0X10) .........................................................................55
TABLE 52. PTP_INER (PTP INTERRUPT ENABLE REGISTER, PAGE 0XE40, ADDRESS 0X11)........................................................56
TABLE 53. PTP_INSR (PTP INTERRUPT STATUS REGISTER, PAGE 0XE40, ADDRESS 0X12) ........................................................56
TABLE 54. SYNCE_CTL (SYNC-E CONTROL REGISTER, PAGE 0XE40, ADDRESS 0X13) .............................................................57
TABLE 55. PTP_CLK_CFG (PTP CLOCK CONFIG REGISTER, PAGE 0XE41, ADDRESS 0X10) ......................................................57
TABLE 56. PTP_CFG_NS_LO (PTP TIME CONFIG NANO-SEC LOW REGISTER, PAGE 0XE41, ADDRESS 0X11)...........................58
TABLE 57. PTP_CFG_NS_HI (PTP TIME CONFIG NANO-SEC HIGH REGISTER, PAGE 0XE41, ADDRESS 0X12)...........................58
TABLE 58. PTP_CFG_S_LO (PTP TIME CONFIG SEC LOW REGISTER, PAGE 0XE41, ADDRESS 0X13).........................................58
TABLE 59. PTP_CFG_S_MI (PTP TIME CONFIG SEC MID REGISTER, PAGE 0XE41, ADDRESS 0X14)..........................................59
TABLE 60. PTP_S_HI (PTP TIME CONFIG SEC HIGH REGISTER, PAGE 0XE41, ADDRESS 0X15) ..................................................59
TABLE 61. PTP_TAI_CFG (PTP APPLICATION I/F CONFIG REGISTER, PAGE 0XE42, ADDRESS 0X10) ........................................59
TABLE 62. PTP_TRIG_CFG (PTP TRIGGER CONFIG REGISTER, PAGE 0XE42, ADDRESS 0X11) ..................................................60
TABLE 63. PTP_TAI_STA (PTP APPLICATION I/F STATUS REGISTER, PAGE 0XE42, ADDRESS 0X12) ........................................61
TABLE 64. PTP_TAI_TS_NS_LO (PTP TAI TIMESTAMP NANO-SEC LOW REGISTER, PAGE 0XE42, ADDRESS 0X13)................61
TABLE 65. PTP_TAI_TS_NS_HI (PTP TAI TIMESTAMP NANO-SEC HIGH REGISTER, PAGE 0XE42, ADDRESS 0X14) ................62
TABLE 66. PTP_S_LO (PTP TIME CONFIG SEC LOW REGISTER, PAGE 0XE41, ADDRESS 0X13) ..................................................62
TABLE 67. PTP_S_MI (PTP TIME CONFIG SEC MID REGISTER, PAGE 0XE41, ADDRESS 0X14) ...................................................62
TABLE 68. PTP_TRX_TS_STA (PTP TXRX TIMESTAMP STATUS REGISTER, PAGE 0XE43, ADDRESS 0X10)..............................62
TABLE 69. PTP_TRX_TS_INFO (PTP TXRX TIMESTAMP INFO REGISTER, PAGE 0XE44, ADDRESS 0X10).................................63
TABLE 70. PTP_TRX_TS_SH (PTP TXRX TIMESTAMP SOURCE HASH REGISTER, PAGE 0XE44, ADDRESS 0X11)......................63
TABLE 71. PTP_TRX_TS_SID (PTP TXRX TIMESTAMP SEQ ID REGISTER, PAGE 0XE44, ADDRESS 0X12)................................64
TABLE 72. PTP_ TRX_TS NS_LO (PTP TXRX TIMESTAMP NANO-SEC LOW REGISTER, PAGE 0XE44, ADDRESS 0X13) ............64
TABLE 73. PTP_ TRX_TS NS_HI (PTP TXRX TIMESTAMP NANO-SEC HIGH REGISTER, PAGE 0XE44, ADDRESS 0X14) ............64
TABLE 74. PTP_ TRX_TS S_LO (PTP TXRX TIMESTAMP SEC LOW REGISTER, PAGE 0XE44, ADDRESS 0X15)..........................64
TABLE 75. PTP_ TRX_TS S_MID (PTP TXRX TIMESTAMP SEC MID REGISTER, PAGE 0XE44, ADDRESS 0X16) ........................65
TABLE 76. PTP_ TRX_TS S_LO (PTP TXRX TIMESTAMP SEC HIGH REGISTER, PAGE 0XE44, ADDRESS 0X17) .........................65
TABLE 77. PC1R (PCS CONTROL 1 REGISTER, MMD DEVICE 3, ADDRESS 0X00)........................................................................65
TABLE 78. PS1R (PCS STATUS 1 REGISTER, MMD DEVICE 3, ADDRESS 0X01)...........................................................................65
TABLE 79. EEECR (EEE CAPABILITY REGISTER, MMD DEVICE 3, ADDRESS 0X14) ...................................................................66
TABLE 80. EEEWER (EEE WAKE ERROR REGISTER, MMD DEVICE 3, ADDRESS 0X16).............................................................66
TABLE 81. EEEAR (EEE ADVERTISEMENT REGISTER, MMD DEVICE 7, ADDRESS 0X3C)...........................................................66
TABLE 82. EEELPAR (EEE LINK PARTNER ABILITY REGISTER, MMD DEVICE 7, ADDRESS 0X3D)............................................67
TABLE 83. FIBER BMCR (FIBER BASIC MODE CONTROL REGISTER, ADDRESS 0X00)..................................................................68
TABLE 84. FIBER BMSR (FIBER BASIC MODE STATUS REGISTER, ADDRESS 0X01) .....................................................................69
TABLE 85. 1000BASE-X ANAR (AUTO-NEGOTIATION ADVERTISING REGISTER, ADDRESS 0X04) ..............................................70
TABLE 86. 1000BASE-X ANLPAR (AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER, ADDRESS 0X05)..........................71
Integrated 10/100/1000M Ethernet Precision Transceiver
viii
Track ID: JATR-8275-15 Rev. 1.2
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