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IGBT数据手册.pdf
MITSUBISHI SEMICONDUCTOR
MITSUBISHI SEMICONDUCTOR
PS21865/-A
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
TRANSFER-MOLD TYPE
INSULATED TYPE
PS21865
INTEGRATED POWER FUNCTIONS
600V/20A low-loss 5th generation IGBT inverter bridge for
3 phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). (Fig.3)
• Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
• Input interface : 5V line CMOS/TTL compatible. (High Active)
• UL Approved : Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
Dimensions in mm
27×2.8(=75.6)
2.8±0.3
(8.5)(2.4)
1
2
3
4
5
(14.4)
6
8
7
(2.5)
109
(2.4)
(17.6)
12
11
13
14
15
16
17
18
19
20
21
)
1
(
C
Heat sink side
(2.2)
)
5
4
(
.
)
1
3
(
.
2-f4.5±0.2
27
28
30
31
29
32
33
35
34
)
5
6
4
(
.
)
5
3
(
.
(0.6)
(2)
41
Type name , Lot No.
22
23
24
25
26
8.5±0.3
10±0.3
10±0.3
10±0.3
20±0.3
67±0.3
79±0.5
A
B
TERMINAL CODE
1. UP
2. VP1
3. VUFB
4. VUFS
5. VP
6. VP1
7. VVFB
8. VVFS
9. WP
10. VP1
11. VPC
12. VWFB
13. VWFS
14. VN1
15. VNC
16. CIN
17. CFO
18. FO
19. UN
20. VN
21. WN
22. P
23. U
24. V
25. W
26. N
DUMMY TERMINAL CODE
35. UNG
36. VNC
37. VNO
38. WNG
39. VNG
40. W
41. P
27. VPC
28. UPG
29. P
30. VPC
31. VPG
32. U
33. WPG
34. V
)
°
5
~
0
(
1.7±0.05
0.8±0.2
.
5
0
±
6
1
.
5
.
0
±
4
1
2
.
)
1
1
(
)
0
1
(
)
5
1
(
.
5
.
0
±
4
3
1
.
(1.5)
3.8±0.2
1.9±0.05
1±0.2
.
5
0
±
6
1
.
X
A
M
5
0
.
i
s
n
a
m
e
r
r
e
d
o
s
r
a
u
g
e
r
r
I
l
l
i
s
n
a
m
e
r
r
e
d
o
s
r
a
u
g
e
r
r
I
l
l
X
A
M
5
0
.
36
37
38
39
40
)
0
1
(
)
5
6
.
4
(
)
5
3
(
.
(0.6)
(2)
)
9
2
(
.
5
.
0
±
1
3
5
.
0
±
9
4
3
.
5
.
0
±
5
1
1
.
.
.
5
0
±
8
2
1
.
5
0
±
)
0
6
1
(
.
.
5
0
±
7
Heat sink side
3.25MAX
1.85MAX
Detail : A
(t=0.7)
Detail : B
(t=0.7)
Detail : C
-A : Long terminal type (16.0mm)
Jul. 2003
✽
✽
MITSUBISHI SEMICONDUCTOR
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
C1 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
Inrush current
limiter circuit
P
High-side input (PWM)
(5V line)
(Note 1,2)
C
B
U
–
C
B
U
+
C
B
V
–
C
B
V
+
C
B
W
–
C
B
W
+
Input signal
conditioning
Input signal
conditioning
Input signal
conditioning
Level shifter
Level shifter Level shifter
Protection
circuit (UV)
Protection
circuit (UV)
Protection
circuit (UV)
Drive circuit
Drive circuit Drive circuit
C2
C1
(Note 6)
DIP-IPM
AC line input
C
Z
(Note 4)
Fig. 3
N1
N
VNC
CIN
H-side IGBTS
U
V
W
M
AC line output
L-side IGBTS
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
Input signal conditioning
Fo logic
Drive circuit
Protection
circuit
Control supply
Under-Voltage
protection
Low-side input (PWM)
(5V line)
(Note 1, 2)
FO CFO
Fault output (5V line)
(Note 3, 5)
VNC
VD
(15V line)
Note1: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
3: This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance.
(see also Fig. 8)
4: The wiring between the power DC link capacitor and the PN1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these PN1 DC power input pins.
5: Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.))
6: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
P
Drive circuit
H-side IGBTS
L-side IGBTS
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
U
V
W
SC Protection
Trip Level
External protection circuit
N1
Shunt Resistor
A
N
(Note 1)
C R
C
VNC
CIN
B
(Note 2)
Drive circuit
Protection circuit
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Collector current
waveform
0
2
tw (µs)
Jul. 2003
MITSUBISHI SEMICONDUCTOR
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Parameter
Condition
Symbol
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C) however, to en-
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Tf = 25°C
Tf = 25°C, less than 1ms
Tf = 25°C, per 1 chip
Applied between P-N
Applied between P-N
Ratings
450
500
600
20
40
52.6
Unit
V
V
V
A
A
W
°C
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ Tf ≤ 100°C).
(Note 1)
–20~+125
CONTROL (PROTECTION) PART
Symbol
VD
VDB
VIN
VFO
IFO
VSC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP-VPC, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
TOTAL SYSTEM
Symbol
VCC(PROT)
Tf
Tstg
Viso
Parameter
Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
Storage temperature
Isolation voltage
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Ratings
20
20
–0.5~VD+0.5
–0.5~VD+0.5
1
–0.5~VD+0.5
Ratings
400
–20~+100
–40~+125
2500
Unit
V
V
V
V
mA
V
Unit
V
°C
°C
Vrms
Note 2 : Tf MEASUREMENT POINT
Al Board Specification :
Dimensions : 100✕ 100✕ 10mm, Finishing : 12s, Warp : –50~100µm
Control Terminals
Groove
18mm
13.5mm
DIP-IPM
AI board
P
U
V W
Power Terminals
N
FWDi Chip
IGBT Chip
Temp. measurement point
(inside the AI board)
Temp. measurement point
(inside the AI board)
Silicon-grease should be applied evenly with a thickness of 100~200µm
Jul. 2003
MITSUBISHI SEMICONDUCTOR
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
Parameter
Unit
°C/W
Rth(j-f)Q
°C/W
Rth(j-f)F
Note 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Junction to case thermal
resistance (Note 3)
Max.
1.90
3.00
Min.
—
—
Condition
Limits
Typ.
—
—
and heat-sink.
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
Collector-emitter saturation
voltage
FWDi forward voltage
VD = VDB = 15V
VIN = 5V
Tj = 25°C, –IC = 20A, VIN = 0V
IC = 20A, Tj = 25°C
IC = 20A, Tj = 125°C
Switching times
VCC = 300V, VD = VDB = 15V
IC = 20A, Tj = 125°C, VIN = 0 ↔ 5V
Inductive load (upper-lower arm)
Collector-emitter cut-off
current
VCE = VCES
Tj = 25°C
Tj = 125°C
Limits
Typ.
1.60
1.70
1.50
1.30
0.30
0.40
1.60
0.50
—
—
Max.
2.10
2.20
2.00
1.90
—
0.60
2.20
0.80
1
10
Min.
—
—
—
0.70
—
—
—
—
—
—
Unit
V
V
µs
µs
µs
µs
µs
mA
Unit
mA
mA
mA
mA
V
V
V
mA
V
V
V
V
ms
V
V
Jul. 2003
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
ID
Circuit current
Total of VP1-VPC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Total of VP1-VPC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
VD = VDB = 15V
VIN = 5V
VD = VDB = 15V
VIN = 0V
VSC = 0V, FO circuit pull-up to 5V with 10kΩ
VSC = 1V, IFO = 1mA
Tj = 25°C, VD = 15V (Note 4)
VIN = 5V
Fault output voltage
Short circuit trip level
Input current
VFOH
VFOL
VSC(ref)
IIN
UVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
Fault output pulse width
ON threshold voltage
OFF threshold voltage
Supply circuit under-voltage
protection
Trip level
Reset level
Trip level
Reset level
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
(Note 5)
Tj ≤ 125°C
CFO = 22nF
level is less than 34 A.
5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕
10-6 ✕
tFO [F].
Limits
Typ.
—
—
—
—
—
—
0.48
1.5
—
—
—
—
1.8
2.3
1.4
Max.
5.00
0.40
7.00
0.55
—
0.95
0.53
2.0
12.0
12.5
12.5
13.0
—
2.6
2.1
Min.
—
—
—
—
4.9
—
0.43
1.0
10.0
10.5
10.3
10.8
1.0
2.1
0.8
MITSUBISHI SEMICONDUCTOR
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Condition
Mounting torque
Weight
Heat-sink flatness
Mounting screw : M4
Recommended 1.18 N·m
(Note 6)
Limits
Typ.
—
65
—
Min.
0.98
—
–50
Max.
1.47
—
100
Unit
N·m
g
µm
Note 6: Measurement point of heat-sink flatness
–+
Measurement location
3mm
Heat-sink side
–
+
Heat-sink side
RECOMMENDED OPERATION CONDITIONS
Parameter
Condition
Applied between P-N
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Symbol
VCC
VD
VDB
∆VD, ∆VDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
IO
Allowable r.m.s. current
For each input signal, Tf ≤ 100°C
Tf ≤ 100°C, Tj ≤ 125°C
VCC = 300V, VD = 15V, fc = 10kHz
P.F = 0.8, sinusoidal
Tj ≤ 125°C, Tf ≤ 100°C
ON
between VNC-N (including surge)
PWIN
VNC
Note 7 : The allowable r.m.s. current value depends on the actual application conditions.
Minimum input pulse width
VNC variation
8 : The input pulse width less than PWIN might make no response.
(Note 7)
(Note 8)
Limits
Typ.
300
15.0
15.0
—
—
5
—
—
—
Min.
0
13.5
13.0
–1
2
—
—
300
–5.0
Max.
400
16.5
18.5
1
—
—
12
—
5.0
Unit
V
V
V
V/µs
µs
kHz
Arms
ns
V
Jul. 2003
MITSUBISHI SEMICONDUCTOR
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
VUFB
VUFS
VP1
UP
VVFB
VVFS
VP1
VP
VWFB
VWFS
VP1
WP
VPC
HVIC1
VCC
VB
IN
HO
COM
VS
HVIC2
VCC
VB
IN
HO
COM
VS
HVIC3
VCC
VB
IN
HO
COM
VS
LVIC
VN1
VCC
UN
VN
WN
Fo
VNC
UN
VN
WN
Fo
GND
UOUT
VOUT
WOUT
VNO
CIN
CFO
DIP-IPM
IGBT1
Di1
IGBT2
Di2
IGBT3
Di3
IGBT4
Di4
IGBT5
IGBT6
Di5
Di6
CFO
CIN
P
U
V
W
N
Jul. 2003
MITSUBISHI SEMICONDUCTOR
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-arms only)
(With the external shunt resistance and CR connection)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. Hard IGBT gate interrupt.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input “L” : IGBT OFF state.
a7. Input “H” : IGBT ON state, but during the FO active signal period the IGBT doesn’t turn ON.
a8. IGBT OFF state.
Lower-arms control
input
Protection circuit state
Internal IGBT gate
a1
Output current Ic
Sense voltage of the
shunt resistance
Error output Fo
a5
a6
a7
SET
RESET
a3
a2
SC
a4
a8
SC reference voltage
CR circuit time
constant DELAY
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO operation starts.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
SET
RESET
Control supply voltage VD
UVDr
b1
UVDt
b2
Output current Ic
Error output Fo
b6
b7
b3
b4
b5
Jul. 2003
MITSUBISHI SEMICONDUCTOR
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
[C] Under-Voltage Protection (Upper-arm, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input condition, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
SET
RESET
Control supply voltage VDB
UVDBr
c1
UVDBt
c3
c5
c2
c4
c6
Output current Ic
Error output Fo
High-level (no fault output)
Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT
5V line
CPU
10kΩ
DIP-IPM
UP,VP,WP,UN,VN,WN
2.5kΩ (min)
Fo
VNC(Logic)
Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in
the application and the wiring impedance of the application’s printed circuit board.
The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external
filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
Fig. 7 RECOMMENDED WIRING OF SHUNT RESISTANCE
Wiring inductance should be less than 10nH.
DIP-IPM
width=3mm, thickness=100µm, length=17mm
in copper pattern (rough standard)
VNC
N
Shunt resistor
Please make the connection point
as close as possible to the terminal
of shunt resistor.
Jul. 2003
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