JESD209-4(LPDDR4协议).pdf

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1 Scope

2 Package Ballout & Pin Definition

2.1 Pad Order

2.2 Package Ballout

2.3 Pad Definition and Description

3 Functional Description

3.1 LPDDR4 SDRAM Addressing

3.2 Simplified LPDDR4 State Diagram

3.3 Power-up, Initialization and Power-off Procedure

3.4 Mode Register Definition

4 Command Definitions and Timing Diagrams

4.1 Activate Command

4.2 8-Bank Device Operation

4.3 Read and Write Access Operations

4.4 Read Preamble and Postamble

4.5 Burst Read Operation

4.6 tDQSCK Timing Table

4.7 Write Preamble and Postamble

4.8 Burst Write Operation

4.9 Masked Write Operation

4.10 LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) Function

4.11 Pre-Charge Operation

4.12 Refresh command

4.13 Self Refresh Operation

4.14 Self Refresh Abort

4.15 MRR, MRW, MPC Command during tXSR, tRFC

4.16 Mode Register Read (MRR)

4.17 Mode Register Write (MRW) Operation

4.18 VREF Current Generator (VRCG)

4.19 CA VREF Training

4.20 DQ VREF Training

4.21 Command Bus Training

4.22 Frequency Set Point

4.23 Mode Reister Write-WR Leveling Mode

4.24 RD DQ Calibration

4.25 DQS-DQ Training

4.26 DQS Interval Oscillator

4.27 READ Preamble Training

4.28 Multi-Purpose Command (MPC)

4.29 Thermal Offset

4.30 Temperature Sensor

4.31 ZQ Calibration

4.32 Pull Up/Pull Down Driver Characteristics and Calibration

4.33 On Die Termination (ODT) for Command/Address Bus

4.34 On-Die Termination (ODT)

4.35 On-Die Termination (ODT) for DQ, DQS, and DMI

4.36 Power-Down Mode

4.37 Input Clock Stop and Frequency Change

4.38 Truth Tables

4.39 TRR Mode - Target Row Refresh

4.40 Post Package Repair (PPR)

5 Absolute Maximum DC Ratings

6 AC and DC Operating Conditions

6.1 Recommended DC Operating Conditions

7 AC and DC Input/Output Measurement Levels

7.1 V High speed LVCMOS (HS_LLVCMOS)

7.2 Differential Input Cross Point Voltage

7.3 AC/DC Input level for ODT input

7.4 Single Ended Output Slew Rate

7.5 Overshoot and Undershoot for LVSTL

7.6 LPDDR4 Driver Output Timing Reference load

7.7 LVSTL(Low Voltage Swing Terminated Logic) IO System

8 Input/Output Capacitance

9 IDD Specification Parameters and Test Conditions

9.1 IDD Measurement Conditions

9.2 IDD Specifications

10 Electrical Characteristics and AC Timing

10.1 Clock Timing

10.2 Core Timing

10.3 Temperature Derating for AC timing

10.4 CA Rx voltage and timing

10.5 DRAM Data Timing

10.6 DQ Rx Voltage and Timing

Standards Improvement Form

JEDEC STANDARD Low Power Double Data Rate 4 (LPDDR4) JESD209-4 AUGUST 2014 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an No claims to be in conformance with this standard may be made unless all requirements stated in the standard are ANSI standard. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative met. contact information. Published by ©JEDEC Solid State Technology Association 2014 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC

PLEASE! DON'T VIOLATE THE LAW! This document is copyrighted by the JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street, Suite 240 South Arlington, Virginia 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information

LOW POWER DOUBLE DATA RATE 4 (LPDDR4) (From JEDEC Board Ballot JCB-14-41, formulated under the cognizance of the JC-42.6 Subcommittee on Low Power Memories.) JEDEC Standard No. 209-4 Page 1 1 Scope This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16x2channel SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3). Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the LPDDR4 standard.

JEDEC Standard No. 209-4 Page 2 1 2 2.1 Package Ballout & Pin Definition Pad Order Ch. A Top VDD2 VSS VDD1 VDD2 VSS VSSQ DQ8_A VDDQ DQ9_A VSSQ DQ10_A VDDQ DQ11_A VSSQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQS1_t_A 16 DQS1_c_A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDDQ DMI1_A VSSQ DQ12_A VDDQ DQ13_A VSSQ DQ14_A VDDQ DQ15_A VSSQ ZQ VDDQ VDD2 VDD1 VSS CA5_A CA4_A VDD2 CA3_A CA2_A VSS CK_c_A CK_t_A VDD2 CKE_A CS_A VSS CA1_A CA0_A VDD2 VSS VDD1 VSSQ DQ7_A VDDQ DQ6_A VSSQ DQ5_A VDDQ DQ4_A VSSQ DMI0_A VDDQ 41 42 43 44 45 46 47 48 ODT(ca)_A 49 50 51 52 53 54 55 56 57 58 59 60 61 62 DQS0_c_A 63 DQS0_t_A 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Ch. A Bottom VSSQ DQ3_A VDDQ DQ2_A VSSQ DQ1_A VDDQ DQ0_A VSSQ VSS VDD2 VDD1 VSS VDD2 A l e n n a h C Top BoƩom C h a n n e l B Ch. B Top VDD2 101 VSS 102 VDD1 103 VDD2 104 VSS 105 VSSQ 106 DQ8_B 107 VDDQ 108 DQ9_B 109 110 VSSQ 111 DQ10_B 112 VDDQ 113 DQ11_B 114 VSSQ 115 DQS1_t_B 116 DQS1_c_B 117 VDDQ 118 DMI1_B 119 VSSQ 120 DQ12_B 121 VDDQ 122 DQ13_B 123 VSSQ 124 DQ14_B 125 VDDQ 126 DQ15_B 127 VSSQ 128 RESET_n 129 130 131 132 133 134 135 136 137 138 139 CK_c_B 140 CK_t_B VDDQ VDD2 VDD1 VSS CA5_B CA4_B VDD2 CA3_B CA2_B VSS VDD2 CKE_B CS_B VSS CA1_B CA0_B VDD2 141 142 143 144 145 146 147 148 ODT(ca)_B VSS 149 VDD1 150 VSSQ 151 DQ7_B 152 VDDQ 153 DQ6_B 154 VSSQ 155 DQ5_B 156 VDDQ 157 DQ4_B 158 159 VSSQ 160 DMI0_B 161 VDDQ 162 DQS0_c_B 163 DQS0_t_B 164 165 166 167 168 169 170 171 172 173 174 175 176 177 Ch. B Bottom VSSQ DQ3_B VDDQ DQ2_B VSSQ DQ1_B VDDQ DQ0_B VSSQ VSS VDD2 VDD1 VSS VDD2 NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes. NOTE 2 Additional pads are allowed for DRAM mfg-specific pads (“DNU”), or additional power pads as long as the extra pads are grouped with like-named pads.

JEDEC Standard No. 209-4 Page 3 2.2 Package Ballout 2.2.1 272-ball 15mm x 15mm 0.4mm pitch, Quad-Channel POP FBGA (top view) Using Variation VFFCDB for MO-273 NOTE 1 15mm x 15mm, 0.4mm ball pitch NOTE 2 272 ball count, 36 rows NOTE 3 Top View, A1 in top left corner NOTE 4 ODT ca_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if present) are disabled in the package. NOTE 5 Package Channel a and Channel c shall be assigned to die Channel A of different DRAM die. NOTE 6 Die pad VSS and VSSQ signals are combined to VSS package balls.

JEDEC Standard No. 209-4 Page 4 2.2.2 200-ball x32 Discrete Package, 0.80mm x 0.65mm using MO-311 1 2 3 4 5 6 7 8 9 DNU DNU VSS VDD2 ZQ0 ZQ1 VDD2 10 VSS 11 12 DNU DNU 0.80mm Pitch DNU DQ0_A VDDQ DQ7_A VDDQ VDDQ DQ15_A VDDQ DQ8_A DNU VSS DQ1_A DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSS VDDQ VSS DQS0_T_A VSS VDDQ VDDQ VSS DQS1_T_A VSS VDDQ VSS DQ2_A DQS0_C_ A DQ5_A VSS VSS DQ13_A DQS1_C_ A DQ10_A VSS VDD1 DQ3_A VDDQ DQ4_A VDD2 VDD2 DQ12_A VDDQ DQ11_A VDD1 VSS ODT_CA_ A VSS VDD1 VSS VSS VDD1 VSS ZQ2 VSS VDD2 CA0_A CS1_A CS0_A VDD2 VDD2 CA2_A CA3_A CA4_A VDD2 VSS CA1_A VSS CKE0_A CKE1_A CK_t_A CK_c_A VSS CA5_A VSS VDD2 VSS VDD2 VSS CS2_A CKE2_A VSS VDD2 VSS VDD2 VDD2 VSS VDD2 VSS CS2_B CKE2_B VSS VDD2 VSS VDD2 VSS CA1_B VSS CKE0_B CKE1_B CK_T_B CK_C_B VSS CA5_B VSS VDD2 CA0_B CS1_B CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2 VSS ODT_CA_ B VSS VDD1 VSS VSS VDD1 VSS RESET_N VSS VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1 VSS DQ2_B DQS0_C_ B DQ5_B VSS VSS DQ13_B DQS1_C_ B DQ10_B VSS A B C D E F G H J K L M N P R T U V h c t i P m m 5 6 . 0 W VDDQ VSS DQS0_T_B VSS VDDQ VDDQ VSS DQS1_T_B VSS VDDQ Y VSS DQ1_B DMI0_B DQ6_B VSS VSS DQ14_B DMI1_B DQ9_B VSS AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15_B VDDQ DQ8_B DNU AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU DNU NOTE 1 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows. NOTE 2 Top View, A1 in top left corner. NOTE 3 ODT_CA_[x] balls are wired to ODT_CA)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if present) are disabled in the package. NOTE 4 ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. For 1-rank and 2-rank package those balls are NC. NOTE 5 Die pad VSS and VSSQ signals are combined to VSS package balls.

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