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Atmel_SAM-D21 资料.pdf
Introduction
Features
Table of Contents
1. Description
2. Configuration Summary
3. Ordering Information
3.1. SAM D21E
3.2. SAM D21G
3.3. SAM D21J
3.4. Device Identification
4. Block Diagram
5. Pinout
5.1. SAM D21J
5.1.1. QFN64 / TQFP64
5.1.2. UFBGA64
5.2. SAM D21G
5.2.1. QFN48 / TQFP48
5.2.2. WLCSP45
5.3. SAM D21E
5.3.1. QFN32 / TQFP32
5.3.2. WLCSP35
6. Signal Descriptions List
7. I/O Multiplexing and Considerations
7.1. Multiplexed Signals
7.2. Other Functions
7.2.1. Oscillator Pinout
7.2.2. Serial Wire Debug Interface Pinout
7.2.3. SERCOM I2C Pins
7.2.4. GPIO Clusters
7.2.5. TCC Configurations
8. Power Supply and Start-Up Considerations
8.1. Power Domain Overview
8.2. Power Supply Considerations
8.2.1. Power Supplies
8.2.2. Voltage Regulator
8.2.3. Typical Powering Schematics
8.2.4. Power-Up Sequence
8.2.4.1. Minimum Rise Rate
8.2.4.2. Maximum Rise Rate
8.3. Power-Up
8.3.1. Starting of Clocks
8.3.2. I/O Pins
8.3.3. Fetching of Initial Instructions
8.4. Power-On Reset and Brown-Out Detector
8.4.1. Power-On Reset on VDDANA
8.4.2. Brown-Out Detector on VDDANA
8.4.3. Brown-Out Detector on VDDCORE
9. Product Mapping
10. Memories
10.1. Embedded Memories
10.2. Physical Memory Map
10.3. NVM Calibration and Auxiliary Space
10.3.1. NVM User Row Mapping
10.3.2. NVM Software Calibration Area Mapping
10.3.3. Serial Number
11. Processor And Architecture
11.1. Cortex M0+ Processor
11.1.1. Cortex M0+ Configuration
11.1.2. Cortex-M0+ Peripherals
11.1.3. Cortex-M0+ Address Map
11.1.4. I/O Interface
11.1.4.1. Overview
11.1.4.2. Description
11.2. Nested Vector Interrupt Controller
11.2.1. Overview
11.2.2. Interrupt Line Mapping
11.3. Micro Trace Buffer
11.3.1. Features
11.3.2. Overview
11.4. High-Speed Bus System
11.4.1. Features
11.4.2. Configuration
11.4.3. SRAM Quality of Service
11.5. AHB-APB Bridge
11.6. PAC - Peripheral Access Controller
11.6.1. Overview
11.6.2. Register Description
11.6.2.1. PAC0 Register Description
11.6.2.1.1. Write Protect Clear
11.6.2.1.2. Write Protect Set
11.6.2.2. PAC1 Register Description
11.6.2.2.1. Write Protect Clear
11.6.2.2.2. Write Protect Set
11.6.2.3. PAC2 Register Description
11.6.2.3.1. Write Protect Clear
11.6.2.3.2. Write Protect Set
12. Peripherals Configuration Summary
13. DSU - Device Service Unit
13.1. Overview
13.2. Features
13.3. Block Diagram
13.4. Signal Description
13.5. Product Dependencies
13.5.1. IO Lines
13.5.2. Power Management
13.5.3. Clocks
13.5.4. DMA
13.5.5. Interrupts
13.5.6. Events
13.5.7. Register Access Protection
13.5.8. Analog Connections
13.6. Debug Operation
13.6.1. Principle of Operation
13.6.2. CPU Reset Extension
13.6.3. Debugger Probe Detection
13.6.3.1. Cold Plugging
13.6.3.2. Hot Plugging
13.7. Chip Erase
13.8. Programming
13.9. Intellectual Property Protection
13.10. Device Identification
13.10.1. CoreSight Identification
13.10.2. Chip Identification Method
13.11. Functional Description
13.11.1. Principle of Operation
13.11.2. Basic Operation
13.11.2.1. Initialization
13.11.2.2. Operation From a Debug Adapter
13.11.2.3. Operation From the CPU
13.11.3. 32-bit Cyclic Redundancy Check CRC32
13.11.3.1. Starting CRC32 Calculation
13.11.3.2. Interpreting the Results
13.11.4. Debug Communication Channels
13.11.5. Testing of On-Board Memories MBIST
13.11.6. System Services Availability when Accessed Externally
13.12. Register Summary
13.13. Register Description
13.13.1. Control
13.13.2. Status A
13.13.3. Status B
13.13.4. Address
13.13.5. Length
13.13.6. Data
13.13.7. Debug Communication Channel 0
13.13.8. Debug Communication Channel 1
13.13.9. Device Identification
13.13.10. CoreSight ROM Table Entry 0
13.13.11. CoreSight ROM Table Entry 1
13.13.12. CoreSight ROM Table End
13.13.13. CoreSight ROM Table Memory Type
13.13.14. Peripheral Identification 4
13.13.15. Peripheral Identification 0
13.13.16. Peripheral Identification 1
13.13.17. Peripheral Identification 2
13.13.18. Peripheral Identification 3
13.13.19. Component Identification 0
13.13.20. Component Identification 1
13.13.21. Component Identification 2
13.13.22. Component Identification 3
14. Clock System
14.1. Clock Distribution
14.2. Synchronous and Asynchronous Clocks
14.3. Register Synchronization
14.3.1. Common Synchronizer Register Synchronization
14.3.1.1. Overview
14.3.1.2. Write-Synchronization
14.3.1.3. Read-Synchronization
14.3.1.4. Completion of synchronization
14.3.1.5. Read Request
14.3.1.6. Enable Write-Synchronization
14.3.1.7. Software Reset Write-Synchronization
14.3.1.8. Synchronization Delay
14.3.2. Distributed Synchronizer Register Synchronization
14.3.2.1. Overview
14.3.2.2. General Write synchronization
14.3.2.3. General read synchronization
14.3.2.4. Completion of synchronization
14.3.2.5. Enable Write-Synchronization
14.3.2.6. Software Reset Write-Synchronization
14.3.2.7. Synchronization Delay
14.4. Enabling a Peripheral
14.5. On-demand, Clock Requests
14.6. Power Consumption vs. Speed
14.7. Clocks after Reset
15. GCLK - Generic Clock Controller
15.1. Overview
15.2. Features
15.3. Block Diagram
15.4. Signal Description
15.5. Product Dependencies
15.5.1. I/O Lines
15.5.2. Power Management
15.5.3. Clocks
15.5.4. DMA
15.5.5. Interrupts
15.5.6. Events
15.5.7. Debug Operation
15.5.8. Register Access Protection
15.5.9. Analog Connections
15.6. Functional Description
15.6.1. Principle of Operation
15.6.2. Basic Operation
15.6.2.1. Initialization
15.6.2.2. Enabling, Disabling and Resetting
15.6.2.3. Generic Clock Generator
15.6.2.4. Enabling a Generic Clock Generator
15.6.2.5. Disabling a Generic Clock Generator
15.6.2.6. Selecting a Clock Source for the Generic Clock Generator
15.6.2.7. Changing Clock Frequency
15.6.2.8. Duty Cycle
15.6.2.9. Generic Clock Output on I/O Pins
15.6.3. Generic Clock
15.6.3.1. Enabling a Generic Clock
15.6.3.2. Disabling a Generic Clock
15.6.3.3. Selecting a Clock Source for the Generic Clock
15.6.3.4. Configuration Lock
15.6.4. Additional Features
15.6.4.1. Indirect Access
15.6.4.2. Generic Clock Enable after Reset
15.6.5. Sleep Mode Operation
15.6.5.1. Sleep Walking
15.6.5.2. Run in Standby Mode
15.6.6. Synchronization
15.7. Register Summary
15.8. Register Description
15.8.1. Control
15.8.2. Status
15.8.3. Generic Clock Control
15.8.4. Generic Clock Generator Control
15.8.5. Generic Clock Generator Division
16. PM – Power Manager
16.1. Overview
16.2. Features
16.3. Block Diagram
16.4. Signal Description
16.5. Product Dependencies
16.5.1. I/O Lines
16.5.2. Power Management
16.5.3. Clocks
16.5.3.1. Main Clock
16.5.3.2. CPU Clock
16.5.3.3. AHB Clock
16.5.3.4. APBx Clocks
16.5.4. DMA
16.5.5. Interrupts
16.5.6. Events
16.5.7. Debug Operation
16.5.8. Register Access Protection
16.5.9. Analog Connections
16.6. Functional Description
16.6.1. Principle of Operation
16.6.1.1. Synchronous Clocks
16.6.1.2. Reset Controller
16.6.1.3. Sleep Mode Controller
16.6.2. Basic Operation
16.6.2.1. Initialization
16.6.2.2. Enabling, Disabling and Resetting
16.6.2.3. Selecting the Main Clock Source
16.6.2.4. Selecting the Synchronous Clock Division Ratio
16.6.2.5. Clock Ready Flag
16.6.2.6. Peripheral Clock Masking
16.6.2.7. Reset Controller
16.6.2.8. Sleep Mode Controller
16.6.2.8.1. IDLE Mode
16.6.2.8.2. STANDBY Mode
16.6.3. SleepWalking
16.6.4. DMA Operation
16.6.5. Interrupts
16.6.6. Events
16.6.7. Sleep Mode Operation
16.7. Register Summary
16.8. Register Description
16.8.1. Control
16.8.2. Sleep Mode
16.8.3. CPU Clock Select
16.8.4. APBA Clock Select
16.8.5. APBB Clock Select
16.8.6. APBC Clock Select
16.8.7. AHB Mask
16.8.8. APBA Mask
16.8.9. APBB Mask
16.8.10. APBC Mask
16.8.11. Interrupt Enable Clear
16.8.12. Interrupt Enable Set
16.8.13. Interrupt Flag Status and Clear
16.8.14. Reset Cause
17. SYSCTRL – System Controller
17.1. Overview
17.2. Features
17.3. Block Diagram
17.4. Signal Description
17.5. Product Dependencies
17.5.1. I/O Lines
17.5.2. Power Management
17.5.3. Clocks
17.5.4. Interrupts
17.5.5. Debug Operation
17.5.6. Register Access Protection
17.5.7. Analog Connections
17.6. Functional Description
17.6.1. Principle of Operation
17.6.2. External Multipurpose Crystal Oscillator (XOSC) Operation
17.6.3. 32kHz External Crystal Oscillator (XOSC32K) Operation
17.6.4. 32kHz Internal Oscillator (OSC32K) Operation
17.6.5. 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
17.6.6. 8MHz Internal Oscillator (OSC8M) Operation
17.6.7. Digital Frequency Locked Loop (DFLL48M) Operation
17.6.7.1. Basic Operation
17.6.7.1.1. Open-Loop Operation
17.6.7.1.2. Closed-Loop Operation
17.6.7.1.3. Frequency Locking
17.6.7.1.4. Frequency Error Measurement
17.6.7.1.5. Drift Compensation
17.6.7.1.6. Reference Clock Stop Detection
17.6.7.2. Additional Features
17.6.7.2.1. Dealing with Delay in the DFLL in Closed-Loop Mode
17.6.7.2.2. USB Clock Recovery Module
17.6.7.2.3. Wake from Sleep Modes
17.6.7.2.4. Accuracy
17.6.8. FDPLL96M – Fractional Digital Phase-Locked Loop Controller (DFLL96M)
17.6.8.1. Overview
17.6.8.2. Block Diagram
17.6.8.3. Principle of Operation
17.6.8.4. Initialization, Enabling, Disabling and Resetting
17.6.8.5. Reference Clock Switching
17.6.8.6. Loop Divider Ratio updates
17.6.8.7. Digital Filter Selection
17.6.9. 3.3V Brown-Out Detector Operation
17.6.9.1. 3.3V Brown-Out Detector (BOD33)
17.6.9.2. Continuous Mode
17.6.9.3. Sampling Mode
17.6.9.4. Hysteresis
17.6.10. Voltage Reference System Operation
17.6.10.1. User Control of the Voltage Reference System
17.6.11. Voltage Regulator System Operation
17.6.12. DMA Operation
17.6.13. Interrupts
17.6.14. Synchronization
17.7. Register Summary
17.8. Register Description
17.8.1. Interrupt Enable Clear
17.8.2. Interrupt Enable Set
17.8.3. Interrupt Flag Status and Clear
17.8.4. Power and Clocks Status
17.8.5. External Multipurpose Crystal Oscillator (XOSC) Control
17.8.6. 32kHz External Crystal Oscillator (XOSC32K) Control
17.8.7. 32kHz Internal Oscillator (OSC32K) Control
17.8.8. 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
17.8.9. 8MHz Internal Oscillator (OSC8M) Control
17.8.10. DFLL48M Control
17.8.11. DFLL48M Value
17.8.12. DFLL48M Multiplier
17.8.13. DFLL48M Synchronization
17.8.14. 3.3V Brown-Out Detector (BOD33) Control
17.8.15. Voltage Regulator System (VREG) Control
17.8.16. Voltage References System (VREF) Control
17.8.17. DPLL Control A
17.8.18. DPLL Ratio Control
17.8.19. DPLL Control B
17.8.20. DPLL Status
18. WDT – Watchdog Timer
18.1. Overview
18.2. Features
18.3. Block Diagram
18.4. Signal Description
18.5. Product Dependencies
18.5.1. I/O Lines
18.5.2. Power Management
18.5.3. Clocks
18.5.4. DMA
18.5.5. Interrupts
18.5.6. Events
18.5.7. Debug Operation
18.5.8. Register Access Protection
18.5.9. Analog Connections
18.6. Functional Description
18.6.1. Principle of Operation
18.6.2. Basic Operation
18.6.2.1. Initialization
18.6.2.2. Configurable Reset Values
18.6.2.3. Enabling and Disabling
18.6.2.4. Normal Mode
18.6.2.5. Window Mode
18.6.3. Additional Features
18.6.3.1. Always-On Mode
18.6.4. Interrupts
18.6.5. Synchronization
18.7. Register Summary
18.8. Register Description
18.8.1. Control
18.8.2. Configuration
18.8.3. Early Warning Interrupt Control
18.8.4. Interrupt Enable Clear
18.8.5. Interrupt Enable Set
18.8.6. Interrupt Flag Status and Clear
18.8.7. Status
18.8.8. Clear
19. RTC – Real-Time Counter
19.1. Overview
19.2. Features
19.3. Block Diagram
19.4. Signal Description
19.5. Product Dependencies
19.5.1. I/O Lines
19.5.2. Power Management
19.5.3. Clocks
19.5.4. DMA
19.5.5. Interrupts
19.5.6. Events
19.5.7. Debug Operation
19.5.8. Register Access Protection
19.5.9. Analog Connections
19.6. Functional Description
19.6.1. Principle of Operation
19.6.2. Basic Operation
19.6.2.1. Initialization
19.6.2.2. Enabling, Disabling and Resetting
19.6.3. Operating Modes
19.6.3.1. 32-Bit Counter (Mode 0)
19.6.3.2. 16-Bit Counter (Mode 1)
19.6.3.3. Clock/Calendar (Mode 2)
19.6.4. DMA Operation
19.6.5. Interrupts
19.6.6. Events
19.6.7. Sleep Mode Operation
19.6.8. Synchronization
19.6.9. Additional Features
19.6.9.1. Periodic Events
19.6.9.2. Frequency Correction
19.7. Register Summary
19.8. Register Description
19.8.1. Control - MODE0
19.8.2. Control - MODE1
19.8.3. Control - MODE2
19.8.4. Read Request
19.8.5. Event Control - MODE0
19.8.6. Event Control - MODE1
19.8.7. Event Control - MODE2
19.8.8. Interrupt Enable Clear - MODE0
19.8.9. Interrupt Enable Clear - MODE1
19.8.10. Interrupt Enable Clear - MODE2
19.8.11. Interrupt Enable Set - MODE0
19.8.12. Interrupt Enable Set - MODE1
19.8.13. Interrupt Enable Set - MODE2
19.8.14. Interrupt Flag Status and Clear - MODE0
19.8.15. Interrupt Flag Status and Clear - MODE1
19.8.16. Interrupt Flag Status and Clear - MODE2
19.8.17. Status
19.8.18. Debug Control
19.8.19. Frequency Correction
19.8.20. Counter Value - MODE0
19.8.21. Counter Value - MODE1
19.8.22. Clock Value - MODE2
19.8.23. Counter Period - MODE1
19.8.24. Compare n Value - MODE0
19.8.25. Compare n Value - MODE1
19.8.26. Alarm 0 Value - MODE2
19.8.27. Alarm n Mask - MODE2
20. DMAC – Direct Memory Access Controller
20.1. Overview
20.2. Features
20.3. Block Diagram
20.4. Signal Description
20.5. Product Dependencies
20.5.1. I/O Lines
20.5.2. Power Management
20.5.3. Clocks
20.5.4. DMA
20.5.5. Interrupts
20.5.6. Events
20.5.7. Debug Operation
20.5.8. Register Access Protection
20.5.9. Analog Connections
20.6. Functional Description
20.6.1. Principle of Operation
20.6.1.1. DMA
20.6.1.2. CRC
20.6.2. Basic Operation
20.6.2.1. Initialization
20.6.2.2. Enabling, Disabling, and Resetting
20.6.2.3. Transfer Descriptors
20.6.2.4. Arbitration
20.6.2.5. Data Transmission
20.6.2.6. Transfer Triggers and Actions
20.6.2.7. Addressing
20.6.2.8. Error Handling
20.6.3. Additional Features
20.6.3.1. Linked Descriptors
20.6.3.1.1. Adding Descriptor to the End of a List
20.6.3.1.2. Modifying a Descriptor in a List
20.6.3.1.3. Adding a Descriptor Between Existing Descriptors
20.6.3.2. Channel Suspend
20.6.3.3. Channel Resume and Next Suspend Skip
20.6.3.4. Event Input Actions
20.6.3.5. Event Output Selection
20.6.3.6. Aborting Transfers
20.6.3.7. CRC Operation
20.6.4. DMA Operation
20.6.5. Interrupts
20.6.6. Events
20.6.7. Sleep Mode Operation
20.6.8. Synchronization
20.7. Register Summary
20.8. Register Description
20.8.1. Control
20.8.2. CRC Control
20.8.3. CRC Data Input
20.8.4. CRC Checksum
20.8.5. CRC Status
20.8.6. Debug Control
20.8.7. Quality of Service Control
20.8.8. Software Trigger Control
20.8.9. Priority Control 0
20.8.10. Interrupt Pending
20.8.11. Interrupt Status
20.8.12. Busy Channels
20.8.13. Pending Channels
20.8.14. Active Channel and Levels
20.8.15. Descriptor Memory Section Base Address
20.8.16. Write-Back Memory Section Base Address
20.8.17. Channel ID
20.8.18. Channel Control A
20.8.19. Channel Control B
20.8.20. Channel Interrupt Enable Clear
20.8.21. Channel Interrupt Enable Set
20.8.22. Channel Interrupt Flag Status and Clear
20.8.23. Channel Status
20.9. Register Summary - SRAM
20.10. Register Description - SRAM
20.10.1. Block Transfer Control
20.10.2. Block Transfer Count
20.10.3. Block Transfer Source Address
20.10.4. Block Transfer Destination Address
20.10.5. Next Descriptor Address
21. EIC – External Interrupt Controller
21.1. Overview
21.2. Features
21.3. Block Diagram
21.4. Signal Description
21.5. Product Dependencies
21.5.1. I/O Lines
21.5.2. Power Management
21.5.3. Clocks
21.5.4. DMA
21.5.5. Interrupts
21.5.6. Events
21.5.7. Debug Operation
21.5.8. Register Access Protection
21.5.9. Analog Connections
21.6. Functional Description
21.6.1. Principle of Operation
21.6.2. Basic Operation
21.6.2.1. Initialization
21.6.2.2. Enabling, Disabling and Resetting
21.6.3. External Pin Processing
21.6.4. Additional Features
21.6.4.1. Non-Maskable Interrupt (NMI)
21.6.5. DMA Operation
21.6.6. Interrupts
21.6.7. Events
21.6.8. Sleep Mode Operation
21.6.9. Synchronization
21.7. Register Summary
21.8. Register Description
21.8.1. Control
21.8.2. Status
21.8.3. Non-Maskable Interrupt Control
21.8.4. Non-Maskable Interrupt Flag Status and Clear
21.8.5. Event Control
21.8.6. Interrupt Enable Clear
21.8.7. Interrupt Enable Set
21.8.8. Interrupt Flag Status and Clear
21.8.9. Wake-Up Enable
21.8.10. Configuration n
22. NVMCTRL – Non-Volatile Memory Controller
22.1. Overview
22.2. Features
22.3. Block Diagram
22.4. Signal Description
22.5. Product Dependencies
22.5.1. Power Management
22.5.2. Clocks
22.5.3. Interrupts
22.5.4. Debug Operation
22.5.5. Register Access Protection
22.5.6. Analog Connections
22.6. Functional Description
22.6.1. Principle of Operation
22.6.1.1. Initialization
22.6.2. Memory Organization
22.6.3. Region Lock Bits
22.6.4. Command and Data Interface
22.6.4.1. NVM Read
22.6.4.2. RWWEE Read
22.6.4.3. NVM Write
22.6.4.3.1. Procedure for Manual Page Writes (CTRLB.MANW=1)
22.6.4.3.2. Procedure for Automatic Page Writes (CTRLB.MANW=0)
22.6.4.4. Page Buffer Clear
22.6.4.5. Erase Row
22.6.4.5.1. Procedure for Erase Row
22.6.4.6. Lock and Unlock Region
22.6.4.7. Set and Clear Power Reduction Mode
22.6.5. NVM User Configuration
22.6.6. Security Bit
22.6.7. Cache
22.7. Register Summary
22.8. Register Description
22.8.1. Control A
22.8.2. Control B
22.8.3. NVM Parameter
22.8.4. Interrupt Enable Clear
22.8.5. Interrupt Enable Set
22.8.6. Interrupt Flag Status and Clear
22.8.7. Status
22.8.8. Address
22.8.9. Lock Section
23. PORT - I/O Pin Controller
23.1. Overview
23.2. Features
23.3. Block Diagram
23.4. Signal Description
23.5. Product Dependencies
23.5.1. I/O Lines
23.5.2. Power Management
23.5.3. Clocks
23.5.4. DMA
23.5.5. Interrupts
23.5.6. Events
23.5.7. Debug Operation
23.5.8. Register Access Protection
23.5.9. Analog Connections
23.5.10. CPU Local Bus
23.6. Functional Description
23.6.1. Principle of Operation
23.6.2. Basic Operation
23.6.2.1. Initialization
23.6.2.2. Operation
23.6.3. I/O Pin Configuration
23.6.3.1. Pin Configurations Summary
23.6.3.2. Input Configuration
23.6.3.3. Totem-Pole Output
23.6.3.4. Digital Functionality Disabled
23.6.4. PORT Access Priority
23.7. Register Summary
23.8. Register Description
23.8.1. Data Direction
23.8.2. Data Direction Clear
23.8.3. Data Direction Set
23.8.4. Data Direction Toggle
23.8.5. Data Output Value
23.8.6. Data Output Value Clear
23.8.7. Data Output Value Set
23.8.8. Data Output Value Toggle
23.8.9. Data Input Value
23.8.10. Control
23.8.11. Write Configuration
23.8.12. Peripheral Multiplexing n
23.8.13. Pin Configuration y
24. EVSYS – Event System
24.1. Overview
24.2. Features
24.3. Block Diagram
24.4. Signal Description
24.5. Product Dependencies
24.5.1. I/O Lines
24.5.2. Power Management
24.5.3. Clocks
24.5.4. DMA
24.5.5. Interrupts
24.5.6. Events
24.5.7. Debug Operation
24.5.8. Register Access Protection
24.5.9. Analog Connections
24.6. Functional Description
24.6.1. Principle of Operation
24.6.2. Basic Operation
24.6.2.1. Initialization
24.6.2.2. Enabling, Disabling and Resetting
24.6.2.3. User Multiplexer Setup
24.6.2.4. Channel Setup
24.6.2.5. Channel Path
24.6.2.5.1. Asynchronous Path
24.6.2.5.2. Synchronous Path
24.6.2.5.3. Resynchronized Path
24.6.2.6. Edge Detection
24.6.2.7. Event Generators
24.6.2.8. Channel Status
24.6.2.9. Software Event
24.6.3. Interrupts
24.6.3.1. The Overrun Channel n Interrupt
24.6.3.2. The Event Detected Channel n Interrupt
24.6.4. Sleep Mode Operation
24.7. Register Summary
24.8. Register Description
24.8.1. Control
24.8.2. Channel
24.8.3. User Multiplexer
24.8.4. Channel Status
24.8.5. Interrupt Enable Clear
24.8.6. Interrupt Enable Set
24.8.7. Interrupt Flag Status and Clear
25. SERCOM – Serial Communication Interface
25.1. Overview
25.2. Features
25.3. Block Diagram
25.4. Signal Description
25.5. Product Dependencies
25.5.1. I/O Lines
25.5.2. Power Management
25.5.3. Clocks
25.5.4. DMA
25.5.5. Interrupts
25.5.6. Events
25.5.7. Debug Operation
25.5.8. Register Access Protection
25.5.9. Analog Connections
25.6. Functional Description
25.6.1. Principle of Operation
25.6.2. Basic Operation
25.6.2.1. Initialization
25.6.2.2. Enabling, Disabling, and Resetting
25.6.2.3. Clock Generation – Baud-Rate Generator
25.6.2.3.1. Asynchronous Arithmetic Mode BAUD Value Selection
25.6.3. Additional Features
25.6.3.1. Address Match and Mask
25.6.3.1.1. Address With Mask
25.6.3.1.2. Two Unique Addresses
25.6.3.1.3. Address Range
25.6.4. DMA Operation
25.6.5. Interrupts
25.6.6. Events
25.6.7. Sleep Mode Operation
25.6.8. Synchronization
26. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
26.1. Overview
26.2. USART Features
26.3. Block Diagram
26.4. Signal Description
26.5. Product Dependencies
26.5.1. I/O Lines
26.5.2. Power Management
26.5.3. Clocks
26.5.4. DMA
26.5.5. Interrupts
26.5.6. Events
26.5.7. Debug Operation
26.5.8. Register Access Protection
26.5.9. Analog Connections
26.6. Functional Description
26.6.1.
26.6.2. Principle of Operation
26.6.3. Basic Operation
26.6.3.1. Initialization
26.6.3.2. Enabling, Disabling, and Resetting
26.6.3.3. Clock Generation and Selection
26.6.3.3.1. Synchronous Clock Operation
26.6.3.4. Data Register
26.6.3.5. Data Transmission
26.6.3.5.1. Disabling the Transmitter
26.6.3.6. Data Reception
26.6.3.6.1. Disabling the Receiver
26.6.3.6.2. Error Bits
26.6.3.6.3. Asynchronous Data Reception
26.6.3.6.4. Asynchronous Operational Range
26.6.4. Additional Features
26.6.4.1. Parity
26.6.4.2. Hardware Handshaking
26.6.4.3. IrDA Modulation and Demodulation
26.6.4.4. Break Character Detection and Auto-Baud
26.6.4.5. Collision Detection
26.6.4.6. Loop-Back Mode
26.6.4.7. Start-of-Frame Detection
26.6.4.8. Sample Adjustment
26.6.5. DMA_ Interrupts and Events
26.6.5.1. DMA Operation
26.6.5.2. Interrupts
26.6.5.3. Events
26.6.6. Sleep Mode Operation
26.6.7. Synchronization
26.7. Register Summary
26.8. Register Description
26.8.1. Control A
26.8.2. Control B
26.8.3. Baud
26.8.4. Receive Pulse Length Register
26.8.5. Interrupt Enable Clear
26.8.6. Interrupt Enable Set
26.8.7. Interrupt Flag Status and Clear
26.8.8. Status
26.8.9. Synchronization Busy
26.8.10. Data
26.8.11. Debug Control
27. SERCOM SPI – SERCOM Serial Peripheral Interface
27.1. Overview
27.2. Features
27.3. Block Diagram
27.4. Signal Description
27.5. Product Dependencies
27.5.1. I/O Lines
27.5.2. Power Management
27.5.3. Clocks
27.5.4. DMA
27.5.5. Interrupts
27.5.6. Events
27.5.7. Debug Operation
27.5.8. Register Access Protection
27.5.9. Analog Connections
27.6. Functional Description
27.6.1. Principle of Operation
27.6.2. Basic Operation
27.6.2.1. Initialization
27.6.2.2. Enabling, Disabling, and Resetting
27.6.2.3. Clock Generation
27.6.2.4. Data Register
27.6.2.5. SPI Transfer Modes
27.6.2.6. Transferring Data
27.6.2.6.1. Master
27.6.2.6.2. Slave
27.6.2.7. Receiver Error Bit
27.6.3. Additional Features
27.6.3.1. Address Recognition
27.6.3.2. Preloading of the Slave Shift Register
27.6.3.3. Master with Several Slaves
27.6.3.4. Loop-Back Mode
27.6.3.5. Hardware Controlled _SS
27.6.3.6. Slave Select Low Detection
27.6.4. DMA, Interrupts, and Events
27.6.4.1. DMA Operation
27.6.4.2. Interrupts
27.6.4.3. Events
27.6.5. Sleep Mode Operation
27.6.6. Synchronization
27.7. Register Summary
27.8. Register Description
27.8.1. Control A
27.8.2. Control B
27.8.3. Baud Rate
27.8.4. Interrupt Enable Clear
27.8.5. Interrupt Enable Set
27.8.6. Interrupt Flag Status and Clear
27.8.7. Status
27.8.8. Synchronization Busy
27.8.9. Address
27.8.10. Data
27.8.11. Debug Control
28. SERCOM I2C – SERCOM Inter-Integrated Circuit
28.1. Overview
28.2. Features
28.3. Block Diagram
28.4. Signal Description
28.5. Product Dependencies
28.5.1. I/O Lines
28.5.2. Power Management
28.5.3. Clocks
28.5.4. DMA
28.5.5. Interrupts
28.5.6. Events
28.5.7. Debug Operation
28.5.8. Register Access Protection
28.5.9. Analog Connections
28.6. Functional Description
28.6.1. Principle of Operation
28.6.2. Basic Operation
28.6.2.1. Initialization
28.6.2.2. Enabling, Disabling, and Resetting
28.6.2.3. I2C Bus State Logic
28.6.2.4. I2C Master Operation
28.6.2.4.1. Master Clock Generation
28.6.2.4.1.1. Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
28.6.2.4.1.2. Master Clock Generation (High-Speed Mode)
28.6.2.4.2. Transmitting Address Packets
28.6.2.4.3. Transmitting Data Packets
28.6.2.4.4. Receiving Data Packets (SCLSM=0)
28.6.2.4.5. Receiving Data Packets (SCLSM=1)
28.6.2.4.6. High-Speed Mode
28.6.2.4.7. 10-Bit Addressing
28.6.2.5. I2C Slave Operation
28.6.2.5.1. Receiving Address Packets (SCLSM=0)
28.6.2.5.2. Receiving Address Packets (SCLSM=1)
28.6.2.5.3. Receiving and Transmitting Data Packets
28.6.2.5.4. High-Speed Mode
28.6.2.5.5. 10-Bit Addressing
28.6.2.5.6. PMBus Group Command
28.6.3. Additional Features
28.6.3.1. SMBus
28.6.3.2. Smart Mode
28.6.3.3. 4-Wire Mode
28.6.3.4. Quick Command
28.6.4. DMA, Interrupts and Events
28.6.4.1. DMA Operation
28.6.4.1.1. Slave DMA
28.6.4.1.2. Master DMA
28.6.4.2. Interrupts
28.6.4.3. Events
28.6.5. Sleep Mode Operation
28.6.6. Synchronization
28.7. Register Summary - I2C Slave
28.8. Register Description - I2C Slave
28.8.1. Control A
28.8.2. Control B
28.8.3. Interrupt Enable Clear
28.8.4. Interrupt Enable Set
28.8.5. Interrupt Flag Status and Clear
28.8.6. Status
28.8.7. Synchronization Busy
28.8.8. Address
28.8.9. Data
28.9. Register Summary - I2C Master
28.10. Register Description - I2C Master
28.10.1. Control A
28.10.2. Control B
28.10.3. Baud Rate
28.10.4. Interrupt Enable Clear
28.10.5. Interrupt Enable Clear
28.10.6. Interrupt Flag Status and Clear
28.10.7. Status
28.10.8. Synchronization Busy
28.10.9. Address
28.10.10. Data
28.10.11. Debug Control
29. I2S - Inter-IC Sound Controller
29.1. Overview
29.2. Features
29.3. Block Diagram
29.4. Signal Description
29.5. Product Dependencies
29.5.1. I/O Lines
29.5.2. Power Management
29.5.3. Clocks
29.5.4. DMA
29.5.5. Interrupts
29.5.6. Events
29.5.7. Debug Operation
29.5.8. Register Access Protection
29.5.9. Analog Connections
29.6. Functional Description
29.6.1. Principle of Operation
29.6.1.1. Initialization
29.6.2. Basic Operation
29.6.2.1. Master Clock, Serial Clock, and Frame Sync Generation
29.6.2.1.1. Slave Mode
29.6.2.1.2. Master Mode and Controller Mode
29.6.2.1.3. MCKn Clock Frequency
29.6.2.1.4. SCKn Clock Frequency
29.6.2.1.5. Relation Between MCKn, SCKn, and Sampling Frequency fs
29.6.2.2. Data Holding Registers
29.6.2.2.1. Data Reception Mode
29.6.2.2.2. Data Transmission Mode
29.6.3. Master, Controller, and Slave Modes
29.6.4. I2S Format - Reception and Transmission Sequence with Word Select
29.6.5. TDM Format - Reception and Transmission Sequence
29.6.6. PDM Reception
29.6.7. Data Formatting Unit
29.6.8. DMA, Interrupts and Events
29.6.8.1. DMA Operation
29.6.8.2. Interrupts
29.6.8.3. Events
29.6.9. Sleep Mode Operation
29.6.10. Synchronization
29.6.11. Loop-Back Mode
29.7. I2S Application Examples
29.8. Register Summary
29.9. Register Description
29.9.1. Control A
29.9.2. Clock Unit n Control
29.9.3. Interrupt Enable Clear
29.9.4. Interrupt Enable Set
29.9.5. Interrupt Flag Status and Clear
29.9.6. Synchronization Busy
29.9.7. Serializer n Control
29.9.8. Data Holding m
29.9.9. Rx Data
30. TC – Timer/Counter
30.1. Overview
30.2. Features
30.3. Block Diagram
30.4. Signal Description
30.5. Product Dependencies
30.5.1. I/O Lines
30.5.2. Power Management
30.5.3. Clocks
30.5.4. Interrupts
30.5.5. Events
30.5.6. Debug Operation
30.5.7. Register Access Protection
30.5.8. Analog Connections
30.6. Functional Description
30.6.1. Principle of Operation
30.6.2. Basic Operation
30.6.2.1. Initialization
30.6.2.2. Enabling, Disabling and Resetting
30.6.2.3. Prescaler Selection
30.6.2.4. Counter Mode
30.6.2.5. Counter Operations
30.6.2.5.1. Stop Command and Event Action
30.6.2.5.2. Re-Trigger Command and Event Action
30.6.2.5.3. Count Event Action
30.6.2.5.4. Start Event Action
30.6.2.6. Compare Operations
30.6.2.6.1. Waveform Output Operations
30.6.2.6.2. Frequency Operation
30.6.2.6.3. PWM Operation
30.6.2.6.4. Changing the Top Value
30.6.2.7. Capture Operations
30.6.2.7.1. Event Capture Action
30.6.2.7.2. Period and Pulse-Width (PPW) Capture Action
30.6.3. Additional Features
30.6.3.1. One-Shot Operation
30.6.4. DMA, Interrupts and Events
30.6.4.1. Interrupts
30.6.4.2. Events
30.6.5. Sleep Mode Operation
30.6.6. Synchronization
30.7. Register Summary
30.8. Register Description
30.8.1. Control A
30.8.2. Read Request
30.8.3. Control B Clear
30.8.4. Control B Set
30.8.5. Control C
30.8.6. Debug Control
30.8.7. Event Control
30.8.8. Interrupt Enable Clear
30.8.9. Interrupt Enable Set
30.8.10. Interrupt Flag Status and Clear
30.8.11. Status
30.8.12. Counter Value
30.8.12.1. Counter Value, 8-bit Mode
30.8.12.2. Counter Value, 16-bit Mode
30.8.12.3. Counter Value, 32-bit Mode
30.8.13. Period Value
30.8.13.1. Period Value, 8-bit Mode
30.8.14. Compare/Capture
30.8.14.1. Channel x Compare/Capture Value, 8-bit Mode
30.8.14.2. Channel x Compare/Capture Value, 16-bit Mode
30.8.14.3. Channel x Compare/Capture Value, 32-bit Mode
31. TCC – Timer/Counter for Control Applications
31.1. Overview
31.2. Features
31.3. Block Diagram
31.4. Signal Description
31.5. Product Dependencies
31.5.1. I/O Lines
31.5.2. Power Management
31.5.3. Clocks
31.5.4. DMA
31.5.5. Interrupts
31.5.6. Events
31.5.7. Debug Operation
31.5.8. Register Access Protection
31.5.9. Analog Connections
31.6. Functional Description
31.6.1. Principle of Operation
31.6.2. Basic Operation
31.6.2.1. Initialization
31.6.2.2. Enabling, Disabling, and Resetting
31.6.2.3. Prescaler Selection
31.6.2.4. Counter Operation
31.6.2.5. Compare Operations
31.6.2.5.1. Waveform Output Generation Operations
31.6.2.5.2. Normal Frequency (NFRQ)
31.6.2.5.3. Match Frequency (MFRQ)
31.6.2.5.4. Normal Pulse-Width Modulation (NPWM)
31.6.2.5.5. Single-Slope PWM Operation
31.6.2.5.6. Dual-Slope PWM Generation
31.6.2.5.7. Dual-Slope Critical PWM Generation
31.6.2.5.8. Output Polarity
31.6.2.6. Double Buffering
31.6.2.7. Capture Operations
31.6.3. Additional Features
31.6.3.1. One-Shot Operation
31.6.3.2. Circular Buffer
31.6.3.3. Dithering Operation
31.6.3.4. Ramp Operations
31.6.3.5. Recoverable Faults
31.6.3.6. Non-Recoverable Faults
31.6.3.7. Waveform Extension
31.6.4. DMA, Interrupts, and Events
31.6.4.1. DMA Operation
31.6.4.2. Interrupts
31.6.4.3. Events
31.6.5. Sleep Mode Operation
31.6.6. Synchronization
31.7. Register Summary
31.8. Register Description
31.8.1. Control A
31.8.2. Control B Clear
31.8.3. Control B Set
31.8.4. Synchronization Busy
31.8.5. Fault Control A and B
31.8.6. Waveform Extension Control
31.8.7. Driver Control
31.8.8. Debug control
31.8.9. Event Control
31.8.10. Interrupt Enable Clear
31.8.11. Interrupt Enable Set
31.8.12. Interrupt Flag Status and Clear
31.8.13. Status
31.8.14. Counter Value
31.8.15. Pattern
31.8.16. Waveform
31.8.17. Period Value
31.8.18. Compare/Capture Channel x
31.8.19. Pattern Buffer
31.8.20. Waveform Buffer
31.8.21. Period Buffer Value
31.8.22. Channel x Compare/Capture Buffer Value
32. USB – Universal Serial Bus
32.1. Overview
32.2. Features
32.3. USB Block Diagram
32.4. Signal Description
32.5. Product Dependencies
32.5.1. I/O Lines
32.5.2. Power Management
32.5.3. Clocks
32.5.4. DMA
32.5.5. Interrupts
32.5.6. Events
32.5.7. Debug Operation
32.5.8. Register Access Protection
32.5.9. Analog Connections
32.5.10. Calibration
32.6. Functional Description
32.6.1. USB General Operation
32.6.1.1. Initialization
32.6.2. USB Device Operations
32.6.2.1. Initialization
32.6.2.2. Endpoint Configuration
32.6.2.3. Multi-Packet Transfers
32.6.2.4. USB Reset
32.6.2.5. Start-of-Frame
32.6.2.6. Management of SETUP Transactions
32.6.2.7. Management of OUT Transactions
32.6.2.8. Multi-Packet Transfers for OUT Endpoint
32.6.2.9. Management of IN Transactions
32.6.2.10. Multi-Packet Transfers for IN Endpoint
32.6.2.11. Ping-Pong Operation
32.6.2.12. Feedback Operation
32.6.2.13. Suspend State and Pad Behavior
32.6.2.14. Remote Wakeup
32.6.2.15. Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
32.6.2.16. USB Device Interrupt
32.6.3. Host Operations
32.6.3.1. Device Detection and Disconnection
32.6.3.2. Host Terminology
32.6.3.3. USB Reset
32.6.3.4. Pipe Configuration
32.6.3.5. Pipe Activation
32.6.3.6. Pipe Address Setup
32.6.3.7. Suspend and Wakeup
32.6.3.8. Phase-locked SOFs
32.6.3.9. Management of Control Pipes
32.6.3.10. Management of IN Pipes
32.6.3.11. Management of OUT Pipes
32.6.3.12. Alternate Pipe
32.6.3.13. Data Flow Error
32.6.3.14. CRC Error
32.6.3.15. PERR Error
32.6.3.16. Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
32.6.3.17. Host Interrupt
32.7. Register Summary
32.7.1. Common Device Summary
32.7.2. Device Summary
32.7.3. Host Summary
32.8. Register Description
32.8.1. Communication Device Host Registers
32.8.1.1. Control A
32.8.1.2. Synchronization Busy
32.8.1.3. QOS Control
32.8.1.4. Finite State Machine Status
32.8.1.5. Descriptor Address
32.8.1.6. Pad Calibration
32.8.2. Device Registers - Common
32.8.2.1. Control B
32.8.2.2. Device Address
32.8.2.3. Status
32.8.2.4. Device Frame Number
32.8.2.5. Device Interrupt Enable Clear
32.8.2.6. Device Interrupt Enable Set
32.8.2.7. Device Interrupt Flag Status and Clear
32.8.2.8. Endpoint Interrupt Summary
32.8.3. Device Registers - Endpoint
32.8.3.1. Device Endpoint Configuration register n
32.8.3.2. EndPoint Status Clear n
32.8.3.3. EndPoint Status Set n
32.8.3.4. EndPoint Status n
32.8.3.5. Device EndPoint Interrupt Flag n
32.8.3.6. Device EndPoint Interrupt Enable n
32.8.3.7. Device Interrupt EndPoint Set n
32.8.4. Device Registers - Endpoint RAM
32.8.4.1. Endpoint Descriptor Structure
32.8.4.2. Address of Data Buffer
32.8.4.3. Packet Size
32.8.4.4. Extended Register
32.8.4.5. Device Status Bank
32.8.5. Host Registers - Common
32.8.5.1. Control B
32.8.5.2. Host Start-of-Frame Control
32.8.5.3. Status
32.8.5.4. Host Frame Number
32.8.5.5. Host Frame Length
32.8.5.6. Host Interrupt Enable Register Clear
32.8.5.7. Host Interrupt Enable Register Set
32.8.5.8. Host Interrupt Flag Status and Clear
32.8.5.9. Pipe Interrupt Summary
32.8.6. Host Registers - Pipe
32.8.6.1. Host Pipe n Configuration
32.8.6.2. Interval for the Bulk-Out/Ping Transaction
32.8.6.3. Pipe Status Clear n
32.8.6.4. Pipe Status Set Register n
32.8.6.5. Pipe Status Register n
32.8.6.6. Host Pipe Interrupt Flag Register
32.8.6.7. Host Pipe Interrupt Clear Register
32.8.6.8. Host Interrupt Pipe Set Register
32.8.7. Host Registers - Pipe RAM
32.8.7.1. Pipe Descriptor Structure
32.8.7.2. Address of the Data Buffer
32.8.7.3. Packet Size
32.8.7.4. Extended Register
32.8.7.5. Host Status Bank
32.8.7.6. Host Control Pipe
32.8.7.7. Host Status Pipe
33. ADC – Analog-to-Digital Converter
33.1. Overview
33.2. Features
33.3. Block Diagram
33.4. Signal Description
33.5. Product Dependencies
33.5.1. I/O Lines
33.5.2. Power Management
33.5.3. Clocks
33.5.4. DMA
33.5.5. Interrupts
33.5.6. Events
33.5.7. Debug Operation
33.5.8. Register Access Protection
33.5.9. Analog Connections
33.5.10. Calibration
33.6. Functional Description
33.6.1. Principle of Operation
33.6.2. Basic Operation
33.6.2.1. Initialization
33.6.2.2. Enabling, Disabling and Reset
33.6.2.3. Basic Operation
33.6.3. Prescaler
33.6.4. ADC Resolution
33.6.5. Differential and Single-Ended Conversions
33.6.5.1. Conversion Timing
33.6.6. Accumulation
33.6.7. Averaging
33.6.8. Oversampling and Decimation
33.6.9. Window Monitor
33.6.10. Offset and Gain Correction
33.6.11. DMA Operation
33.6.12. Interrupts
33.6.13. Events
33.6.14. Sleep Mode Operation
33.6.15. Synchronization
33.7. Register Summary
33.8. Register Description
33.8.1. Control A
33.8.2. Reference Control
33.8.3. Average Control
33.8.4. Sampling Time Control
33.8.5. Control B
33.8.6. Window Monitor Control
33.8.7. Software Trigger
33.8.8. Input Control
33.8.9. Event Control
33.8.10. Interrupt Enable Clear
33.8.11. Interrupt Enable Set
33.8.12. Interrupt Flag Status and Clear
33.8.13. Status
33.8.14. Result
33.8.15. Window Monitor Lower Threshold
33.8.16. Window Monitor Upper Threshold
33.8.17. Gain Correction
33.8.18. Offset Correction
33.8.19. Calibration
33.8.20. Debug Control
34. AC – Analog Comparators
34.1. Overview
34.2. Features
34.3. Block Diagram
34.4. Signal Description
34.5. Product Dependencies
34.5.1. I/O Lines
34.5.2. Power Management
34.5.3. Clocks
34.5.4. DMA
34.5.5. Interrupts
34.5.6. Events
34.5.7. Debug Operation
34.5.8. Register Access Protection
34.5.9. Analog Connections
34.6. Functional Description
34.6.1. Principle of Operation
34.6.2. Basic Operation
34.6.2.1. Initialization
34.6.2.2. Enabling, Disabling and Resetting
34.6.2.3. Comparator Configuration
34.6.2.4. Starting a Comparison
34.6.2.4.1. Continuous Measurement
34.6.2.4.2. Single-Shot
34.6.3. Selecting Comparator Inputs
34.6.4. Window Operation
34.6.5. Voltage Doubler
34.6.6. VDDANA Scaler
34.6.7. Input Hysteresis
34.6.8. Propagation Delay vs. Power Consumption
34.6.9. Filtering
34.6.10. Comparator Output
34.6.11. Offset Compensation
34.6.12. Interrupts
34.6.13. Events
34.6.14. Sleep Mode Operation
34.6.14.1. Continuous Measurement during Sleep
34.6.14.2. Single-Shot Measurement during Sleep
34.6.15. Synchronization
34.7. Register Summary
34.8. Register Description
34.8.1. Control A
34.8.2. Control B
34.8.3. Event Control
34.8.4. Interrupt Enable Clear
34.8.5. Interrupt Enable Set
34.8.6. Interrupt Flag Status and Clear
34.8.7. Status A
34.8.8. Status B
34.8.9. Status A
34.8.10. Window Control
34.8.11. Comparator Control n
34.8.12. Scaler n
35. DAC – Digital-to-Analog Converter
35.1. Overview
35.2. Features
35.3. Block Diagram
35.4. Signal Description
35.5. Product Dependencies
35.5.1. I/O Lines
35.5.2. Power Management
35.5.3. Clocks
35.5.4. DMA
35.5.5. Interrupts
35.5.6. Events
35.5.7. Debug Operation
35.5.8. Register Access Protection
35.5.9. Analog Connections
35.6. Functional Description
35.6.1. Principle of Operation
35.6.2. Basic Operation
35.6.2.1. Initialization
35.6.2.2. Enabling, Disabling and Resetting
35.6.2.3. Enabling the Output Buffer
35.6.2.4. Digital to Analog Conversion
35.6.3. DMA Operation
35.6.4. Interrupts
35.6.5. Events
35.6.6. Sleep Mode Operation
35.6.7. Synchronization
35.6.8. Additional Features
35.6.8.1. DAC as an Internal Reference
35.6.8.2. Data Buffer
35.6.8.3. Voltage Pump
35.7. Register Summary
35.8. Register Description
35.8.1. Control A
35.8.2. Control B
35.8.3. Event Control
35.8.4. Interrupt Enable Clear
35.8.5. Interrupt Enable Set
35.8.6. Interrupt Flag Status and Clear
35.8.7. Status
35.8.8. Data DAC
35.8.9. Data Buffer
36. PTC - Peripheral Touch Controller
36.1. Overview
36.2. Features
36.3. Block Diagram
36.4. Signal Description
36.5. Product Dependencies
36.5.1. I/O Lines
36.5.1.1. Mutual-capacitance Sensor Arrangement
36.5.1.2. Self-capacitance Sensor Arrangement
36.5.2. Clocks
36.6. Functional Description
37. Electrical Characteristics
37.1. Disclaimer
37.2. Absolute Maximum Ratings
37.3. General Operating Ratings
37.4. Supply Characteristics
37.5. Maximum Clock Frequencies
37.6. Power Consumption
37.7. Peripheral Power Consumption
37.7.1. All peripheral except USB
37.7.2. USB Peripheral Power Consumption
37.8. I/O Pin Characteristics
37.8.1. Normal I/O Pins
37.8.2. I2C Pins
37.8.3. XOSC Pin
37.8.4. XOSC32 Pin
37.8.5. External Reset Pin
37.9. Injection Current
37.10. Analog Characteristics
37.10.1. Voltage Regulator Characteristics
37.10.2. Power-On Reset (POR) Characteristics
37.10.3. Brown-Out Detectors Characteristics
37.10.3.1. BOD33
37.10.4. Analog-to-Digital (ADC) characteristics
37.10.4.1. Performance with the Averaging Digital Feature
37.10.4.2. Performance with the hardware offset and gain correction
37.10.4.3. Inputs and Sample and Hold Acquisition Times
37.10.5. Digital to Analog Converter (DAC) Characteristics
37.10.6. Analog Comparator Characteristics
37.10.7. Internal 1.1V Bandgap Reference Characteristics
37.10.8. Temperature Sensor Characteristics
37.10.8.1. Temperature Sensor Characteristics
37.10.8.2. Software-based Refinement of the Actual Temperature
37.10.8.2.1. Temperature Log Row
37.10.8.2.2. Using Linear Interpolation
37.11. NVM Characteristics
37.12. Oscillators Characteristics
37.12.1. Crystal Oscillator (XOSC) Characteristics
37.12.1.1. Digital Clock Characteristics
37.12.1.2. Crystal Oscillator Characteristics
37.12.2. External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
37.12.2.1. Digital Clock Characteristics
37.12.2.1.1. Crystal Oscillator Characteristics
37.12.3. Digital Frequency Locked Loop (DFLL48M) Characteristics
37.12.4. 32.768kHz Internal oscillator (OSC32K) Characteristics
37.12.5. Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
37.12.6. 8MHz RC Oscillator (OSC8M) Characteristics
37.12.7. Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
37.13. PTC Typical Characteristics
37.13.1. Device Variant A
37.13.2. Device Variant B
37.14. USB Characteristics
37.15. Timing Characteristics
37.15.1. External Reset
37.15.2. SERCOM in SPI Mode Timing
37.15.3. SERCOM in I2C Mode Timing
37.15.4. SWD Timing
37.15.5. I2S Timing
38. Packaging Information
38.1. Thermal Considerations
38.1.1. Thermal Resistance Data
38.1.2. Junction Temperature
38.2. Package Drawings
38.2.1. 64 pin TQFP
38.2.2. 64 pin QFN
38.2.3. 64-ball UFBGA
38.2.4. 48 pin TQFP
38.2.5. 48 pin QFN
38.2.6. 45-ball WLCSP
38.2.7. 32 pin TQFP
38.2.8. 32 pin QFN
38.2.9. 35 ball WLCSP (Device Variant B)
38.3. Soldering Profile
39. Schematic Checklist
39.1. Introduction
39.1.1. Operation in Noisy Environment
39.2. Power Supply
39.2.1. Power Supply Connections
39.3. External Analog Reference Connections
39.4. External Reset Circuit
39.5. Clocks and Crystal Oscillators
39.5.1. External Clock Source
39.5.2. Crystal Oscillator
39.5.3. External Real Time Oscillator
39.5.4. Calculating the Correct Crystal Decoupling Capacitor
39.6. Unused or Unconnected Pins
39.7. Programming and Debug Ports
39.7.1. Cortex Debug Connector (10-pin)
39.7.2. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
39.7.3. 20-pin IDC JTAG Connector
39.8. USB Interface
40. Errata
40.1. Device Variant A
40.1.1. Die Revision A
40.1.1.1. Device
40.1.1.2. DSU
40.1.1.3. PM
40.1.1.4. DFLL48M
40.1.1.5. XOSC32K
40.1.1.6. FDPLL
40.1.1.7. DMAC
40.1.1.8. EIC
40.1.1.9. NVMCTRL
40.1.1.10. SERCOM
40.1.1.11. TC
40.1.1.12. TCC
40.1.1.13. USB
40.1.1.14. PTC
40.1.2. Die Revision B
40.1.2.1. Device
40.1.2.2. DSU
40.1.2.3. PM
40.1.2.4. DFLL48M
40.1.2.5. XOSC32K
40.1.2.6. DMAC
40.1.2.7. EIC
40.1.2.8. NVMCTRL
40.1.2.9. SERCOM
40.1.2.10. TC
40.1.2.11. TCC
40.1.2.12. PTC
40.1.3. Die Revision C
40.1.3.1. Device
40.1.3.2. DSU
40.1.3.3. PM
40.1.3.4. DFLL48M
40.1.3.5. XOSC32K
40.1.3.6. DMAC
40.1.3.7. EIC
40.1.3.8. NVMCTRL
40.1.3.9. I2S
40.1.3.10. SERCOM
40.1.3.11. TC
40.1.3.12. TCC
40.1.3.13. PTC
40.1.4. Die Revision D
40.1.4.1. Device
40.1.4.2. DSU
40.1.4.3. PM
40.1.4.4. DFLL48M
40.1.4.5. XOSC32K
40.1.4.6. DMAC
40.1.4.7. EIC
40.1.4.8. NVMCTRL
40.1.4.9. I2S
40.1.4.10. SERCOM
40.1.4.11. TC
40.1.4.12. TCC
40.1.4.13. PTC
40.2. Device Variant B
40.2.1. Die Revision E
40.2.1.1. Device
40.2.1.2. DSU
40.2.1.3. DFLL48M
40.2.1.4. DMAC
40.2.1.5. EIC
40.2.1.6. NVMCTRL
40.2.1.7. I2S
40.2.1.8. SERCOM
40.2.1.9. TCC
41. Conventions
41.1. Numerical Notation
41.2. Memory Size and Type
41.3. Frequency and Time
41.4. Registers and Bits
42. Acronyms and Abbreviations
43. Datasheet Revision History
43.1. Rev. K – 09/2016
43.2. Rev. J – 07/2016
43.3. Rev. I – 03/2016
43.4. Rev. H – 01/2016
43.5. Rev. G – 09/2015
43.6. Rev. F – 07/2015
43.7. Rev. E – 02/2015
43.8. Rev. D – 09/2014
43.9. Rev. C – 07/2014
43.10. Rev. B – 07/2014
43.11. Rev. A - 02/2014
44. Appendix A. Electrical Characteristics at 125°C
44.1. Disclaimer
44.2. Absolute Maximum Ratings
44.3. General Operating Ratings
44.4. Maximum Clock Frequencies
44.5. Power Consumption
44.6. Analog Characteristics
44.6.1. Power-On Reset (POR) Characteristics
44.6.2. Brown-Out Detectors Characteristics
44.6.2.1. BOD33
44.6.3. Analog-to-Digital (ADC) characteristics
44.6.4. Inputs and Sample and Hold Acquisition Times
44.6.5. Digital to Analog Converter (DAC) Characteristics
44.6.6. Analog Comparator Characteristics
44.6.7. Temperature Sensor Characteristics
44.7. NVM Characteristics
44.8. Oscillators Characteristics
44.8.1. Crystal Oscillator (XOSC) Characteristics
44.8.1.1. Digital Clock Characteristics
44.8.1.2. Crystal Oscillator Characteristics
44.8.2. External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
44.8.2.1. Digital Clock Characteristics
44.8.2.2. Crystal Oscillator Characteristics
44.8.3. Digital Frequency Locked Loop (DFLL48M) Characteristics
44.8.4. 32.768kHz Internal oscillator (OSC32K) Characteristics
44.8.5. Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
44.8.6. 8MHz RC Oscillator (OSC8M) Characteristics
44.8.7. Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
44.8.8. USB Characteristics
44.9. Timing Characteristics
44.9.1. SERCOM in SPI Mode Timing
44.9.2. SERCOM in I2C Mode Timing
44.9.3. I2S Timing
SMART ARM-Based Microcontrollers
SAM D21E / SAM D21G / SAM D21J
DATASHEET COMPLETE
Introduction
Atmel® | SMART™ SAM D21 is a series of low-power microcontrollers using
the 32-bit ARM® Cortex®-M0+ processor, and ranging from 32- to 64-pins
with up to 256KB Flash and 32KB of SRAM. The SAM D21 devices operate
at a maximum frequency of 48MHz and reach 2.46 CoreMark®/MHz. They
are designed for simple and intuitive migration with identical peripheral
modules, hex compatible code, identical linear address map and pin
compatible migration paths between all devices in the product series. All
devices include intelligent and flexible peripherals, Atmel Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and
wheel user interfaces.
Features
•
Processor
– ARM Cortex-M0+ CPU running at up to 48MHz
Single-cycle hardware multiplier
•
• Micro Trace Buffer (MTB)
• Memories
–
–
32/64/128/256KB in-system self-programmable Flash
4/8/16/32KB SRAM Memory
•
System
– Power-on reset (POR) and brown-out detection (BOD)
–
Internal and external clock options with 48MHz Digital Frequency
Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional Digital
Phase Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
–
– One non-maskable interrupt
–
16 external interrupts
Two-pin Serial Wire Debug (SWD) programming, test and
debugging interface
•
Low Power
Idle and standby sleep modes
–
– SleepWalking peripherals
Atmel-42181K-SAM-D21_Datasheet_Complete-09/2016
•
Peripherals
12-channel Direct Memory Access Controller (DMAC)
12-channel Event System
–
–
– Up to five 16-bit Timer/Counters (TC), configurable as either:
• One 16-bit TC with two compare/capture channels
• One 8-bit TC with two compare/capture channels
• One 32-bit TC with two compare/capture channels, by using two TCs
–
Three 24-bit Timer/Counters for Control (TCC), with extended functions:
Up to four compare channels with optional complementary output
•
• Generation of synchronized pulse width modulation (PWM) pattern across port pins
•
Deterministic fault protection, fast decay and configurable dead-time between
complementary output
Dithering that increase resolution with up to 5 bit and reduce quantization error
•
32-bit Real Time Counter (RTC) with clock/calendar function
–
– Watchdog Timer (WDT)
– CRC-32 generator
– One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface
•
•
Embedded host and device function
Eight endpoints
– Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as
either:
•
•
•
•
USART with full-duplex and single-wire half-duplex configuration
I2C up to 3.4MHz
SPI
LIN slave
– One two-channel Inter-IC Sound (I2S) interface
– One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
Differential and single-ended input
1/2x to 16x programmable gain stage
Automatic offset and gain error compensation
•
•
•
• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
10-bit, 350ksps Digital-to-Analog Converter (DAC)
Two Analog Comparators (AC) with window compare function
–
–
– Peripheral Touch Controller (PTC)
•
256-Channel capacitive touch and proximity sensing
•
•
•
•
I/O
– Up to 52 programmable I/O pins
Drop in compatible with SAM D20
Packages
–
–
–
64-pin TQFP, QFN, UFBGA
48-pin TQFP, QFN, WLCSP
32-pin TQFP, QFN, WLCSP
Operating Voltage
–
1.62V – 3.63V
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Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description...............................................................................................................11
2. Configuration Summary...........................................................................................12
3. Ordering Information................................................................................................14
SAM D21E..................................................................................................................................14
3.1.
SAM D21G................................................................................................................................. 16
3.2.
3.3.
SAM D21J.................................................................................................................................. 18
3.4. Device Identification................................................................................................................... 20
4. Block Diagram......................................................................................................... 22
5. Pinout.......................................................................................................................24
SAM D21J.................................................................................................................................. 24
SAM D21G................................................................................................................................. 26
SAM D21E..................................................................................................................................28
5.1.
5.2.
5.3.
6. Signal Descriptions List........................................................................................... 30
7.
I/O Multiplexing and Considerations........................................................................32
7.1. Multiplexed Signals.....................................................................................................................32
7.2. Other Functions..........................................................................................................................34
8. Power Supply and Start-Up Considerations............................................................ 37
Power Domain Overview............................................................................................................37
Power Supply Considerations.................................................................................................... 37
Power-Up....................................................................................................................................38
Power-On Reset and Brown-Out Detector................................................................................. 39
8.1.
8.2.
8.3.
8.4.
9. Product Mapping......................................................................................................40
10. Memories.................................................................................................................41
10.1. Embedded Memories................................................................................................................. 41
10.2. Physical Memory Map................................................................................................................ 41
10.3. NVM Calibration and Auxiliary Space.........................................................................................42
11. Processor And Architecture.....................................................................................46
11.1. Cortex M0+ Processor................................................................................................................46
11.2. Nested Vector Interrupt Controller..............................................................................................47
11.3. Micro Trace Buffer...................................................................................................................... 49
11.4. High-Speed Bus System............................................................................................................ 50
11.5. AHB-APB Bridge........................................................................................................................ 52
11.6. PAC - Peripheral Access Controller............................................................................................53
12. Peripherals Configuration Summary........................................................................71
13. DSU - Device Service Unit...................................................................................... 74
13.1. Overview.....................................................................................................................................74
13.2. Features..................................................................................................................................... 74
13.3. Block Diagram............................................................................................................................ 75
13.4. Signal Description.......................................................................................................................75
13.5. Product Dependencies............................................................................................................... 75
13.6. Debug Operation........................................................................................................................ 76
13.7. Chip Erase..................................................................................................................................78
13.8. Programming..............................................................................................................................78
13.9.
Intellectual Property Protection...................................................................................................79
13.10. Device Identification...................................................................................................................80
13.11. Functional Description................................................................................................................82
13.12. Register Summary..................................................................................................................... 87
13.13. Register Description...................................................................................................................89
14. Clock System.........................................................................................................113
14.1. Clock Distribution......................................................................................................................113
14.2. Synchronous and Asynchronous Clocks.................................................................................. 114
14.3. Register Synchronization..........................................................................................................114
14.4. Enabling a Peripheral............................................................................................................... 119
14.5. On-demand, Clock Requests....................................................................................................119
14.6. Power Consumption vs. Speed................................................................................................ 120
14.7. Clocks after Reset.................................................................................................................... 120
15. GCLK - Generic Clock Controller.......................................................................... 121
15.1. Overview...................................................................................................................................121
15.2. Features................................................................................................................................... 121
15.3. Block Diagram.......................................................................................................................... 121
15.4. Signal Description.....................................................................................................................122
15.5. Product Dependencies............................................................................................................. 122
15.6. Functional Description..............................................................................................................123
15.7. Register Summary....................................................................................................................128
15.8. Register Description................................................................................................................. 129
16. PM – Power Manager............................................................................................142
16.1. Overview...................................................................................................................................142
16.2. Features................................................................................................................................... 142
16.3. Block Diagram.......................................................................................................................... 143
16.4. Signal Description.....................................................................................................................143
16.5. Product Dependencies............................................................................................................. 143
16.6. Functional Description..............................................................................................................145
16.7. Register Summary....................................................................................................................151
16.8. Register Description................................................................................................................. 152
17. SYSCTRL – System Controller............................................................................. 173
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17.1. Overview...................................................................................................................................173
17.2. Features................................................................................................................................... 173
17.3. Block Diagram.......................................................................................................................... 175
17.4. Signal Description.....................................................................................................................175
17.5. Product Dependencies............................................................................................................. 175
17.6. Functional Description..............................................................................................................177
17.7. Register Summary....................................................................................................................192
17.8. Register Description................................................................................................................. 194
18. WDT – Watchdog Timer........................................................................................ 237
18.1. Overview...................................................................................................................................237
18.2. Features................................................................................................................................... 237
18.3. Block Diagram.......................................................................................................................... 238
18.4. Signal Description.....................................................................................................................238
18.5. Product Dependencies............................................................................................................. 238
18.6. Functional Description..............................................................................................................239
18.7. Register Summary....................................................................................................................244
18.8. Register Description................................................................................................................. 244
19. RTC – Real-Time Counter..................................................................................... 255
19.1. Overview...................................................................................................................................255
19.2. Features................................................................................................................................... 255
19.3. Block Diagram.......................................................................................................................... 256
19.4. Signal Description.....................................................................................................................256
19.5. Product Dependencies............................................................................................................. 256
19.6. Functional Description..............................................................................................................258
19.7. Register Summary....................................................................................................................263
19.8. Register Description................................................................................................................. 266
20. DMAC – Direct Memory Access Controller........................................................... 299
20.1. Overview...................................................................................................................................299
20.2. Features................................................................................................................................... 299
20.3. Block Diagram.......................................................................................................................... 301
20.4. Signal Description.....................................................................................................................301
20.5. Product Dependencies............................................................................................................. 301
20.6. Functional Description..............................................................................................................302
20.7. Register Summary....................................................................................................................322
20.8. Register Description................................................................................................................. 323
20.9. Register Summary - SRAM...................................................................................................... 354
20.10. Register Description - SRAM................................................................................................... 354
21. EIC – External Interrupt Controller........................................................................ 362
21.1. Overview...................................................................................................................................362
21.2. Features................................................................................................................................... 362
21.3. Block Diagram.......................................................................................................................... 362
21.4. Signal Description.....................................................................................................................363
21.5. Product Dependencies............................................................................................................. 363
21.6. Functional Description..............................................................................................................364
21.7. Register Summary....................................................................................................................368
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21.8. Register Description................................................................................................................. 369
22. NVMCTRL – Non-Volatile Memory Controller....................................................... 380
22.1. Overview...................................................................................................................................380
22.2. Features................................................................................................................................... 380
22.3. Block Diagram.......................................................................................................................... 380
22.4. Signal Description.....................................................................................................................381
22.5. Product Dependencies............................................................................................................. 381
22.6. Functional Description..............................................................................................................382
22.7. Register Summary....................................................................................................................389
22.8. Register Description................................................................................................................. 389
23. PORT - I/O Pin Controller......................................................................................403
23.1. Overview...................................................................................................................................403
23.2. Features................................................................................................................................... 403
23.3. Block Diagram.......................................................................................................................... 404
23.4. Signal Description.....................................................................................................................404
23.5. Product Dependencies............................................................................................................. 404
23.6. Functional Description..............................................................................................................407
23.7. Register Summary....................................................................................................................411
23.8. Register Description................................................................................................................. 412
24. EVSYS – Event System........................................................................................ 431
24.1. Overview...................................................................................................................................431
24.2. Features................................................................................................................................... 431
24.3. Block Diagram.......................................................................................................................... 431
24.4. Signal Description.....................................................................................................................432
24.5. Product Dependencies............................................................................................................. 432
24.6. Functional Description..............................................................................................................433
24.7. Register Summary....................................................................................................................438
24.8. Register Description................................................................................................................. 438
25. SERCOM – Serial Communication Interface.........................................................452
25.1. Overview...................................................................................................................................452
25.2. Features................................................................................................................................... 452
25.3. Block Diagram.......................................................................................................................... 453
25.4. Signal Description.....................................................................................................................453
25.5. Product Dependencies............................................................................................................. 453
25.6. Functional Description..............................................................................................................455
26. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver
and Transmitter......................................................................................................461
26.1. Overview...................................................................................................................................461
26.2. USART Features...................................................................................................................... 461
26.3. Block Diagram.......................................................................................................................... 462
26.4. Signal Description.....................................................................................................................462
26.5. Product Dependencies............................................................................................................. 462
26.6. Functional Description..............................................................................................................464
26.7. Register Summary....................................................................................................................476
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26.8. Register Description................................................................................................................. 476
27. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................499
27.1. Overview...................................................................................................................................499
27.2. Features................................................................................................................................... 499
27.3. Block Diagram.......................................................................................................................... 500
27.4. Signal Description.....................................................................................................................500
27.5. Product Dependencies............................................................................................................. 500
27.6. Functional Description..............................................................................................................502
27.7. Register Summary....................................................................................................................511
27.8. Register Description................................................................................................................. 512
28. SERCOM I2C – SERCOM Inter-Integrated Circuit................................................ 532
28.1. Overview...................................................................................................................................532
28.2. Features................................................................................................................................... 532
28.3. Block Diagram.......................................................................................................................... 533
28.4. Signal Description.....................................................................................................................533
28.5. Product Dependencies............................................................................................................. 533
28.6. Functional Description..............................................................................................................535
28.7. Register Summary - I2C Slave.................................................................................................554
28.8. Register Description - I2C Slave.............................................................................................. 554
28.9. Register Summary - I2C Master...............................................................................................574
28.10. Register Description - I2C Master............................................................................................ 575
29. I2S - Inter-IC Sound Controller.............................................................................. 597
29.1. Overview...................................................................................................................................597
29.2. Features................................................................................................................................... 597
29.3. Block Diagram.......................................................................................................................... 598
29.4. Signal Description.....................................................................................................................599
29.5. Product Dependencies............................................................................................................. 599
29.6. Functional Description..............................................................................................................601
I2S Application Examples......................................................................................................... 612
29.7.
29.8. Register Summary....................................................................................................................615
29.9. Register Description................................................................................................................. 616
30. TC – Timer/Counter...............................................................................................633
30.1. Overview...................................................................................................................................633
30.2. Features................................................................................................................................... 633
30.3. Block Diagram.......................................................................................................................... 634
30.4. Signal Description.....................................................................................................................634
30.5. Product Dependencies............................................................................................................. 635
30.6. Functional Description..............................................................................................................636
30.7. Register Summary....................................................................................................................648
30.8. Register Description................................................................................................................. 650
31. TCC – Timer/Counter for Control Applications...................................................... 676
31.1. Overview...................................................................................................................................676
31.2. Features................................................................................................................................... 676
31.3. Block Diagram.......................................................................................................................... 677
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31.4. Signal Description.....................................................................................................................677
31.5. Product Dependencies............................................................................................................. 678
31.6. Functional Description..............................................................................................................679
31.7. Register Summary....................................................................................................................714
31.8. Register Description................................................................................................................. 716
32. USB – Universal Serial Bus...................................................................................761
32.1. Overview...................................................................................................................................761
32.2. Features................................................................................................................................... 761
32.3. USB Block Diagram..................................................................................................................762
32.4. Signal Description.....................................................................................................................762
32.5. Product Dependencies............................................................................................................. 762
32.6. Functional Description..............................................................................................................764
32.7. Register Summary....................................................................................................................782
32.8. Register Description................................................................................................................. 786
33. ADC – Analog-to-Digital Converter........................................................................861
33.1. Overview...................................................................................................................................861
33.2. Features................................................................................................................................... 861
33.3. Block Diagram.......................................................................................................................... 862
33.4. Signal Description.....................................................................................................................862
33.5. Product Dependencies............................................................................................................. 863
33.6. Functional Description..............................................................................................................864
33.7. Register Summary....................................................................................................................873
33.8. Register Description................................................................................................................. 874
34. AC – Analog Comparators.....................................................................................899
34.1. Overview...................................................................................................................................899
34.2. Features................................................................................................................................... 899
34.3. Block Diagram.......................................................................................................................... 900
34.4. Signal Description.....................................................................................................................900
34.5. Product Dependencies............................................................................................................. 900
34.6. Functional Description..............................................................................................................902
34.7. Register Summary....................................................................................................................911
34.8. Register Description................................................................................................................. 912
35. DAC – Digital-to-Analog Converter........................................................................929
35.1. Overview...................................................................................................................................929
35.2. Features................................................................................................................................... 929
35.3. Block Diagram.......................................................................................................................... 929
35.4. Signal Description.....................................................................................................................929
35.5. Product Dependencies............................................................................................................. 929
35.6. Functional Description..............................................................................................................931
35.7. Register Summary....................................................................................................................935
35.8. Register Description................................................................................................................. 935
36. PTC - Peripheral Touch Controller.........................................................................946
36.1. Overview...................................................................................................................................946
36.2. Features................................................................................................................................... 946
Atmel SAM D21E / SAM D21G / SAM D21J [DATASHEET]
Atmel-42181K-SAM-D21_Datasheet_Complete-09/2016
8
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