第1页 / 共406页
第2页 / 共406页
第3页 / 共406页
第4页 / 共406页
第5页 / 共406页
第6页 / 共406页
第7页 / 共406页
第8页 / 共406页
DFT EDT 压缩解压缩模块详解.pdf
Bookcase
Revision History ISO-26262
Table of Contents
List of Figures
List of Tables
Chapter 1 Getting Started
Tessent TestKompress
EDT Technology
Scan Channels
Structure and Function
Test Patterns
TestKompress Compression Logic
TestKompress Usage Flow Overview
EDT IP Creation and Pattern Generation Flow
Pre-Synthesis Flow
Tessent Core Description (TCD)
EDT IP Generation
EDT Logic Synthesis
EDT Pattern Generation
Using TCD-Based Flow With Flattened EDT Hierarchy
Tessent Shell User Interface
Chapter 2 The Compressed Pattern Flows
Top-Down Design Flows
The Compressed Pattern Flows
Design Requirements for a Compressed Pattern Flow
Compressed Pattern External Flow
Compressed Pattern Internal Flow
Chapter 3 Scan Chain Synthesis
Design Preparation
Scan Chain Insertion
OCC Sub-Chain Stitching
ATPG Baseline Generation
Chapter 4 Creation of the EDT Logic
Compression Analysis
Analyzing Compression
Preparation for EDT Logic Creation
Parameter Specification for the EDT Logic
Dual Compression Configurations
Defining Dual Compression Configurations
Asymmetric Input and Output Channels
Bypass Scan Chains
Latch-Based EDT Logic
Compactor Type
Pipeline Stages in the Compactor
Pipeline Stages Added to the Channel
Longest Scan Chain Range
EDT Logic Reset
EDT Architecture Version
Specifying Hard Macros
Pulse EDT Clock Before Scan Shift Clocks
Reporting of the EDT Logic Configuration
EDT Control and Channel Pins
EDT Control and Channel Pin Configuration
Functional/EDT Pin Sharing
Shared Pin Configuration
Connections for EDT Pins (Internal Flow Only)
Internally Driven EDT Pins
Structure of the Bypass Chains
Decompressor and Compactor Connections
IJTAG and the EDT IP TCD Flow
Design Rule Checks
Creation of EDT Logic Files
The EDT Logic Files
IJTAG and EDT Logic
Specification of Module/Instance Names
EDT Logic Description
Inserting EDT Logic During Synthesis
Creation of a Reduced Netlist for Synthesis
Chapter 5 Synthesizing the EDT Logic
The EDT Logic Synthesis Script
Synthesis and External EDT Logic
Synthesis and Internal EDT Logic
SDC Timing File Generation
SDC Timing File Generation Using extract_sdc
SDC Timing File Generation Using write_edt_files
EDT Logic/Core Interface Timing Files
Scan Chain and ATPG Timing Files
Chapter 6 Generating and Verifying Test Patterns
Preparation for Test Pattern Generation
EDT Pattern Generation Overview
IJTAG Mapping
Scan Chain Handling
Core Instance Parameters
Used Input Channels
Pattern Generation With Internal Chain Masking Hardware
Updating Scan Pins for Test Pattern Generation
Verification of the EDT Logic
Design Rules Checking (DRC)
EDT Logic and Chain Testing
Reducing Serial EDT Chain Test Simulation Runtime
Test Pattern Generation
Generating Patterns
Compression Optimization
Saving of the Patterns
Post-Processing of EDT Patterns
Simulation of the Generated Test Patterns
Chapter 7 Modular Compressed ATPG
The Modular Flow
Understanding Modular Compressed ATPG
Development of a Block-Level Compression Strategy
Balancing Scan Chains Between Blocks
Sharing Input Scan Channels on Identical EDT Blocks
Channel Sharing for Non-Identical EDT Blocks
Overview of Channel Sharing Functionality
Compression Analysis
EDT IP Creation With Separate Control and Data Input Channels
Rules for Connecting Input Channels from Cores to Top
Channel Sharing Reporting
Channel Sharing Limitations
Mixing Channel Sharing for Non-Identical EDT Blocks and Channel Broadcasting for Identical EDT Blocks
Generating Modular EDT Logic for a Fully Integrated Design
Estimating Test Coverage/Pattern Count for EDT Blocks
Legacy ATPG Flow
Chapter 8 Compressed ATPG Advanced Features
Low-Power Test
Low-Power Shift
Setting Up Low-Power Test
Low Pin Count Test Controller
LPCT Controller Decision Tree
Test Mode Clock Multiplexer Requirement
Sharing of the LPCT Clock and a Top-Level Scan Clock
Shift Clock Control for LPCT Controllers
Type 1 LPCT Controller
Type 2 LPCT Controller
Type 3 LPCT Controller
Tessent OCC and LPCT Usage
LPCT Limitations
LPCT Controller Types
Type 1 - LPCT Controller With Top-level Scan Enable
Type 2 - LPCT Controller With a TAP
Type 3 - LPCT Controller-Generated Scan Enable
LPCT Configuration Examples
Type 1 Controller Generation Example
Type 2 Controller Generation Example
Type 3 Controller Example
Type 1 Controller LPCT Clock Example
Type 2 Controller Scan Shift Clock Example
Compression Bypass Logic
Structure of the Bypass Logic
Generating EDT Logic When Bypass Logic is Defined in the Netlist
Dual Bypass Configurations
Generation of Identical EDT and Bypass Test Patterns
Use of Bypass Patterns in Uncompressed ATPG
Creating Bypass Test Patterns in Uncompressed ATPG
Uncompressed ATPG (External Flow) and Boundary Scan
Boundary Scan Coexisting With EDT Logic
Drive Compressed ATPG With the TAP Controller
Use of Pipeline Stages in the Compactor
Use of Pipeline Stages Between Pads and Channel Inputs or Outputs
Channel Output Pipelining
Channel Input Pipelining
Clocks for Channel Input Pipeline Stages
Clocks for Channel Output Pipeline Stages
Input Channel Pipelines Must Hold Their Value During Capture
DRC for Channel Input Pipelining
DRC for Channel Output Pipelining
Input/Output Pipeline Examples
Change Edge Behavior in Bypass and EDT Modes
Understanding Lockup Cells
Lockup Cell Insertion
Lockup Cell Analysis for Bypass Lockup Cells Not Included as Part of the EDT Chains
Lockups Between Decompressor and Scan Chain Inputs
Lockups Between Scan Chain Outputs and Compactor
Lockups in the Bypass Circuitry
Lockup Cell Analysis for Bypass Lockup Cells Included as Part of the EDT Chains
EDT Lockup and Scan Chain Boundary Lockup Cells
Differences Based on Inclusion/Exclusion of Bypass Lockup Cells in EDT Chains
Lockup Cell Functionality Limitations
Comparison of Bypass Lockup Cell Insertion Results
Lockups Between Channel Outputs and Output Pipeline Stages
Compression Performance Evaluation
Establishing a Point of Reference
Performance Measurement
Performance Improvement
Variance in the Number of Scan Chains
Variance in the Number of Scan Channels
Determining the Limits of Compression
Speed up the Process
Understanding Compactor Options
Understanding Scan Chain Masking in the Compactor
Fault Aliasing
About Reordering Patterns
Handling of Last Patterns
EDT Aborted Fault Analysis
Chapter 9 Integrating Compression at the RTL Stage
IP Generation and Insertion Using EDT Specification
Basic Flow
Pipeline Stage Insertion
Bused EDT Channel Input and Output Connections
Lockup Cells on the Input Side of the EDT Controller
Lockup Cells on the Output Side of the EDT Controller
Lockup Cells Clock Connections
EDT Specification Wrapper Creation
Validating the EDT Specification and Creating the EDT IP
Legacy Skeleton RTL Flow
Skeleton Flow Overview
Skeleton Design Input and Interface Files
Skeleton Design Input File
Input File Format
Input File Example
Skeleton Design Interface File
Creation of the EDT Logic for a Skeleton Design
Longest Scan Chain Range Estimate
Integration of the EDT Logic Into the Design
Skeleton Flow Example
Input File
Interface File
Outputs
Appendix A Getting Help
The Tessent Documentation System
Mentor Support Services
Appendix B EDT Logic Specifications
EDT Logic With Basic Compactor and Bypass Module
EDT Logic With Xpress Compactor and Bypass Module
Decompressor Module With Basic Compactor
Decompressor Module With Xpress Compactor
Input Bypass Logic
Compactor Module
Output Bypass Logic
Single Chain Bypass Logic
Basic Compactor Masking Logic
Xpress Compactor Controller Masking Logic
Dual Compression Configuration Input Logic
Dual Compression Configuration Output Logic
EDT Logic With Power Controller
Appendix C Troubleshooting
Debugging Simulation Mismatches
Resolving DRC Issues
K19 Through K22 DRC Violations
Debugging Best Practices
Understanding K19 Rule Violations
Incorrect Control Signals
Inverted Signals
Incorrect EDT Channel Signal Order
Incorrect Scan Chain Order
X Generated by EDT Decompressor
Using set_gate_report K19
Understanding K22 Rule Violations
Inverted Signals
Incorrect Scan Chain Order
Masking Problems
Using set_gate_report K22
Miscellaneous
Incorrect References in Synthesized Netlist
Limiting Observable Xs for a Compact Pattern Set
Applying Uncompressable Patterns Thru Bypass Mode
If Compression Is Less Than Expected
If Test Coverage Is Less Than Expected
If There Are EDT Aborted Faults
Internal Scan Chain Pins Incorrectly Shared With Functional Pins
Masking Broken Scan Chains in the EDT Logic
Appendix D Dofile-Based Legacy IP Creation and Pattern Generation Flow
EDT IP Generation Dofiles
Test Pattern Generation Files
EDT Bypass Files
EDT Pattern Generation Dofiles
Generated Bypass Dofile and Procedure File
Creation of Test Patterns
Low Pin Count Test Controller Dofiles
Type 1 Controller Example
Type 2 Controller Example
Type 3 Controller Example
Index
Third-Party Information
End-User License Agreement with EDA Software Supplemental Terms
Documentation Feedback
Tessent® TestKompress® User’s Manual
Software Version 2020.2
Document Revision 17
Unpublished work. © Siemens 2020
This document contains information that is confidential and proprietary to Mentor Graphics Corporation, Siemens
Industry Software Inc., or their affiliates (collectively, "Siemens"). The original recipient of this document may
duplicate this document in whole or in part for internal business purposes only, provided that this entire notice
appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort
to prevent the unauthorized use and distribution of the confidential and proprietary information.
This document is for information and instruction purposes. Siemens reserves the right to make changes in
specifications and other information contained in this publication without prior notice, and the reader should, in all
cases, consult Siemens to determine whether any changes have been made.
The terms and conditions governing the sale and licensing of Siemens products are set forth in written agreements
between Siemens and its customers. End User License Agreement — You can print a copy of the End User
License Agreement from: mentor.com/eula.
No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give
rise to any liability of Siemens whatsoever.
SIEMENS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.
SIEMENS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, CONSEQUENTIAL OR
PUNITIVE DAMAGES, LOST DATA OR PROFITS, EVEN IF SUCH DAMAGES WERE FORESEEABLE, ARISING
OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF SIEMENS
HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
LICENSE RIGHTS APPLICABLE TO THE U.S. GOVERNMENT: This document explains the capabilities of
commercial products that were developed exclusively at private expense. If the products are acquired directly or
indirectly for use by the U.S. Government, then the parties agree that the products and this document are
considered "Commercial Items" and "Commercial Computer Software" or "Computer Software Documentation," as
defined in 48 C.F.R. §2.101 and 48 C.F.R. §252.227-7014(a)(1) and (a)(5), as applicable. Software and this
document may only be used under the terms and conditions of the End User License Agreement referenced above
as required by 48 C.F.R. §12.212 and 48 C.F.R §227.7202. The U.S. Government will only have the rights set forth
in the End User License Agreement, which supersedes any conflicting terms or conditions in any government order
document, except for provisions which are contrary to applicable mandatory federal laws.
TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Siemens or
other parties. No one is permitted to use these Marks without the prior written consent of Siemens or the owner of
the Marks, as applicable. The use herein of third party Marks is not an attempt to indicate Siemens as a source of a
product, but is intended to indicate a product from, or associated with, a particular third party. A list of Siemens'
trademarks may be viewed at: www.plm.automation.siemens.com/global/en/legal/trademarks.html and
mentor.com/trademarks.
The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of Linus
Torvalds, owner of the mark on a world-wide basis.
Support Center: support.sw.siemens.com
Send Feedback on Documentation: support.sw.siemens.com/doc_feedback_form
Revision History ISO-26262
Revision
Changes
17
16
15
14
Modifications to improve the readability and comprehension of
the content. Approved by Lucille Woo.
All technical enhancements, changes, and fixes listed in the
Tessent Release Notes for this product are reflected in this
document. Approved by Ron Press.
Modifications to improve the readability and comprehension of
the content. Approved by Lucille Woo.
All technical enhancements, changes, and fixes listed in the
Tessent Release Notes for this product are reflected in this
document. Approved by Ron Press.
Modifications to improve the readability and comprehension of
the content. Approved by Lucille Woo.
All technical enhancements, changes, and fixes listed in the
Tessent Release Notes for this product are reflected in this
document. Approved by Ron Press.
Modifications to improve the readability and comprehension of
the content. Approved by Lucille Woo.
All technical enhancements, changes, and fixes listed in the
Tessent Release Notes for this product are reflected in this
document. Approved by Ron Press.
Status/
Date
Released
Jun 2020
Released
Mar 2020
Released
Dec 2019
Released
Sep 2019
Author: In-house procedures and working practices require multiple authors for documents. All
associated authors for each topic within this document are tracked within the Mentor Graphics
Technical Publication’s source. For specific topic authors, contact Mentor Graphics Technical
Publication department.
Revision History: Released documents include a revision history of up to four revisions. For
earlier revision history, refer to earlier releases of documentation on Support Center.
Tessent® TestKompress® User’s Manual, v2020.2
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
4
Tessent® TestKompress® User’s Manual, v2020.2
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Table of Contents
Revision History ISO-26262
Chapter 1
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tessent TestKompress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TestKompress Compression Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TestKompress Usage Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDT IP Creation and Pattern Generation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tessent Core Description (TCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDT IP Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDT Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDT Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using TCD-Based Flow With Flattened EDT Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . .
Tessent Shell User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2
The Compressed Pattern Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top-Down Design Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Compressed Pattern Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Requirements for a Compressed Pattern Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compressed Pattern External Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compressed Pattern Internal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
Scan Chain Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Preparation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Chain Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCC Sub-Chain Stitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATPG Baseline Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 4
Creation of the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compression Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyzing Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preparation for EDT Logic Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Specification for the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Compression Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tessent® TestKompress® User’s Manual, v2020.2
17
17
20
20
21
22
23
29
29
31
33
33
34
34
36
37
41
44
46
46
47
50
53
53
55
60
63
65
66
66
70
74
75
5
Table of Contents
Defining Dual Compression Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Asymmetric Input and Output Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Bypass Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Latch-Based EDT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Compactor Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Pipeline Stages in the Compactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Pipeline Stages Added to the Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
Longest Scan Chain Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
EDT Logic Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
EDT Architecture Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
Specifying Hard Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
Pulse EDT Clock Before Scan Shift Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
Reporting of the EDT Logic Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
EDT Control and Channel Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
EDT Control and Channel Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
Functional/EDT Pin Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Shared Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
Connections for EDT Pins (Internal Flow Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
Internally Driven EDT Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
Structure of the Bypass Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
Decompressor and Compactor Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
IJTAG and the EDT IP TCD Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
Design Rule Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97
Creation of EDT Logic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
The EDT Logic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
IJTAG and EDT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Specification of Module/Instance Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EDT Logic Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Inserting EDT Logic During Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Creation of a Reduced Netlist for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Chapter 5
Synthesizing the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
The EDT Logic Synthesis Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Synthesis and External EDT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Synthesis and Internal EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SDC Timing File Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SDC Timing File Generation Using extract_sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SDC Timing File Generation Using write_edt_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
EDT Logic/Core Interface Timing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Scan Chain and ATPG Timing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Chapter 6
Generating and Verifying Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Preparation for Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
EDT Pattern Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
IJTAG Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Scan Chain Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6
Tessent® TestKompress® User’s Manual, v2020.2
Table of Contents
Core Instance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Used Input Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Pattern Generation With Internal Chain Masking Hardware . . . . . . . . . . . . . . . . . . . . . . . 147
Updating Scan Pins for Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Verification of the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Design Rules Checking (DRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
EDT Logic and Chain Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Reducing Serial EDT Chain Test Simulation Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Generating Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Compression Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Saving of the Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Post-Processing of EDT Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Simulation of the Generated Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Chapter 7
Modular Compressed ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
The Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Understanding Modular Compressed ATPG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Development of a Block-Level Compression Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Balancing Scan Chains Between Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Sharing Input Scan Channels on Identical EDT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Channel Sharing for Non-Identical EDT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Overview of Channel Sharing Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Compression Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
EDT IP Creation With Separate Control and Data Input Channels . . . . . . . . . . . . . . . . . 172
Rules for Connecting Input Channels from Cores to Top . . . . . . . . . . . . . . . . . . . . . . . . 175
Channel Sharing Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Channel Sharing Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Mixing Channel Sharing for Non-Identical EDT Blocks and Channel Broadcasting for
Identical EDT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Generating Modular EDT Logic for a Fully Integrated Design . . . . . . . . . . . . . . . . . . . . . 179
Estimating Test Coverage/Pattern Count for EDT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . 180
Legacy ATPG Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Chapter 8
Compressed ATPG Advanced Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Low-Power Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Low-Power Shift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Setting Up Low-Power Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Low Pin Count Test Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
LPCT Controller Decision Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Test Mode Clock Multiplexer Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Sharing of the LPCT Clock and a Top-Level Scan Clock . . . . . . . . . . . . . . . . . . . . . . . . 199
Shift Clock Control for LPCT Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Type 1 LPCT Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Type 2 LPCT Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Type 3 LPCT Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Tessent® TestKompress® User’s Manual, v2020.2
7
Table of Contents
Tessent OCC and LPCT Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
LPCT Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
LPCT Controller Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Type 1 - LPCT Controller With Top-level Scan Enable . . . . . . . . . . . . . . . . . . . . . . . . . 212
Type 2 - LPCT Controller With a TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Type 3 - LPCT Controller-Generated Scan Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LPCT Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Type 1 Controller Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Type 2 Controller Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Type 3 Controller Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Type 1 Controller LPCT Clock Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Type 2 Controller Scan Shift Clock Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Compression Bypass Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Structure of the Bypass Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Generating EDT Logic When Bypass Logic is Defined in the Netlist. . . . . . . . . . . . . . . . 233
Dual Bypass Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Generation of Identical EDT and Bypass Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Use of Bypass Patterns in Uncompressed ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Creating Bypass Test Patterns in Uncompressed ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Uncompressed ATPG (External Flow) and Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . 242
Boundary Scan Coexisting With EDT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Drive Compressed ATPG With the TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Use of Pipeline Stages in the Compactor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Use of Pipeline Stages Between Pads and Channel Inputs or Outputs . . . . . . . . . . . . . . . . . 249
Channel Output Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Channel Input Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Clocks for Channel Input Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Clocks for Channel Output Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Input Channel Pipelines Must Hold Their Value During Capture . . . . . . . . . . . . . . . . . . . 252
DRC for Channel Input Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
DRC for Channel Output Pipelining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Input/Output Pipeline Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Change Edge Behavior in Bypass and EDT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Understanding Lockup Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Lockup Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Lockup Cell Analysis for Bypass Lockup Cells Not Included as Part of the EDT Chains 258
Lockups Between Decompressor and Scan Chain Inputs . . . . . . . . . . . . . . . . . . . . . . . . 258
Lockups Between Scan Chain Outputs and Compactor. . . . . . . . . . . . . . . . . . . . . . . . . . 260
Lockups in the Bypass Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Lockup Cell Analysis for Bypass Lockup Cells Included as Part of the EDT Chains . . . . 266
EDT Lockup and Scan Chain Boundary Lockup Cells . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Differences Based on Inclusion/Exclusion of Bypass Lockup Cells in EDT Chains . . . 268
Lockup Cell Functionality Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Comparison of Bypass Lockup Cell Insertion Results. . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Lockups Between Channel Outputs and Output Pipeline Stages . . . . . . . . . . . . . . . . . . . . 274
Compression Performance Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Establishing a Point of Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Performance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Performance Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
8
Tessent® TestKompress® User’s Manual, v2020.2
相关推荐
2023年江西萍乡中考道德与法治真题及答案.doc
2012年重庆南川中考生物真题及答案.doc
2013年江西师范大学地理学综合及文艺理论基础考研真题.doc
2020年四川甘孜小升初语文真题及答案I卷.doc
2020年注册岩土工程师专业基础考试真题及答案.doc
2023-2024学年福建省厦门市九年级上学期数学月考试题及答案.doc
2021-2022学年辽宁省沈阳市大东区九年级上学期语文期末试题及答案.doc
2022-2023学年北京东城区初三第一学期物理期末试卷及答案.doc
2018上半年江西教师资格初中地理学科知识与教学能力真题及答案.doc
2012年河北国家公务员申论考试真题及答案-省级.doc
2020-2021学年江苏省扬州市江都区邵樊片九年级上学期数学第一次质量检测试题及答案.doc
2022下半年黑龙江教师资格证中学综合素质真题及答案.doc
