合泰单片机例程资料，HT66FXX+FLASH例程,源码学习.rar.pdf-资料库

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目录例 1：2 输入逻辑门 ......................................................................................................................... 4 例 2：多输入逻辑门 ........................................................................................................................ 4 例 3：多数表决电路 ........................................................................................................................ 5 例 4：二位比较器 ............................................................................................................................ 6 例 5：映射报告（Map Report） .................................................................................................... 7 例 6：2 选 1 多路选择器：if 语句.................................................................................................. 7 例 7：4 选 1 多路选择器：模块例化 ............................................................................................. 9 例 8：4 选 1 多路选择器：case 语句 ........................................................................................... 10 例 9：一个 4 位 2 选 1 多路选择器 ............................................................................................. 11 例 10：通用多路选择器：参数（Parameter） ........................................................................... 12 例 11：毛刺（Glitches） ............................................................................................................... 13 例 12：7 段译码器：逻辑方程 ..................................................................................................... 14 例 13：7 段译码器：case 语句..................................................................................................... 15 例 14：复用 7 段显示管 ................................................................................................................ 16 例 15：7 段显示管：x7seg 和 x7segb .......................................................................................... 17 例 16：使用 Verilog 任务（Task）的 4 位比较器 ........................................................................ 22 例 17：使用关系运算符的 N 位比较器 ....................................................................................... 23 例 18：3-8 译码器：逻辑方程 ..................................................................................................... 24 例 19：3-8 译码器：for 循环 ........................................................................................................ 24 例 20：8-3 编码器：逻辑方程 ..................................................................................................... 25 例 21：8-3 编码器：for 循环 ........................................................................................................ 26 例 22：8-3 优先编码器 ................................................................................................................. 26 例 23：4 位二进制-BCD 码转换器：逻辑方程 ............................................................................ 27 例 24：8 位二进制-BCD 码转换器 ................................................................................................ 28 例 25：4 位二进制到格雷码的转换器 ......................................................................................... 29 例 26：4 位格雷码到二进制码的转换器 ..................................................................................... 29 例 27：四位加法器：逻辑表达式 ................................................................................................ 30 例 28: 四位加法器：行为描述 ..................................................................................................... 31 例 29：N 位加法器：行为描述 .................................................................................................... 32 例 30:四位加/减法器:逻辑表达式 ................................................................................................ 32 例 31：N 位减法器：行为描述 .................................................................................................... 33 例 32：四位移位器 ........................................................................................................................ 33 例 33：与常数相乘 ........................................................................................................................ 34 例 34：四位乘法器 ........................................................................................................................ 34 例 35：用 task 实现 8 位除法电路 ............................................................................................... 35 例 36：四位 ALU ............................................................................................................................ 37 例 37：边沿触发的 D 触发器 ....................................................................................................... 38 例 38：带有置位和清零端的边沿 D 触发器 ............................................................................... 39 例 39：Verilog 中的 D 触发器 ....................................................................................................... 39 例 40：带异步清零和置位端的 D 触发器 ................................................................................... 40 例 41：2 分频计数器 ..................................................................................................................... 40 例 42：一位寄存器 ........................................................................................................................ 41

例 43：4 位寄存器......................................................................................................................... 42 例 44：N 位寄存器 ........................................................................................................................ 42 例 45：移位寄存器 ........................................................................................................................ 43 例 46：环形计数器 ........................................................................................................................ 43 例 47：防抖按钮............................................................................................................................ 44 例 48：时钟脉冲............................................................................................................................ 45 例 49：3 位计数器......................................................................................................................... 45 例 50：模-5 计数器 ....................................................................................................................... 46 例 51：N 位计数器 ........................................................................................................................ 47 例 52：时钟分频器：模-10K 计数器 ........................................................................................... 48 例 53：任意波形的产生 ................................................................................................................ 52 例 54：脉冲宽度调制器（PWM） ............................................................................................... 53 例 56：把开关数据加载到一个寄存器 ........................................................................................ 53 例 57：把数据移入一个移位寄存器 ............................................................................................ 54 例 58：7 段显示管的滚动显示 ..................................................................................................... 56 例 59：Fibonacci 序列 ................................................................................................................... 59 例 60：序列检测器 ........................................................................................................................ 61 例 61：门锁代码............................................................................................................................ 64 例 62：交通灯................................................................................................................................ 67 例 63：GCD 算法(1) ....................................................................................................................... 70 例 64：GCD 算法(2) ....................................................................................................................... 71 例 65：整数平方根算法实现 ........................................................................................................ 76 例 66：GCD 算法(3) ...................................................................................................................... 82 例 67：整数平方根(2) ................................................................................................................... 84 例 68： Verilog ROM ..................................................................................................................... 87 例 69：分布式 RAM/ROM ............................................................................................................. 89 例 70：块 RAM/ROM ..................................................................................................................... 91 例 71：VGA – 条纹显示 ................................................................................................................ 92 例 72：VGA – PROM ...................................................................................................................... 96 例 73：块 ROM 中的 sprite ........................................................................................................... 99 例 74：屏幕保护程序 .................................................................................................................. 102 例 75：键盘 ................................................................................................................................. 105 例 76：鼠标 ................................................................................................................................. 108

例 1：2 输入逻辑门 //Example 1:2-input gates Module gates2( Input wire a; Input wire b; Output wire[5:0] z ); assign z[5]=a&b; assign z[4]=～(a&b); assign z[3]=a|b; assign z[2]= ～(a|b); assign z[1]=aˆb; assign z[0]=a～ˆb; endmodule 例 2：多输入逻辑门 //Example 2: 4-input gates module gates4( input wire [4:1] x, output wire [6:1] z ); assign z[6] = &x; assign z[5] = ~&x; assign z[4] = |x; assign z[3] = ~|x; assign z[2] = ^x; assign z[1] = ~^x; endmodule //Example 2: 4-input gates - top level module gates4_top( input wire [3:0] sw, output wire [5:0] ld ); gates4 X4 (.x(sw), .z(ld) ); endmodule

例 3：多数表决电路 // Example 3: majority4 module majority4 ( input wire a, input wire b, input wire c, input wire d, output wire f ); assign f = b & c & d | a & c & d | a & b & d | a & b & c; endmodule // Example 3: majority4 – top-level module majority4_top ( input wire [3:0] sw, output wire [0:0] ld ); majority4 M1 ( .a(sw[3]), .b(sw[2]), .c(sw[1]), .d(sw[0]), .f(ld[0]) ); endmodule

例 4：二位比较器 // Example 4: comp2bit module comp2bit ( input wire [1:0] a, input wire [1:0] b, output wire a_eq_b, output wire a_gt_b, output wire a_lt_b ); assign a_eq_b = ~b[1] & ~b[0] & ~a[1] & ~a[0] | ~b[1] & b[0] & ~a[1] & a[0] | b[1] & ~b[0] & a[1] & ~a[0] | b[1] & b[0] & a[1] & a[0]; assign a_gt_b = ~b[1] & a[1] | ~b[1] & ~b[0] & a[0] | ~b[0] & a[1] & a[0]; assign a_lt_b = b[1] & ~a[1] | b[1] & b[0] & ~a[0] | b[0] & ~a[1] & ~a[0]; endmodule // Example 4: 2-bit comparator _top-level module comp2bit_top( input wire [3:0] sw, output wire [2:0] ld ); comp2bit U1 (.a(sw[3:2]), .b(sw[1:0]), .a_eq_b(ld[1]), .a_gt_b(ld[0]), .a_lt_b(ld[2]) ); endmodule

例 5：映射报告（Map Report） Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 6 out of 9,312 1% Logic Distribution: Number of occupied Slices: 3 out of 4,656 1% Number of Slices containing only related logic: 3 out of 3 100% Number of Slices containing unrelated logic: 0 out of 3 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 6 out of 9,312 1% Number of bonded IOBs: 8 out of 232 3% 例 1 映射报告中的 Design summary Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 1 out of 9,312 1% Logic Distribution: Number of occupied Slices: 1 out of 4,656 1% Number of Slices containing only related logic: 1 out of 1 100% Number of Slices containing unrelated logic: 0 out of 1 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 1 out of 9,312 1% Number of bonded IOBs: 5 out of 232 2% 例 3 映射报告中的 Design summary 例 6：2 选 1 多路选择器：if 语句 // 例 6a：使用逻辑方程实现的 2 选 1 MUX module mux21a ( input wire a, input wire b, input wire s, output wire y ); assign y = ~ s & a | s & b; endmodule

// 例 6b：使用 if 语句实现的 2 选 1 MUX module mux21b ( input wire a, input wire b, input wire s, output reg y ); always @ (a, b, s) if (s == 0) y = a; else y = b; endmodule // 例 6c：使用 if 语句实现的 2 选 1 MUX module mux21c ( input wire a, input wire b, input wire s, output reg y ); always @ ( * ) if (s == 0) y = a; else y = b; endmodule // 例 6d：使用“？”实现的 2 选 1 MUX module mux21d ( input wire a, input wire b, input wire s, output wire y ); assign y = s ? b : a; endmodule

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