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IMX6ULL参考手册.pdf
Chapter 1: Introduction
About This Document
Audience
Organization
Suggested Reading
General Information
Related Documentation
Conventions
Register Access
Register Diagram Field Access Type Legend
Register Macro Usage
Signal Conventions
Acronyms and Abbreviations
Introduction
Target Applications
Features
Architectural Overview
Simplified Block Diagram
Architectural Partitioning
Endianness Support
Memory Interfaces
Chapter 2: Memory Maps
Memory system overview
ARM Platform Memory Map
DMA memory map
Chapter 3: Interrupts and DMA Events
Overview
Cortex A7 interrupts
SDMA event mapping
Chapter 4: External Signals and Pin Multiplexing
Overview
Muxing Options
Chapter 5: Fusemap
Boot Fusemap
Lock Fusemap
Fusemap Descriptions Table
Chapter 6: External Memory Controllers
Overview
Multi-mode DDR controller (MMDC) overview and feature summary
EIM-PSRAM/NOR flash controller overview
EIM features
EIM boot scenarios
EIM boot configuration
OneNAND requirements
Chapter 7: System Debug
Overview
Chip and ARM Platform Debug Architecture
Debug Features
Debug system components
AMBA Trace Bus (ATB)
ATB replicator
Embedded Cross Triggering
Cross-Trigger Matrix (CTM)
Cross-Trigger Interface (CTI)
Debug Access Port (DAP)
Chip-Specific SJC Features
JTAG Disable Mode
JTAG ID
System JTAG Controller - SJC
System JTAG controller main features
SJC TAP Port
SJC main blocks
Smart DMA (SDMA) core
SDMA On Chip Emulation Module (OnCE) Feature Summary
Other SDMA Debug Functionality
SDMA ROM Patching
Miscellaneous
Clock/Reset/Power
Supported tools
Chapter 8: System Boot
Overview
Boot modes
Boot mode pin settings
High-level boot sequence
Boot From Fuses mode (BOOT_MODE[1:0] = 00b)
Serial Downloader
Internal Boot mode (BOOT_MODE[1:0] = 0b10)
Boot security settings
Device configuration
Boot eFUSE descriptions
GPIO boot overrides
Device Configuration Data (DCD)
Device initialization
Internal ROM/RAM memory map
Boot block activation
Clocks at boot time
Enabling MMU and caches
Exception handling
Interrupt handling during boot
Persistent bits
Boot devices (internal boot)
NOR flash/OneNAND using EIM interface
NOR flash boot operation
OneNAND flash boot operation
IOMUX configuration for EIM devices
NAND flash
NAND eFUSE configuration
NAND flash boot flow and Boot Control Blocks (BCB)
Firmware configuration block
Discovered Bad Block Table (DBBT)
Bad block handling in ROM
Read-retry handling in the ROM
Toggle mode DDR NAND boot
GPMI and BCH clocks configuration
Setup DMA for DDR transfers
Reconfigure timing and speed using values in FCB
Typical NAND page organization
BCH ECC page organization
Metadata
IOMUX configuration for NAND
Expansion device
Expansion device eFUSE configuration
MMC and eMMC boot
SD, eSD, and SDXC
IOMUX configuration for SD/MMC
Redundant boot support for expansion device
Serial ROM through SPI
Serial ROM eFUSE configuration
ECSPI boot
ECSPI IOMUX pin configuration
QuadSPI serial flash memory boot
QuadSPI eFUSE configuration
QuadSPI serial flash BOOT operation
QuadSPI configuration parameters
IOMUX configuration for QSPI devices
QuadSPI boot flow chart
Program image
Image Vector Table and Boot Data
Image vector table structure
Boot data structure
Device Configuration Data (DCD)
Write data command
Check data command
NOP command
Unlock command
Plugin image
Serial Downloader
USB
USB configuration details
IOMUX configuration for USB
UART
UART configuration details
UART eFUSE configuration
IOMUX configuration for UART
Serial Download Protocol (SDP)
SDP commands
READ_REGISTER
WRITE_REGISTER
WRITE_FILE
ERROR_STATUS
DCD_WRITE
SKIP_DCD_HEADER
JUMP_ADDRESS
Recovery devices
USB low-power boot
SD/MMC manufacture mode
High-Assurance Boot (HAB)
HAB API vector table addresses
Chapter 9: Multimedia
Display and graphics subsystem
Electrophoretic Display Controller
PiXel Processing Pipeline (PXP)
LCD Interface (LCDIF)
CMOS Sensor Interface (CSI)
Audio subsystem
Audio Subsystem Module Overview
Medium Quality Sound (MQS)
Synchronous Audio Interface (SAI)
Enhanced Serial Audio Interface (ESAI)
Sony/Philips Digital Interface (SPDIF)
Asynchronous Sample Rate Converter (ASRC)
Chapter 10: Clock and Power Management
Introduction
Device Power Management Architecture Components
Centralized components of clock generation and management
Centralized components of power generation, distribution and management
Reset generation and distribution system
Power and clock management framework
Clock Management
Centralized components of clock management system
Clock generation
Crystal Oscillator (XTALOSC)
Low Voltage Differential Signaling (LVDS) I/O ports
PLLs
General PLL Control and Status Functions
CCM
Low Power Clock Gating unit (LPCG)
Peripheral components of clock management system
Interface and functional clock
Block level clock management
Master clock protocol
Slave clock protocol
Clock Domain(s)
Domain level clock management
Domain dependencies
Power management
Centralized Components of Power Management System
Integrated PMU
Digital LDO Regulators
Analog LDO regulators
USB LDO
SNVS regulator
GPC - General Power Controller
SRC - System reset Controller
Power domain(s)
Power distribution
Domain Memory and domain logic state retention in case of Power Gating
Power Gating Domain Management
ARM Core Platform
SOC_PD
SoC
Power Gating domain dependencies
Voltage domains
Voltage domain management
Dynamic
Voltage Scaling
Static
Standby Leakage reduction (SLR)
ANALOG PHYs IPs
System domains layout
Power management techniques
Power saving techniques
Thermal-aware power management
Peripheral Power management
Main memory power management
Video-Graphics system power management
IO power reduction
Examples of External Power Supply Interface
ONOFF (Button)
Chapter 11: System Security
Overview
Central Security Unit (CSU)
CSU Overview
CSU Features
CSU Functional Description
CSU Peripheral Access Policy
Secure Non-Volatile Storage (SNVS)
SNVS Overview
Tamper Detection
Data Co-Processor (DCP)
High-Assurance Boot (HAB)
System JTAG Controller (SJC)
Chapter 12: ARM Cortex A7 Platform (CA7)
Overview
External Signals
Clocks
Platform Configuration
Low-Power and Performance
Chapter 13: Analog-to-Digital Converter (ADC)
Overview
Features
ADC I/F block diagram
ADC block diagram
ADC module interface
Modes of Operation
External Signals
Functional Description
Clock Select and Divide Control
Voltage Reference Selection
Conversion Control
Initiating Conversions
Completing Conversions
Aborting Conversions
Power Control
Sample Time and Total Conversion Time
Conversion Time Examples
Typical conversion time configuration
Long conversion time configuration
Short conversion time configuration
Hardware Average Function
Automatic Compare Function
Calibration Function
User Defined Offset Function
MCU Wait Mode Operation
MCU Stop Mode Operation
Stop Mode With ADACK Disabled
Stop Mode With ADACK Enabled
Initialization Information
ADC Module Initialization Example
Initialization Sequence
Pseudo-Code Example
Application Information
Sources of Error
Sampling Error
Pin Leakage Error
Noise-Induced Errors
Code Width and Quantization Error
Linearity Errors
Code Jitter, Non-Monotonicity, and Missing Codes
Memory map and register definition
ADCx
ADCx_HC0
ADCx_HS
ADCx_R0
ADCx_CFG
ADCx_GC
ADCx_GS
ADCx_CV
ADCx_OFS
ADCx_CAL
Memory map and register definition
ADCx
ADCx_HC0
ADCx_HCn
ADCx_HS
ADCx_R0
ADCx_Rn
ADCx_CFG
ADCx_GC
ADCx_GS
ADCx_CV
ADCx_OFS
ADCx_CAL
Chapter 14: AHB to IP Bridge (AIPSTZ)
Overview
Features
Clocks
Functional Description
Access Protections
Access Support
Initialization Information
Security Block
AIPSTZ Memory Map/Register Definition
AIPSTZx
AIPSTZx_MPR
AIPSTZx_OPACR
AIPSTZx_OPACR1
AIPSTZx_OPACR2
AIPSTZx_OPACR3
AIPSTZx_OPACR4
Chapter 15: AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
Overview
Clocks
APBH DMA
NAND Read Status Polling Example
APBH Memory Map/Register Definition
APBH
APBH_CTRL0n
APBH_CTRL1n
APBH_CTRL2n
APBH_CHANNEL_CTRLn
APBH_DEVSEL
APBH_DMA_BURST_SIZE
APBH_DEBUG
APBH_CHn_CURCMDAR
APBH_CHn_NXTCMDAR
APBH_CHn_CMD
APBH_CHn_BAR
APBH_CHn_SEMA
APBH_CHn_DEBUG1
APBH_CHn_DEBUG2
APBH_VERSION
Chapter 16: Asynchronous Sample Rate Converter (ASRC)
Overview
Features
Modes of Operation
Data Transfer Schemes
Data Input Modes
Data Output Modes
Word Alignment Supported
Input Data Alignment Modes
Output Data Alignment Modes
Clocks
Interrupts
DMA requests
Functional Description
Algorithm Description
Signal processing flow
Operation of the Filter
Support of Physical Clocks
Startup Procedure
ASRC Memory Map/Register Definition
ASRC
ASRC_ASRCTR
ASRC_ASRIER
ASRC_ASRCNCR
ASRC_ASRCFG
ASRC_ASRCSR
ASRC_ASRCDR1
ASRC_ASRCDR2
ASRC_ASRSTR
ASRC_ASRPMnn
ASRC_ASRTFR1
ASRC_ASRCCR
ASRC_ASRDIn
ASRC_ASRDOn
ASRC_ASRIDRHA
ASRC_ASRIDRLA
ASRC_ASRIDRHB
ASRC_ASRIDRLB
ASRC_ASRIDRHC
ASRC_ASRIDRLC
ASRC_ASR76K
ASRC_ASR56K
ASRC_ASRMCRA
ASRC_ASRFSTA
ASRC_ASRMCRB
ASRC_ASRFSTB
ASRC_ASRMCRC
ASRC_ASRFSTC
ASRC_ASRMCR1n
Chapter 17: 40-BIT Correcting ECC Accelerator (BCH)
Overview
Operation
BCH Limitations and Assumptions
Flash Page Layout
Determining the ECC layout for a device
4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata, Assuming GF(213)
4K+128 flash, 10 bytes metadata, 1024 byte data blocks, separate metadata, assuming GF(213) for data and GF(214) for metadata
Data Buffers in System Memory
Memory to Memory (Loopback) Operation
Programming the BCH/GPMI Interfaces
BCH Encoding for NAND Writes
DMA Structure Code Example
Using the BCH Encoder
BCH Decoding for NAND Reads
DMA Structure Code Example
Using the Decoder
Interrupts
Behavior During Reset
BCH Memory Map/Register Definition
BCH
BCH_CTRLn
BCH_STATUS0n
BCH_MODEn
BCH_ENCODEPTRn
BCH_DATAPTRn
BCH_METAPTRn
BCH_LAYOUTSELECTn
BCH_FLASH0LAYOUT0n
BCH_FLASH0LAYOUT1n
BCH_FLASH1LAYOUT0n
BCH_FLASH1LAYOUT1n
BCH_FLASH2LAYOUT0n
BCH_FLASH2LAYOUT1n
BCH_FLASH3LAYOUT0n
BCH_FLASH3LAYOUT1n
BCH_DEBUG0n
BCH_DBGKESREADn
BCH_DBGCSFEREADn
BCH_DBGSYNDGENREADn
BCH_DBGAHBMREADn
BCH_BLOCKNAMEn
BCH_VERSIONn
BCH_DEBUG1n
Chapter 18: Clock Controller Module (CCM)
Overview
Features
CCM Block Diagram
External Signals
CCM Clock Tree
System Clocks
Functional Description
Clock Generation
External Low Frequency Clock - CKIL
CKIL synchronizing to IPG_CLK
External High Frequency Clock - CKIH and internal oscillator
PLL reference clock
ARM PLL
USB PLLs
System PLL
Audio / Video PLL
Ethernet PLL
Phase Fractional Dividers (PFD)
CCM internal clock generation
Clock Switcher
PLL bypass procedure
PLL clock change
Clock Root Generator
Initial values controlled by the System JTAG Controller (SJC).
Divider change handshake
Disabling / Enabling PLLs
Clock Switching Multiplexers
Low Power Clock Gating module (LPCG)
MMDC handshake
DVFS support
Power modes
RUN mode
WAIT mode
Entering WAIT mode
Exiting WAIT mode
STOP mode
Entering STOP mode
Exiting STOP mode
CCM Memory Map/Register Definition
CCM
CCM_CCR
CCM_CCDR
CCM_CSR
CCM_CCSR
CCM_CACRR
CCM_CBCDR
CCM_CBCMR
CCM_CSCMR1
CCM_CSCMR2
CCM_CSCDR1
CCM_CS1CDR
CCM_CS2CDR
CCM_CDCDR
CCM_CHSCCDR
CCM_CSCDR2
CCM_CSCDR3
CCM_CDHIPR
CCM_CLPCR
CCM_CISR
CCM_CIMR
CCM_CCOSR
CCM_CGPR
CCM_CCGR0
CCM_CCGR1
CCM_CCGR2
CCM_CCGR3
CCM_CCGR4
CCM_CCGR5
CCM_CCGR6
CCM_CMEOR
CCM Analog Memory Map/Register Definition
CCM_ANALOG
CCM_ANALOG_PLL_ARMn
CCM_ANALOG_PLL_USB1n
CCM_ANALOG_PLL_USB2n
CCM_ANALOG_PLL_SYSn
CCM_ANALOG_PLL_SYS_SS
CCM_ANALOG_PLL_SYS_NUM
CCM_ANALOG_PLL_SYS_DENOM
CCM_ANALOG_PLL_AUDIOn
CCM_ANALOG_PLL_AUDIO_NUM
CCM_ANALOG_PLL_AUDIO_DENOM
CCM_ANALOG_PLL_VIDEOn
CCM_ANALOG_PLL_VIDEO_NUM
CCM_ANALOG_PLL_VIDEO_DENOM
CCM_ANALOG_PLL_ENETn
CCM_ANALOG_PFD_480n
CCM_ANALOG_PFD_528n
CCM_ANALOG_MISC0n
CCM_ANALOG_MISC1n
CCM_ANALOG_MISC2n
Chapter 19: CMOS Sensor Interface (CSI)
Overview
External Signals
Clocks
Principles of Operation
Data Transfer with the Embedded DMA Controllers
Gated Clock Mode
Non-Gated Clock Mode
CCIR656 Interlace Mode
CCIR656 Progressive Mode
Error Correction for CCIR656 Coding
Deinterlacer
Interrupt Generation
Start Of Frame Interrupt (SOF_INT)
End Of Frame Interrupt (EOF_INT)
Change Of Field Interrupt (COF_INT)
CCIR Error Interrupt (ECC_INT)
RxFIFO Full Interrupt (RxFF_INT)
Statistic FIFO Full Interrupt (STATFF_INT)
RxFIFO Overrun Interrupt (RFF_OR_INT)
Statistic FIFO Overrun Interrupt (SFF_OR_INT)
Frame Buffer1 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB1)
Frame Buffer2 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB2)
Statistic FIFO DMA Transfer Done Interrupt (DMA_TSF_DONE_SFF)
AHB Bus Response Error Interrupt (HRESP_ERR_INT)
DMA Field 0 Transfer Done Interrupt (DMA_FIELD0_DONE)
DMA Field 1 Transfer Done Interrupt (DMA_FIELD1_DONE)
Base Address Change Error Interrupt (BASEADDR_CHANGE_ERROR)
Data Packing Style
STAT FIFO Path
CSI Memory Map/Register Definition
CSI
CSI_CSICR1
CSI_CSICR2
CSI_CSICR3
CSI_CSISTATFIFO
CSI_CSIRFIFO
CSI_CSIRXCNT
CSI_CSISR
CSI_CSIDMASA_STATFIFO
CSI_CSIDMATS_STATFIFO
CSI_CSIDMASA_FB1
CSI_CSIDMASA_FB2
CSI_CSIFBUF_PARA
CSI_CSIIMAG_PARA
CSI_CSICR18
CSI_CSICR19
Chapter 20: Enhanced Configurable SPI (ECSPI)
Overview
Features
Modes and Operations
External Signals
Clocks
Functional Description
Master Mode
Slave Mode
Low Power Modes
Operations
Typical Master Mode
Master Mode with SPI_RDY
Master Mode with Wait States
Master Mode with SS_CTL[3:0] Control
Master Mode with Phase Control
Typical Slave Mode
Reset
Interrupts
DMA
Byte Order
Initialization
Applications
ECSPI Memory Map/Register Definition
ECSPIx
ECSPIx_RXDATA
ECSPIx_TXDATA
ECSPIx_CONREG
ECSPIx_CONFIGREG
ECSPIx_INTREG
ECSPIx_DMAREG
ECSPIx_STATREG
ECSPIx_PERIODREG
ECSPIx_TESTREG
ECSPIx_MSGDATA
Chapter 21: External Interface Module (EIM)
Overview
Features
Modes of Operation
Asynchronous Mode
Asynchronous Page Read Mode
Multiplexed Address/Data Mode
Burst Clock Mode
Low Power Modes
Boot Mode
External Signals
Other Important Block I/O Signals Internal to the SoC
Clocks
Chip Select Memory Map
Functional Description
Bus Sizing Configuration
8 BIT PORT SUPPORT
MOTOROLA 68000
INTEL 386
EIM Operational Modes
Burst Mode (Synchronous) Memory Operation
Burst Clock Divisor (BCD)
Burst Clock Start (BCS)
Multiplexed Address/Data Mode Support
Mixed Master/Memory Burst Modes Support
AXI (Master) Bus Cycles Support
WAIT_B Signal, RWSC and WWSC bit fields Usage
IPS Register Interface
MRS Set for PSRAM
EIM Access Termination
Error Conditions
DTACK Mode
EIM_GRANT / EIM_BUSY Handshake Description
LPMD / LPACK Handshake Description
Endianness
Strobe Signal Use
Initialization Information
Booting from EIM
Typical Application
Access to Intel Sibley Flash
Intel Sibley Flash Asynchronous Mode Configuration
Intel Sibley Flash Synchronous Mode Configuration
Intel Sibley Flash Utility
Access to MDOC Device
MDOC Device Boot
MDOC Device Asynchronous Mode Configuration
MDOC Device Utility
Access to Micron PSRAM
Micron PSRAM Asynchronous Mode Configuration
Micron PSRAM Synchronous Mode Configuration
Access to Samsung OneNAND
Samsung OneNAND Boot
Samsung OneNAND Asynchronous Mode Configuration
Samsung OneNAND Synchronous Mode Configuration
Samsung OneNAND Utility
Access to Samsung UtRAM
Samsung UtRAM Asynchronous Mode Configuration
Samsung UtRAM Synchronous Mode Configuration
Access to Spansion Flash
Spansion Flash Asynchronous Mode Configuration
Spansion Flash Synchronous Mode Configuration
Spansion Flash Utility
8 bit support
External Bus Timing Diagrams
Asynchronous Read Memory Accesses Timing Diagram
Asynchronous Write Memory Accesses Timing Diagram
Asynchronous Read/Write Memory Accesses Timing Diagram
Asynchronous Read/Write Using RAL, WAL and CSREC
Consecutive Asynchronous Write Memory Accesses Timing Diagram
Consecutive Asynchronous Read Memory Accesses Timing Diagram
Burst (Synchronous Mode) Read Memory Accesses Timing Diagram - BCD=0
Burst (Synchronous Mode) Read Memory Accesses Timing Diagram - BCD=1
Burst (Synchronous Mode) Write Memory Access Timing - BCD=1
Asynchronous Page Mode Access
DTACK Mode - AXI Single Access
DTACK Mode - AXI Single Write Access
DTACK Mode - AXI Burst Access
EIM Memory Map/Register Definition
EIM
EIM_CSnGCR1
EIM_CSnGCR2
EIM_CSnRCR1
EIM_CSnRCR2
EIM_CSnWCR1
EIM_CSnWCR2
EIM_WCR
Chapter 22: 10/100-Mbps Ethernet MAC (ENET)
Introduction
Overview
Features
Ethernet MAC features
IP protocol performance optimization features
IEEE 1588 features
Block diagram
External Signals
Clocks
Memory map/register definition
ENETx
ENETx_EIR
ENETx_EIMR
ENETx_RDAR
ENETx_TDAR
ENETx_ECR
ENETx_MMFR
ENETx_MSCR
ENETx_MIBC
ENETx_RCR
ENETx_TCR
ENETx_PALR
ENETx_PAUR
ENETx_OPD
ENETx_TXIC
ENETx_RXIC
ENETx_IAUR
ENETx_IALR
ENETx_GAUR
ENETx_GALR
ENETx_TFWR
ENETx_RDSR
ENETx_TDSR
ENETx_MRBR
ENETx_RSFL
ENETx_RSEM
ENETx_RAEM
ENETx_RAFL
ENETx_TSEM
ENETx_TAEM
ENETx_TAFL
ENETx_TIPG
ENETx_FTRL
ENETx_TACC
ENETx_RACC
ENETx_RMON_T_DROP
ENETx_RMON_T_PACKETS
ENETx_RMON_T_BC_PKT
ENETx_RMON_T_MC_PKT
ENETx_RMON_T_CRC_ALIGN
ENETx_RMON_T_UNDERSIZE
ENETx_RMON_T_OVERSIZE
ENETx_RMON_T_FRAG
ENETx_RMON_T_JAB
ENETx_RMON_T_COL
ENETx_RMON_T_P64
ENETx_RMON_T_P65TO127
ENETx_RMON_T_P128TO255
ENETx_RMON_T_P256TO511
ENETx_RMON_T_P512TO1023
ENETx_RMON_T_P1024TO2047
ENETx_RMON_T_P_GTE2048
ENETx_RMON_T_OCTETS
ENETx_IEEE_T_DROP
ENETx_IEEE_T_FRAME_OK
ENETx_IEEE_T_1COL
ENETx_IEEE_T_MCOL
ENETx_IEEE_T_DEF
ENETx_IEEE_T_LCOL
ENETx_IEEE_T_EXCOL
ENETx_IEEE_T_MACERR
ENETx_IEEE_T_CSERR
ENETx_IEEE_T_SQE
ENETx_IEEE_T_FDXFC
ENETx_IEEE_T_OCTETS_OK
ENETx_RMON_R_PACKETS
ENETx_RMON_R_BC_PKT
ENETx_RMON_R_MC_PKT
ENETx_RMON_R_CRC_ALIGN
ENETx_RMON_R_UNDERSIZE
ENETx_RMON_R_OVERSIZE
ENETx_RMON_R_FRAG
ENETx_RMON_R_JAB
ENETx_RMON_R_RESVD_0
ENETx_RMON_R_P64
ENETx_RMON_R_P65TO127
ENETx_RMON_R_P128TO255
ENETx_RMON_R_P256TO511
ENETx_RMON_R_P512TO1023
ENETx_RMON_R_P1024TO2047
ENETx_RMON_R_P_GTE2048
ENETx_RMON_R_OCTETS
ENETx_IEEE_R_DROP
ENETx_IEEE_R_FRAME_OK
ENETx_IEEE_R_CRC
ENETx_IEEE_R_ALIGN
ENETx_IEEE_R_MACERR
ENETx_IEEE_R_FDXFC
ENETx_IEEE_R_OCTETS_OK
ENETx_ATCR
ENETx_ATVR
ENETx_ATOFF
ENETx_ATPER
ENETx_ATCOR
ENETx_ATINC
ENETx_ATSTMP
ENETx_TGSR
ENETx_TCSRn
ENETx_TCCRn
Functional description
Ethernet MAC frame formats
Pause Frames
Magic packets
IP and higher layers frame format
Ethernet types
IPv4 datagram format
IPv6 datagram format
Internet Control Message Protocol (ICMP) datagram format
User Datagram Protocol (UDP) datagram format
TCP datagram format
IEEE 1588 message formats
Transport encapsulation
UDP/IP
Native Ethernet (PTPv2)
PTP header
PTPv1 header
PTPv2 header
MAC receive
Collision detection in half-duplex mode
Preamble processing
MAC address check
Unicast address check
Multicast and unicast address resolution
Broadcast address reject
Miss-bit implementation
Frame length/type verification: payload length check
Frame length/type verification: frame length check
VLAN frames processing
Pause frame termination
CRC check
Frame padding removal
MAC transmit
Frame payload padding
MAC address insertion
CRC-32 generation
Inter-packet gap (IPG)
Collision detection and handling — half-duplex operation only
Full-duplex flow control operation
Remote device congestion
Local device/FIFO congestion
Magic packet detection
Sleep mode
Magic packet detection
Wakeup
IP accelerator functions
Checksum calculation
Additional padding processing
32-bit Ethernet payload alignment
Receive processing
Transmit processing
Received frame discard
IPv4 fragments
IPv6 support
Receive processing
Transmit processing
Resets and stop controls
Hardware reset
Soft reset
Hardware freeze
Graceful stop
Graceful transmit stop (GTS)
Graceful receive stop (GRS)
Graceful stop interrupt (GRA)
IEEE 1588 functions
Adjustable timer module
Adjustable timer implementation
Transmit timestamping
Receive timestamping
Time synchronization
Input Capture and Output Compare
Input capture
Output compare
DMA requests
FIFO thresholds
Receive FIFO
Transmit FIFO
Loopback options
Legacy buffer descriptors
Legacy receive buffer descriptor
Legacy transmit buffer descriptor
Enhanced buffer descriptors
Enhanced receive buffer descriptor
Enhanced transmit buffer descriptor
Client FIFO application interface
Data structure description
Data structure examples
Frame status
FIFO protection
Transmit FIFO underflow
Transmit FIFO overflow
Receive FIFO overflow
PHY management interface
MDIO clause 22 frame format
MDIO clause 45 frame format
MDIO clock generation
MDIO operation
Ethernet interfaces
RMII interface
MII Interface — transmit
Transmit with collision — half-duplex
MII interface — receive
Interrupt coalescence
Interrupt coalescence setup
Updating the frame count threshold on-the-fly
Updating the timer threshold on-the-fly
Chapter 23: Electrophoretic Display Controller (EPDC)
Overview
EPDC Block Diagram
External Signals
Programming Model
Assumptions
Register Space (Write/Set/Clear/Toggle)
Interrupts
Interrupt Sources
Enabling/Masking Interrupts
Handling/Clearing Interrupts
Controller Setup
Memory Requirements
Panel Architecture Configuration
TFT Panel Timing Configuration
Source Driver and Pixel Clock Configuration
Initializing the Display
Reset/Clocks and Buffer Preparation
Performing an Initialization Display Update
Update Buffer Analysis Functions
Waveform Mode Selection (AUTOWV)
Panel Interface Generator (Pigeon Mode)
Display Update Programming
Initiating a Display Update
Update Processing and Collisions
Multiple Update Flow
Architectural Clock Gating (Low Power Mode)
Performance Tuning and Considerations
Memory and Bus Bandwidth Requirements
Pixel Latency FIFO
Basic Watermarking Control
Update/Refresh Tuning (VSCAN_HOLDOFF)
System-Level Arbitration Control
EPDC Memory Map/Register Definition
EPDC
EPDC_CTRLn
EPDC_WB_ADDR_TCE
EPDC_WVADDR
EPDC_WB_ADDR
EPDC_RES
EPDC_FORMATn
EPDC_WB_FIELD0
EPDC_WB_FIELD1
EPDC_WB_FIELD2
EPDC_WB_FIELD3
EPDC_FIFOCTRLn
EPDC_UPD_ADDR
EPDC_UPD_STRIDE
EPDC_UPD_CORD
EPDC_UPD_SIZE
EPDC_UPD_CTRLn
EPDC_UPD_FIXEDn
EPDC_TEMP
EPDC_AUTOWV_LUT
EPDC_LUT_STANDBY1n
EPDC_LUT_STANDBY2n
EPDC_TCE_CTRLn
EPDC_TCE_SDCFGn
EPDC_TCE_GDCFGn
EPDC_TCE_HSCAN1n
EPDC_TCE_HSCAN2n
EPDC_TCE_VSCANn
EPDC_TCE_OEn
EPDC_TCE_POLARITYn
EPDC_TCE_TIMING1n
EPDC_TCE_TIMING2n
EPDC_TCE_TIMING3n
EPDC_PIGEON_CTRL0n
EPDC_PIGEON_CTRL1n
EPDC_IRQ_MASK1n
EPDC_IRQ_MASK2n
EPDC_IRQ1n
EPDC_IRQ2n
EPDC_IRQ_MASKn
EPDC_IRQn
EPDC_STATUS_LUTS1n
EPDC_STATUS_LUTS2n
EPDC_STATUS_NEXTLUT
EPDC_STATUS_COL1n
EPDC_STATUS_COL2n
EPDC_STATUSn
EPDC_UPD_COL_CORD
EPDC_UPD_COL_SIZE
EPDC_HIST1_PARAM
EPDC_HIST2_PARAM
EPDC_HIST4_PARAM
EPDC_HIST8_PARAM0
EPDC_HIST8_PARAM1
EPDC_HIST16_PARAM0
EPDC_HIST16_PARAM1
EPDC_HIST16_PARAM2
EPDC_HIST16_PARAM3
EPDC_GPIOn
EPDC_VERSION
EPDC_PIGEON_0_0
EPDC_PIGEON_0_1
EPDC_PIGEON_0_2
EPDC_PIGEON_1_0
EPDC_PIGEON_1_1
EPDC_PIGEON_1_2
EPDC_PIGEON_2_0
EPDC_PIGEON_2_1
EPDC_PIGEON_2_2
EPDC_PIGEON_3_0
EPDC_PIGEON_3_1
EPDC_PIGEON_3_2
EPDC_PIGEON_4_0
EPDC_PIGEON_4_1
EPDC_PIGEON_4_2
EPDC_PIGEON_5_0
EPDC_PIGEON_5_1
EPDC_PIGEON_5_2
EPDC_PIGEON_6_0
EPDC_PIGEON_6_1
EPDC_PIGEON_6_2
EPDC_PIGEON_7_0
EPDC_PIGEON_7_1
EPDC_PIGEON_7_2
EPDC_PIGEON_8_0
EPDC_PIGEON_8_1
EPDC_PIGEON_8_2
EPDC_PIGEON_9_0
EPDC_PIGEON_9_1
EPDC_PIGEON_9_2
EPDC_PIGEON_10_0
EPDC_PIGEON_10_1
EPDC_PIGEON_10_2
EPDC_PIGEON_11_0
EPDC_PIGEON_11_1
EPDC_PIGEON_11_2
EPDC_PIGEON_12_0
EPDC_PIGEON_12_1
EPDC_PIGEON_12_2
EPDC_PIGEON_13_0
EPDC_PIGEON_13_1
EPDC_PIGEON_13_2
EPDC_PIGEON_14_0
EPDC_PIGEON_14_1
EPDC_PIGEON_14_2
EPDC_PIGEON_15_0
EPDC_PIGEON_15_1
EPDC_PIGEON_15_2
EPDC_PIGEON_16_0
EPDC_PIGEON_16_1
EPDC_PIGEON_16_2
Chapter 24: Enhanced Periodic Interrupt Timer (EPIT)
Overview
EPIT features
EPIT modes and operations
External signals
Clocks
Functional Description
Operating modes
Operating in set-and-forget mode
Operating in free-running mode
Operations
Compare Event
Counter Value Overwrite
Low-Power Mode Behavior
Debug Mode Behavior
Initialization/ Application Information
Change of Clock Source
EPIT Memory Map/Register Definition
EPITx
EPITx_CR
EPITx_SR
EPITx_LR
EPITx_CMPR
EPITx_CNR
Chapter 25: Enhanced Serial Audio Interface (ESAI)
Overview
Features
Modes of Operation
Normal/Network/On-Demand Mode Selection
Synchronous/Asynchronous Operating Modes
Frame Sync Selection
Shift Direction Selection
External Signals
Serial Transmit 0 Data Pin
Serial Transmit 1 Data Pin
Serial Transmit 2/Receive 3 Data Pin
Serial Transmit 3/Receive 2 Data Pin
Serial Transmit 4/Receive 1 Data Pin
Serial Transmit 5/Receive 0 Data Pin
Receiver Serial Clock
Transmitter Serial Clock
Frame Sync for Receiver
Frame Sync for Transmitter
High Frequency Clock for Transmitter
High Frequency Clock for Receiver
Serial I/O Flags
Clocks
Functional Description
ESAI After Reset
ESAI Interrupt Requests
ESAI DMA Requests from the FIFOs
ESAI Transmit and Receive Shift Registers
ESAI Transmit Shift Registers
ESAI Receive Shift Registers
Initialization Information
ESAI Initialization
ESAI Initialization Examples
Initializing the ESAI using Personal Reset
Initializing the ESAI Transmitter Section
Initializing the ESAI Receiver Section
ESAI Memory Map/Register Definition
ESAI
ESAI_ETDR
ESAI_ERDR
ESAI_ECR
ESAI_ESR
ESAI_TFCR
ESAI_TFSR
ESAI_RFCR
ESAI_RFSR
ESAI_TXn
ESAI_TSR
ESAI_RXn
ESAI_SAISR
ESAI_SAICR
ESAI_TCR
ESAI_TCCR
ESAI_RCR
ESAI_RCCR
ESAI_TSMA
ESAI_TSMB
ESAI_RSMA
ESAI_RSMB
ESAI_PRRC
ESAI_PCRC
Chapter 26: Flexible Controller Area Network (FLEXCAN)
Overview
Block Diagram
FLEXCAN Module Features
Modes of Operation
External Signals
Clocks
Message Buffer Structure
Rx FIFO Structure
Functional Description
Functional Overview
Transmit Process
Arbitration process
Lowest Mailbox number first
Highest Mailbox priority first
Local Priority disabled
Local Priority enabled
Receive Process
Matching Process
Move Process
Move-in
Move-out
Data Coherence
Transmission Abort Mechanism
Message Buffer Inactivation
Message Buffer Lock Mechanism
Rx FIFO
CAN Protocol Related Features
Remote Frames
Overload Frames
Time Stamp
Protocol Timing
Arbitration and Matching Timing
Modes of Operation Details
Freeze Mode
Module Disable Mode
Stop Mode
Interrupts
Initialization/Application Information
FLEXCAN Initialization Sequence
FLEXCAN Memory Map/Register Definition
FLEXCANx
FLEXCANx_MCR
FLEXCANx_CTRL1
FLEXCANx_TIMER
FLEXCANx_RXMGMASK
FLEXCANx_RX14MASK
FLEXCANx_RX15MASK
FLEXCANx_ECR
FLEXCANx_ESR1
FLEXCANx_IMASK2
FLEXCANx_IMASK1
FLEXCANx_IFLAG2
FLEXCANx_IFLAG1
FLEXCANx_CTRL2
FLEXCANx_ESR2
FLEXCANx_CRCR
FLEXCANx_RXFGMASK
FLEXCANx_RXFIR
FLEXCANx_RXIMRn
FLEXCANx_GFWR
Chapter 27: General Power Controller (GPC)
Overview
Clocks
Power Gating Control (PGC)
Overview
Features
GPC Interrupt Controller (INTC)
Interrupt Controller features
GPC Memory Map/Register Definition
GPC
GPC_CNTR
GPC_PGR
GPC_IMR1
GPC_IMR2
GPC_IMR3
GPC_IMR4
GPC_ISR1
GPC_ISR2
GPC_ISR3
GPC_ISR4
PGC Memory Map/Register Definition
PGC
PGC_MEGA_CTRL
PGC_MEGA_PUPSCR
PGC_MEGA_PDNSCR
PGC_MEGA_SR
PGC_CPU_CTRL
PGC_CPU_PUPSCR
PGC_CPU_PDNSCR
PGC_CPU_SR
Chapter 28: General Purpose Input/Output (GPIO)
Overview
Block Diagram
Features
External Signals
Clocks
GPIO Functional Description
GPIO Function
GPIO pad structure
Input Driver
Schmitt trigger
Input keeper
Output Driver
Drive strength
Output keeper
PU / PD / Keeper Logic
Open drain
GPIO Programming
GPIO Read Mode
GPIO Write Mode
Interrupt Control Unit
GPIO Memory Map/Register Definition
GPIOx
GPIOx_DR
GPIOx_GDIR
GPIOx_PSR
GPIOx_ICR1
GPIOx_ICR2
GPIOx_IMR
GPIOx_ISR
GPIOx_EDGE_SEL
Chapter 29: General Purpose Media Interface (GPMI)
Overview
External Signals
Clocks
GPMI NAND Mode
Multiple NAND Support
GPMI NAND Timing and Clocking
Basic NAND Timing
NAND Asynchronous Timing
NAND Asynchronous EDO Mode Timing
NAND ONFI Source Synchronous Mode Timing
NAND Toggle Mode Timing
Hardware BCH Interface
Behavior During Reset
GPMI Memory Map/Register Definition
GPMI
GPMI_CTRL0n
GPMI_COMPARE
GPMI_ECCCTRLn
GPMI_ECCCOUNT
GPMI_PAYLOAD
GPMI_AUXILIARY
GPMI_CTRL1n
GPMI_TIMING0
GPMI_TIMING1
GPMI_TIMING2
GPMI_DATA
GPMI_STAT
GPMI_DEBUG
GPMI_VERSION
GPMI_DEBUG2
GPMI_DEBUG3
GPMI_READ_DDR_DLL_CTRL
GPMI_WRITE_DDR_DLL_CTRL
GPMI_READ_DDR_DLL_STS
GPMI_WRITE_DDR_DLL_STS
Chapter 30: General Purpose Timer (GPT)
Overview
Features
Modes and Operation
External Signals
External Clock Input
Input Capture Trigger Signals
Output Compare Signals
Clocks
Functional Description
Operating Modes
Restart Mode
Free-Run Mode
Operation
Input Capture
Output Compare
Interrupts
Low Power Mode Behavior
Debug Mode Behavior
Initialization/ Application Information
Selecting the Clock Source
GPT Memory Map/Register Definition
GPTx
GPTx_CR
GPTx_PR
GPTx_SR
GPTx_IR
GPTx_OCR1
GPTx_OCR2
GPTx_OCR3
GPTx_ICR1
GPTx_ICR2
GPTx_CNT
Chapter 31: I2C Controller (I2C)
Overview
Features
Modes and operations
External Signals
Clocks
Functional description
I2C system configuration
Arbitration procedure
Clock synchronization
Handshaking
Clock stretching
Peripheral bus accesses
Generation of transfer error on IP bus
Reset
Interrupts
Byte order
Initialization
Initialization sequence
Generation of Start
Post-transfer software response
Generation of Stop
Generation of Repeated Start
Slave mode
Arbitration lost
Software restriction
I2C Memory Map/Register Definition
I2Cx
I2Cx_IADR
I2Cx_IFDR
I2Cx_I2CR
I2Cx_I2SR
I2Cx_I2DR
Chapter 32: IOMUX Controller (IOMUXC)
Overview
Features
Clocks
Functional description
ALT6 and ALT7 extended muxing modes
SW Loopback through SION bit
Daisy chain - multi pads driving same module input pin
IOMUXC GPR Memory Map/Register Definition
IOMUXC_GPR
IOMUXC_GPR_GPR0
IOMUXC_GPR_GPR1
IOMUXC_GPR_GPR2
IOMUXC_GPR_GPR3
IOMUXC_GPR_GPR4
IOMUXC_GPR_GPR5
IOMUXC_GPR_GPR9
IOMUXC_GPR_GPR10
IOMUXC_GPR_GPR14
IOMUXC SNVS Memory Map/Register Definition
IOMUXC_SNVS
IOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE0
IOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE1
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER0
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER1
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER2
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER3
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER4
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER5
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER6
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER7
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER8
IOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER9
IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE
IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B
IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ
IOMUXC_SNVS_SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ
IOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE0
IOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE1
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER0
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER1
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER2
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER3
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER4
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER5
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER6
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER7
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER8
IOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER9
IOMUXC Memory Map/Register Definition
IOMUXC
IOMUXC_SW_MUX_CTL_PAD_JTAG_MOD
IOMUXC_SW_MUX_CTL_PAD_JTAG_TMS
IOMUXC_SW_MUX_CTL_PAD_JTAG_TDO
IOMUXC_SW_MUX_CTL_PAD_JTAG_TDI
IOMUXC_SW_MUX_CTL_PAD_JTAG_TCK
IOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09
IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B
IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B
IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B
IOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B
IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B
IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B
IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA
IOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA
IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0
IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1
IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN
IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0
IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1
IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN
IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK
IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER
IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0
IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1
IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN
IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0
IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1
IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN
IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK
IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER
IOMUXC_SW_MUX_CTL_PAD_LCD_CLK
IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE
IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC
IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC
IOMUXC_SW_MUX_CTL_PAD_LCD_RESET
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22
IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23
IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B
IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07
IOMUXC_SW_MUX_CTL_PAD_NAND_ALE
IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B
IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B
IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B
IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B
IOMUXC_SW_MUX_CTL_PAD_NAND_CLE
IOMUXC_SW_MUX_CTL_PAD_NAND_DQS
IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3
IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK
IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK
IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC
IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD
IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI
IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK
IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09
IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B
IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B
IOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B
IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B
IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B
IOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA
IOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA
IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0
IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1
IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN
IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0
IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1
IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN
IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK
IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER
IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0
IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1
IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN
IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0
IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1
IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN
IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK
IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER
IOMUXC_SW_PAD_CTL_PAD_LCD_CLK
IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE
IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC
IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC
IOMUXC_SW_PAD_CTL_PAD_LCD_RESET
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22
IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23
IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B
IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06
IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07
IOMUXC_SW_PAD_CTL_PAD_NAND_ALE
IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B
IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B
IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B
IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B
IOMUXC_SW_PAD_CTL_PAD_NAND_CLE
IOMUXC_SW_PAD_CTL_PAD_NAND_DQS
IOMUXC_SW_PAD_CTL_PAD_SD1_CMD
IOMUXC_SW_PAD_CTL_PAD_SD1_CLK
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2
IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3
IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK
IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK
IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC
IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07
IOMUXC_SW_PAD_CTL_GRP_ADDDS
IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
IOMUXC_SW_PAD_CTL_GRP_B0DS
IOMUXC_SW_PAD_CTL_GRP_DDRPK
IOMUXC_SW_PAD_CTL_GRP_CTLDS
IOMUXC_SW_PAD_CTL_GRP_B1DS
IOMUXC_SW_PAD_CTL_GRP_DDRHYS
IOMUXC_SW_PAD_CTL_GRP_DDRPKE
IOMUXC_SW_PAD_CTL_GRP_DDRMODE
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT
IOMUXC_USB_OTG2_ID_SELECT_INPUT
IOMUXC_CCM_PMIC_READY_SELECT_INPUT
IOMUXC_CSI_DATA02_SELECT_INPUT
IOMUXC_CSI_DATA03_SELECT_INPUT
IOMUXC_CSI_DATA05_SELECT_INPUT
IOMUXC_CSI_DATA00_SELECT_INPUT
IOMUXC_CSI_DATA01_SELECT_INPUT
IOMUXC_CSI_DATA04_SELECT_INPUT
IOMUXC_CSI_DATA06_SELECT_INPUT
IOMUXC_CSI_DATA07_SELECT_INPUT
IOMUXC_CSI_DATA08_SELECT_INPUT
IOMUXC_CSI_DATA09_SELECT_INPUT
IOMUXC_CSI_DATA10_SELECT_INPUT
IOMUXC_CSI_DATA11_SELECT_INPUT
IOMUXC_CSI_DATA12_SELECT_INPUT
IOMUXC_CSI_DATA13_SELECT_INPUT
IOMUXC_CSI_DATA14_SELECT_INPUT
IOMUXC_CSI_DATA15_SELECT_INPUT
IOMUXC_CSI_DATA16_SELECT_INPUT
IOMUXC_CSI_DATA17_SELECT_INPUT
IOMUXC_CSI_DATA18_SELECT_INPUT
IOMUXC_CSI_DATA19_SELECT_INPUT
IOMUXC_CSI_DATA20_SELECT_INPUT
IOMUXC_CSI_DATA21_SELECT_INPUT
IOMUXC_CSI_DATA22_SELECT_INPUT
IOMUXC_CSI_DATA23_SELECT_INPUT
IOMUXC_CSI_HSYNC_SELECT_INPUT
IOMUXC_CSI_PIXCLK_SELECT_INPUT
IOMUXC_CSI_VSYNC_SELECT_INPUT
IOMUXC_CSI_FIELD_SELECT_INPUT
IOMUXC_ECSPI1_SCLK_SELECT_INPUT
IOMUXC_ECSPI1_MISO_SELECT_INPUT
IOMUXC_ECSPI1_MOSI_SELECT_INPUT
IOMUXC_ECSPI1_SS0_B_SELECT_INPUT
IOMUXC_ECSPI2_SCLK_SELECT_INPUT
IOMUXC_ECSPI2_MISO_SELECT_INPUT
IOMUXC_ECSPI2_MOSI_SELECT_INPUT
IOMUXC_ECSPI2_SS0_B_SELECT_INPUT
IOMUXC_ECSPI3_SCLK_SELECT_INPUT
IOMUXC_ECSPI3_MISO_SELECT_INPUT
IOMUXC_ECSPI3_MOSI_SELECT_INPUT
IOMUXC_ECSPI3_SS0_B_SELECT_INPUT
IOMUXC_ECSPI4_SCLK_SELECT_INPUT
IOMUXC_ECSPI4_MISO_SELECT_INPUT
IOMUXC_ECSPI4_MOSI_SELECT_INPUT
IOMUXC_ECSPI4_SS0_B_SELECT_INPUT
IOMUXC_ENET1_REF_CLK1_SELECT_INPUT
IOMUXC_ENET1_MAC0_MDIO_SELECT_INPUT
IOMUXC_ENET2_REF_CLK2_SELECT_INPUT
IOMUXC_ENET2_MAC0_MDIO_SELECT_INPUT
IOMUXC_FLEXCAN1_RX_SELECT_INPUT
IOMUXC_FLEXCAN2_RX_SELECT_INPUT
IOMUXC_GPT1_CAPTURE1_SELECT_INPUT
IOMUXC_GPT1_CAPTURE2_SELECT_INPUT
IOMUXC_GPT1_CLK_SELECT_INPUT
IOMUXC_GPT2_CAPTURE1_SELECT_INPUT
IOMUXC_GPT2_CAPTURE2_SELECT_INPUT
IOMUXC_GPT2_CLK_SELECT_INPUT
IOMUXC_I2C1_SCL_SELECT_INPUT
IOMUXC_I2C1_SDA_SELECT_INPUT
IOMUXC_I2C2_SCL_SELECT_INPUT
IOMUXC_I2C2_SDA_SELECT_INPUT
IOMUXC_I2C3_SCL_SELECT_INPUT
IOMUXC_I2C3_SDA_SELECT_INPUT
IOMUXC_I2C4_SCL_SELECT_INPUT
IOMUXC_I2C4_SDA_SELECT_INPUT
IOMUXC_KPP_COL0_SELECT_INPUT
IOMUXC_KPP_COL1_SELECT_INPUT
IOMUXC_KPP_COL2_SELECT_INPUT
IOMUXC_KPP_ROW0_SELECT_INPUT
IOMUXC_KPP_ROW1_SELECT_INPUT
IOMUXC_KPP_ROW2_SELECT_INPUT
IOMUXC_LCD_BUSY_SELECT_INPUT
IOMUXC_SAI1_MCLK_SELECT_INPUT
IOMUXC_SAI1_RX_DATA_SELECT_INPUT
IOMUXC_SAI1_TX_BCLK_SELECT_INPUT
IOMUXC_SAI1_TX_SYNC_SELECT_INPUT
IOMUXC_SAI2_MCLK_SELECT_INPUT
IOMUXC_SAI2_RX_DATA_SELECT_INPUT
IOMUXC_SAI2_TX_BCLK_SELECT_INPUT
IOMUXC_SAI2_TX_SYNC_SELECT_INPUT
IOMUXC_SAI3_MCLK_SELECT_INPUT
IOMUXC_SAI3_RX_DATA_SELECT_INPUT
IOMUXC_SAI3_TX_BCLK_SELECT_INPUT
IOMUXC_SAI3_TX_SYNC_SELECT_INPUT
IOMUXC_SDMA_EVENTS0_SELECT_INPUT
IOMUXC_SDMA_EVENTS1_SELECT_INPUT
IOMUXC_SPDIF_IN_SELECT_INPUT
IOMUXC_SPDIF_EXT_CLK_SELECT_INPUT
IOMUXC_UART1_RTS_B_SELECT_INPUT
IOMUXC_UART1_RX_DATA_SELECT_INPUT
IOMUXC_UART2_RTS_B_SELECT_INPUT
IOMUXC_UART2_RX_DATA_SELECT_INPUT
IOMUXC_UART3_RTS_B_SELECT_INPUT
IOMUXC_UART3_RX_DATA_SELECT_INPUT
IOMUXC_UART4_RTS_B_SELECT_INPUT
IOMUXC_UART4_RX_DATA_SELECT_INPUT
IOMUXC_UART5_RTS_B_SELECT_INPUT
IOMUXC_UART5_RX_DATA_SELECT_INPUT
IOMUXC_UART6_RTS_B_SELECT_INPUT
IOMUXC_UART6_RX_DATA_SELECT_INPUT
IOMUXC_UART7_RTS_B_SELECT_INPUT
IOMUXC_UART7_RX_DATA_SELECT_INPUT
IOMUXC_UART8_RTS_B_SELECT_INPUT
IOMUXC_UART8_RX_DATA_SELECT_INPUT
IOMUXC_USB_OTG2_OC_SELECT_INPUT
IOMUXC_USB_OTG_OC_SELECT_INPUT
IOMUXC_USDHC1_CD_B_SELECT_INPUT
IOMUXC_USDHC1_WP_SELECT_INPUT
IOMUXC_USDHC2_CLK_SELECT_INPUT
IOMUXC_USDHC2_CD_B_SELECT_INPUT
IOMUXC_USDHC2_CMD_SELECT_INPUT
IOMUXC_USDHC2_DATA0_SELECT_INPUT
IOMUXC_USDHC2_DATA1_SELECT_INPUT
IOMUXC_USDHC2_DATA2_SELECT_INPUT
IOMUXC_USDHC2_DATA3_SELECT_INPUT
IOMUXC_USDHC2_DATA4_SELECT_INPUT
IOMUXC_USDHC2_DATA5_SELECT_INPUT
IOMUXC_USDHC2_DATA6_SELECT_INPUT
IOMUXC_USDHC2_DATA7_SELECT_INPUT
IOMUXC_USDHC2_WP_SELECT_INPUT
Chapter 33: Keypad Port (KPP)
Overview
Features
Modes and Operations
Clocks
External Signals
Input Pins
Output Pins
Generation of Transfer Error Signal on Peripheral Bus
Functional Description
Keypad Matrix Construction
Keypad Port Configuration
Keypad Matrix Scanning
Keypad Standby
Glitch Suppression on Keypad Inputs
Multiple Key Closures
Ghost Key Problem and Correction
3-Point Contact Keys Support
Initialization/Application Information
Typical Keypad Configuration and Scanning Sequence
Key Press Interrupt Scanning Sequence
Additional Comments
KPP Memory Map/Register Definition
KPP
KPP_KPCR
KPP_KPSR
KPP_KDDR
KPP_KPDR
Chapter 34: Enhanced LCD Interface (eLCDIF)
Overview
External Signals
Clocks
Functional Description
Bus Interface Mechanisms
Bus Master Operation in Write/Display Modes
System Bus Master Performance
Write Data Path
Read Data Path
eLCDIF Interrupts
Initializing the eLCDIF
Write Modes
MPU Read Mode
MPU Interface
Code Example to Initialize the eLCDIF in MPU Write Mode
VSYNC Interface
Code Example to Initialize eLCDIF in VSYNC Mode
DOTCLK Interface
Code Example
CSI HANDSHAKE INTERFACE
Alpha Blending Interface
ITU-R BT.656 Digital Video Interface (DVI)
eLCDIF Pin Usage by Interface Mode
Behavior During Reset
eLCDIF Memory Map/Register Definition
LCDIF
LCDIF_CTRLn
LCDIF_CTRL1n
LCDIF_CTRL2n
LCDIF_TRANSFER_COUNT
LCDIF_CUR_BUF
LCDIF_NEXT_BUF
LCDIF_TIMING
LCDIF_VDCTRL0n
LCDIF_VDCTRL1
LCDIF_VDCTRL2
LCDIF_VDCTRL3
LCDIF_VDCTRL4
LCDIF_DVICTRL0
LCDIF_DVICTRL1
LCDIF_DVICTRL2
LCDIF_DVICTRL3
LCDIF_DVICTRL4
LCDIF_CSC_COEFF0
LCDIF_CSC_COEFF1
LCDIF_CSC_COEFF2
LCDIF_CSC_COEFF3
LCDIF_CSC_COEFF4
LCDIF_CSC_OFFSET
LCDIF_CSC_LIMIT
LCDIF_DATA
LCDIF_BM_ERROR_STAT
LCDIF_CRC_STAT
LCDIF_STAT
LCDIF_THRES
LCDIF_AS_CTRL
LCDIF_AS_BUF
LCDIF_AS_NEXT_BUF
LCDIF_AS_CLRKEYLOW
LCDIF_AS_CLRKEYHIGH
LCDIF_SYNC_DELAY
Chapter 35: Multi Mode DDR Controller (MMDC)
Overview
MMDC feature summary
External Signals
Clocks
Functional Description
Write/Read data flow
Write data flow
Read data flow
MMDC initialization
Configuring the MMDC registers
MMDC Address Space
Address decoding
Chip select settings
Creating 4 Gbyte address space with 2 Gbyte CS density
Creating 2 Gbyte address spaces with 1 Gbyte CS density
Translation of AXI accesses to DDR accessess
Example 1
Example 2
Example 3
Example 4
Example 5
Address mirroring
LPDDR2 and DDR3 pin mux mapping
Power Saving and Clock Frequency Change modes
Power saving general
Self refresh and Frequency change entry/exit
Reset
Hard reset
Warm reset
Software reset
Refresh Scheme
Burst Length options towards DDR
Exclusive accesses handling
AXI Error Handling
Performance
Arbitration and reordering mechanism
Arbitration General
Real time channel mode
Dynamic scoring mode (Arbitration Winning Conditions)
Guarding (aging) mechanism
Prediction mechanism
Special Optimization for accesses towards DDR3
MMDC Debug
Hardware debug monitor
Step By Step (SBS) software monitor
MMDC Profiling
LPDDR2 Refresh Rate Update and Timing Derating
DLL Switching
DLL Off mode
ODT Configuration
Calibration Process
Delay-line
ZQ calibration
ZQ automatic (hardware) calibration process
ZQ automatic Pull-up calibration
ZQ automatic Pull-down calibration
ZQ software calibration process
ZQ calibration commands
Read DQS Gating Calibration
Hardware DQS Gating Calibration
Hardware DQS Calibration with MPR
Hardware DQS Calibration with pre-defined value
SW read DQS gating Calibration
SW read Calibration with MPR
SW read Calibration with pre-defined value
Read Calibration
Hardware (automatic) Read Calibration
Hardware (automatic) Calibration with MPR/DQ Calibration
Hardware (automatic) Calibration with pre-defined value
SW Read Calibration
Calibration with MPR/DQ calibration
Calibration with pre-defined value
Write Calibration
HW (automatic) Write Calibration
SW Write Calibration
Write leveling Calibration
Hardware Write Leveling Calibration
SW Write Leveling Calibration
Write fine tuning
Read fine tuning
ZQ Fine Tuning
Duty cycle adjustment
MMDC Memory Map/Register Definition
MMDC
MMDC_MDCTL
MMDC_MDPDC
MMDC_MDOTC
MMDC_MDCFG0
MMDC_MDCFG1
MMDC_MDCFG2
MMDC_MDMISC
MMDC_MDSCR
MMDC_MDREF
MMDC_MDRWD
MMDC_MDOR
MMDC_MDMRR
MMDC_MDCFG3LP
MMDC_MDMR4
MMDC_MDASP
MMDC_MAARCR
MMDC_MAPSR
MMDC_MAEXIDR0
MMDC_MAEXIDR1
MMDC_MADPCR0
MMDC_MADPCR1
MMDC_MADPSR0
MMDC_MADPSR1
MMDC_MADPSR2
MMDC_MADPSR3
MMDC_MADPSR4
MMDC_MADPSR5
MMDC_MASBS0
MMDC_MASBS1
MMDC_MAGENP
MMDC_MPZQHWCTRL
MMDC_MPZQSWCTRL
MMDC_MPWLGCR
MMDC_MPWLDECTRL0
MMDC_MPWLDECTRL1
MMDC_MPWLDLST
MMDC_MPODTCTRL
MMDC_MPRDDQBY0DL
MMDC_MPRDDQBY1DL
MMDC_MPWRDQBY0DL
MMDC_MPWRDQBY1DL
MMDC_MPWRDQBY2DL
MMDC_MPWRDQBY3DL
MMDC_MPDGCTRL0
MMDC_MPDGCTRL1
MMDC_MPDGDLST0
MMDC_MPRDDLCTL
MMDC_MPRDDLST
MMDC_MPWRDLCTL
MMDC_MPWRDLST
MMDC_MPSDCTRL
MMDC_MPZQLP2CTL
MMDC_MPRDDLHWCTL
MMDC_MPWRDLHWCTL
MMDC_MPRDDLHWST0
MMDC_MPWRDLHWST0
MMDC_MPWLHWERR
MMDC_MPDGHWST0
MMDC_MPDGHWST1
MMDC_MPDGHWST2
MMDC_MPDGHWST3
MMDC_MPPDCMPR1
MMDC_MPPDCMPR2
MMDC_MPSWDAR0
MMDC_MPSWDRDR0
MMDC_MPSWDRDR1
MMDC_MPSWDRDR2
MMDC_MPSWDRDR3
MMDC_MPSWDRDR4
MMDC_MPSWDRDR5
MMDC_MPSWDRDR6
MMDC_MPSWDRDR7
MMDC_MPMUR0
MMDC_MPWRCADL
MMDC_MPDCCR
Chapter 36: Medium Quality Sound (MQS)
Overview
Block Diagram
External Signals
Interface Signals
Programming Considerations
Usage Model
Chapter 37: On-Chip OTP Controller (OCOTP_CTRL)
Overview
Features
Clocks
Top-Level Symbol and Functional Overview
Operation
Shadow Register Reload
Fuse and Shadow Register Read
Fuse and Shadow Register Writes
Write Postamble
Fuse Shadow Memory Footprint
OTP Read/Write Timing Parameters
Hardware Visible Fuses
Behavior During Reset
Secure JTAG control
Fuse Map
OCOTP Memory Map/Register Definition
OCOTP
OCOTP_CTRLn
OCOTP_TIMING
OCOTP_DATA
OCOTP_READ_CTRL
OCOTP_READ_FUSE_DATA
OCOTP_SW_STICKY
OCOTP_SCSn
OCOTP_CRC_ADDR
OCOTP_CRC_VALUE
OCOTP_VERSION
OCOTP_TIMING2
OCOTP_LOCK
OCOTP_CFG0
OCOTP_CFG1
OCOTP_CFG2
OCOTP_CFG3
OCOTP_CFG4
OCOTP_CFG5
OCOTP_CFG6
OCOTP_MEM0
OCOTP_MEM1
OCOTP_MEM2
OCOTP_MEM3
OCOTP_MEM4
OCOTP_ANA0
OCOTP_ANA1
OCOTP_ANA2
OCOTP_OTPMK0
OCOTP_OTPMK1
OCOTP_OTPMK2
OCOTP_OTPMK3
OCOTP_OTPMK4
OCOTP_OTPMK5
OCOTP_OTPMK6
OCOTP_OTPMK7
OCOTP_SRK0
OCOTP_SRK1
OCOTP_SRK2
OCOTP_SRK3
OCOTP_SRK4
OCOTP_SRK5
OCOTP_SRK6
OCOTP_SRK7
OCOTP_SJC_RESP0
OCOTP_SJC_RESP1
OCOTP_MAC0
OCOTP_MAC1
OCOTP_MAC
OCOTP_CRC
OCOTP_GP1
OCOTP_GP2
OCOTP_SW_GP0
OCOTP_SW_GP1
OCOTP_SW_GP2
OCOTP_SW_GP3
OCOTP_SW_GP4
OCOTP_MISC_CONF
OCOTP_FIELD_RETURN
OCOTP_SRK_REVOKE
OCOTP_ROM_PATCH0
OCOTP_ROM_PATCH1
OCOTP_ROM_PATCH2
OCOTP_ROM_PATCH3
OCOTP_ROM_PATCH4
OCOTP_ROM_PATCH5
OCOTP_ROM_PATCH6
OCOTP_ROM_PATCH7
OCOTP_GP3_0
OCOTP_GP3_1
OCOTP_GP3_2
OCOTP_GP3_3
OCOTP_GP4_0
OCOTP_GP4_1
OCOTP_GP4_2
OCOTP_GP4_3
Chapter 38: On-Chip RAM Memory Controller (OCRAM)
Overview
Basic Functions
Read/Write Arbitration
Advanced Features
Read Data Wait State
Read Address Pipeline
Write Data Pipeline
Write Address Pipeline
Programmable Registers
Chapter 39: Power Management Unit (PMU)
Overview
Digital LDO Regulators
Analog LDO Regulators
LDO 1P1
LDO 2P5
Low Power Operation
USB LDO Regulator
SNVS Regulator
PMU Memory Map/Register Definition
PMU
PMU_REG_1P1n
PMU_REG_3P0n
PMU_REG_2P5n
PMU_REG_COREn
PMU_MISC0n
PMU_MISC1n
PMU_MISC2n
PMU_LOWPWR_CTRLn
Chapter 40: Pulse Width Modulation (PWM)
Overview
External Signals
Clocks
Functional Description
Operation
FIFO
Rollover and Compare Event
Low Power Mode Behavior
Debug Mode Behavior
Enable Sequence for the PWM
Disable Sequence for the PWM
PWM Memory Map/Register Definition
PWMx
PWMx_PWMCR
PWMx_PWMSR
PWMx_PWMIR
PWMx_PWMSAR
PWMx_PWMPR
PWMx_PWMCNR
Chapter 41: Pixel Pipeline (PXP)
Overview
Clocks
Top-level architecture
Processing Details
Scaling Operation
Decimation Image Scaling
Bilinear Image Scaling Filter
YUV 4:2:2 Image Scaling
YUV 4:2:0 Image Scaling
RGB/YUV444 Image Scaling
Color Space Conversion (CSC)
CSC1 Operation
YUV versus YCbCr Support
CSC2 operation
Alpha Blending/Color Key
Alpha Blend
Normal Alpha Blend
Porter-Duff Alpha Blend
Color Key
LUT
Lookup Modes
DIRECT_Y8
DIRECT_RGB444
DIRECT_RGB454
CACHE_RGB565
Output Modes
Y8
RGBW4444CFA
CFA Correction
RGB888
Rotation
Output Buffer
Address calculator
Block size selection
Interlaced Video Support
LCDIF Handshake
LCDIF Abort
Theory of Operation
Pixel Handling
Output Buffer Composition
PS Image Processing
Letterboxing
Clipping source images
Color Key Processing
In Place Processing (PS buffer is destination buffer)
Alpha Surface (AS) Processing
Alpha Handling
Color Key Processing (AS_CTRL)
Output Image Processing
Output Image Size
Output Format
Rotation/Flip operations
Queuing PXP transactions
Error Handling
Known PXP Limitations/Issues
Dither Engine Block
Top Level Connections
Dither Engine Design
Pipelined Data Flow
Initialization of Dedicated Memories
Register Configuration Interface
Waveform Engines
Overview
Functionality
PXP Store Engine Block Description
Overview
Top-Level Architecture
Store Engine Design
Input Data Source
Store data shift operation
Data Packing
Data Store Format
Output Format Modes
Limitations
Histogram
Basic Operation
Mask Functionality
Collision use-case Example
PXP Memory Map/Register Definition
PXP
PXP_HW_PXP_CTRLn
PXP_HW_PXP_STATn
PXP_HW_PXP_OUT_CTRLn
PXP_HW_PXP_OUT_BUF
PXP_HW_PXP_OUT_BUF2
PXP_HW_PXP_OUT_PITCH
PXP_HW_PXP_OUT_LRC
PXP_HW_PXP_OUT_PS_ULC
PXP_HW_PXP_OUT_PS_LRC
PXP_HW_PXP_OUT_AS_ULC
PXP_HW_PXP_OUT_AS_LRC
PXP_HW_PXP_PS_CTRLn
PXP_HW_PXP_PS_BUF
PXP_HW_PXP_PS_UBUF
PXP_HW_PXP_PS_VBUF
PXP_HW_PXP_PS_PITCH
PXP_HW_PXP_PS_BACKGROUND_0
PXP_HW_PXP_PS_SCALE
PXP_HW_PXP_PS_OFFSET
PXP_HW_PXP_PS_CLRKEYLOW_0
PXP_HW_PXP_PS_CLRKEYHIGH_0
PXP_HW_PXP_AS_CTRL
PXP_HW_PXP_AS_BUF
PXP_HW_PXP_AS_PITCH
PXP_HW_PXP_AS_CLRKEYLOW_0
PXP_HW_PXP_AS_CLRKEYHIGH_0
PXP_HW_PXP_CSC1_COEF0
PXP_HW_PXP_CSC1_COEF1
PXP_HW_PXP_CSC1_COEF2
PXP_HW_PXP_CSC2_CTRL
PXP_HW_PXP_CSC2_COEF0
PXP_HW_PXP_CSC2_COEF1
PXP_HW_PXP_CSC2_COEF2
PXP_HW_PXP_CSC2_COEF3
PXP_HW_PXP_CSC2_COEF4
PXP_HW_PXP_CSC2_COEF5
PXP_HW_PXP_LUT_CTRL
PXP_HW_PXP_LUT_ADDR
PXP_HW_PXP_LUT_DATA
PXP_HW_PXP_LUT_EXTMEM
PXP_HW_PXP_CFA
PXP_HW_PXP_ALPHA_A_CTRL
PXP_HW_PXP_PS_BACKGROUND_1
PXP_HW_PXP_PS_CLRKEYLOW_1
PXP_HW_PXP_PS_CLRKEYHIGH_1
PXP_HW_PXP_AS_CLRKEYLOW_1
PXP_HW_PXP_AS_CLRKEYHIGH_1
PXP_HW_PXP_CTRL2n
PXP_HW_PXP_POWER_REG0
PXP_HW_PXP_POWER_REG1
PXP_HW_PXP_DATA_PATH_CTRL0n
PXP_HW_PXP_DATA_PATH_CTRL1n
PXP_HW_PXP_INIT_MEM_CTRLn
PXP_HW_PXP_INIT_MEM_DATA
PXP_HW_PXP_INIT_MEM_DATA_HIGH
PXP_HW_PXP_IRQ_MASKn
PXP_HW_PXP_IRQn
PXP_HW_PXP_NEXT_ENn
PXP_HW_PXP_NEXT
PXP_HW_PXP_DEBUGCTRL
PXP_HW_PXP_DEBUG
PXP_HW_PXP_VERSION
PXP_HW_PXP_DITHER_STORE_SIZE_CH0
PXP_HW_PXP_WFB_FETCH_CTRLn
PXP_HW_PXP_WFB_FETCH_BUF1_ADDR
PXP_HW_PXP_WFB_FETCH_BUF1_PITCH
PXP_HW_PXP_WFB_FETCH_BUF1_SIZE
PXP_HW_PXP_WFB_FETCH_BUF2_ADDR
PXP_HW_PXP_WFB_FETCH_BUF2_PITCH
PXP_HW_PXP_WFB_FETCH_BUF2_SIZE
PXP_HW_PXP_WFB_ARRAY_PIXEL0_MASK
PXP_HW_PXP_WFB_ARRAY_PIXEL1_MASK
PXP_HW_PXP_WFB_ARRAY_PIXEL2_MASK
PXP_HW_PXP_WFB_ARRAY_PIXEL3_MASK
PXP_HW_PXP_WFB_ARRAY_PIXEL4_MASK
PXP_HW_PXP_WFB_ARRAY_PIXEL5_MASK
PXP_HW_PXP_WFB_ARRAY_PIXEL6_MASK
PXP_HW_PXP_WFB_ARRAY_PIXEL7_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG0_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG1_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG2_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG3_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG4_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG5_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG6_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG7_MASK
PXP_HW_PXP_WFB_FETCH_BUF1_CORD
PXP_HW_PXP_WFB_FETCH_BUF2_CORD
PXP_HW_PXP_WFB_ARRAY_FLAG8_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG9_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG10_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG11_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG12_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG13_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG14_MASK
PXP_HW_PXP_WFB_ARRAY_FLAG15_MASK
PXP_HW_PXP_WFB_ARRAY_REG0
PXP_HW_PXP_WFB_ARRAY_REG1
PXP_HW_PXP_WFB_ARRAY_REG2
PXP_HW_PXP_WFE_B_STORE_CTRL_CH0n
PXP_HW_PXP_WFE_B_STORE_CTRL_CH1n
PXP_HW_PXP_WFE_B_STORE_STATUS_CH0
PXP_HW_PXP_WFE_B_STORE_STATUS_CH1
PXP_HW_PXP_WFE_B_STORE_SIZE_CH0
PXP_HW_PXP_WFE_B_STORE_SIZE_CH1
PXP_HW_PXP_WFE_B_STORE_PITCH
PXP_HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0n
PXP_HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1n
PXP_HW_PXP_WFE_B_STORE_ADDR_0_CH0
PXP_HW_PXP_WFE_B_STORE_ADDR_1_CH0
PXP_HW_PXP_WFE_B_STORE_FILL_DATA_CH0
PXP_HW_PXP_WFE_B_STORE_ADDR_0_CH1
PXP_HW_PXP_WFE_B_STORE_ADDR_1_CH1
PXP_HW_PXP_WFE_B_STORE_D_MASK0_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK0_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK1_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK1_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK2_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK2_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK3_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK3_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK4_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK4_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK5_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK5_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK6_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK6_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK7_H_CH0
PXP_HW_PXP_WFE_B_STORE_D_MASK7_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0
PXP_HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0
PXP_HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0
PXP_HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0
PXP_HW_PXP_WFE_B_STORE_F_MASK_L_CH0
PXP_HW_PXP_WFE_B_STORE_F_MASK_H_CH0
PXP_HW_PXP_FETCH_WFE_B_DEBUG
PXP_HW_PXP_DITHER_CTRLn
PXP_HW_PXP_DITHER_FINAL_LUT_DATA0n
PXP_HW_PXP_DITHER_FINAL_LUT_DATA1n
PXP_HW_PXP_DITHER_FINAL_LUT_DATA2n
PXP_HW_PXP_DITHER_FINAL_LUT_DATA3n
PXP_HW_PXP_WFE_B_CTRLn
PXP_HW_PXP_WFE_B_DIMENSIONS
PXP_HW_PXP_WFE_B_OFFSET
PXP_HW_PXP_WFE_B_SW_DATA_REGS
PXP_HW_PXP_WFE_B_SW_FLAG_REGS
PXP_HW_PXP_WFE_B_STAGE1_MUX0n
PXP_HW_PXP_WFE_B_STAGE1_MUX1n
PXP_HW_PXP_WFE_B_STAGE1_MUX2n
PXP_HW_PXP_WFE_B_STAGE1_MUX3n
PXP_HW_PXP_WFE_B_STAGE1_MUX4n
PXP_HW_PXP_WFE_B_STAGE1_MUX5n
PXP_HW_PXP_WFE_B_STAGE1_MUX6n
PXP_HW_PXP_WFE_B_STAGE1_MUX7n
PXP_HW_PXP_WFE_B_STAGE1_MUX8n
PXP_HW_PXP_WFE_B_STAGE2_MUX0n
PXP_HW_PXP_WFE_B_STAGE2_MUX1n
PXP_HW_PXP_WFE_B_STAGE2_MUX2n
PXP_HW_PXP_WFE_B_STAGE2_MUX3n
PXP_HW_PXP_WFE_B_STAGE2_MUX4n
PXP_HW_PXP_WFE_B_STAGE2_MUX5n
PXP_HW_PXP_WFE_B_STAGE2_MUX6n
PXP_HW_PXP_WFE_B_STAGE2_MUX7n
PXP_HW_PXP_WFE_B_STAGE2_MUX8n
PXP_HW_PXP_WFE_B_STAGE2_MUX9n
PXP_HW_PXP_WFE_B_STAGE2_MUX10n
PXP_HW_PXP_WFE_B_STAGE2_MUX11n
PXP_HW_PXP_WFE_B_STAGE2_MUX12n
PXP_HW_PXP_WFE_B_STAGE3_MUX0n
PXP_HW_PXP_WFE_B_STAGE3_MUX1n
PXP_HW_PXP_WFE_B_STAGE3_MUX2n
PXP_HW_PXP_WFE_B_STAGE3_MUX3n
PXP_HW_PXP_WFE_B_STAGE3_MUX4n
PXP_HW_PXP_WFE_B_STAGE3_MUX5n
PXP_HW_PXP_WFE_B_STAGE3_MUX6n
PXP_HW_PXP_WFE_B_STAGE3_MUX7n
PXP_HW_PXP_WFE_B_STAGE3_MUX8n
PXP_HW_PXP_WFE_B_STAGE3_MUX9n
PXP_HW_PXP_WFE_B_STAGE3_MUX10n
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_0
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_1
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_2
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_3
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_4
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_5
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_6
PXP_HW_PXP_WFE_B_STG1_5X8_OUT0_7
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_0
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_1
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_2
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_3
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_4
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_5
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_6
PXP_HW_PXP_WFE_B_STG1_5X8_OUT1_7
PXP_HW_PXP_WFE_B_STAGE1_5X8_MASKS_0
PXP_HW_PXP_WFE_B_STG1_5X1_OUT0
PXP_HW_PXP_WFE_B_STG1_5X1_MASKS
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_0
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_1
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_2
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_3
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_4
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_5
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_6
PXP_HW_PXP_WFE_B_STG1_8X1_OUT0_7
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_0
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_1
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_2
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_3
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_4
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_5
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_6
PXP_HW_PXP_WFE_B_STG1_8X1_OUT1_7
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_0
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_1
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_2
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_3
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_4
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_5
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_6
PXP_HW_PXP_WFE_B_STG1_8X1_OUT2_7
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_0
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_1
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_2
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_3
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_4
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_5
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_6
PXP_HW_PXP_WFE_B_STG1_8X1_OUT3_7
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_0
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_1
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_2
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_3
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_4
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_5
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_6
PXP_HW_PXP_WFE_B_STG1_8X1_OUT4_7
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_0
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_1
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_2
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_3
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_4
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_5
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_6
PXP_HW_PXP_WFE_B_STG2_5X6_OUT0_7
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_0
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_1
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_2
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_3
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_4
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_5
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_6
PXP_HW_PXP_WFE_B_STG2_5X6_OUT1_7
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_0
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_1
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_2
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_3
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_4
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_5
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_6
PXP_HW_PXP_WFE_B_STG2_5X6_OUT2_7
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_0
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_1
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_2
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_3
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_4
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_5
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_6
PXP_HW_PXP_WFE_B_STG2_5X6_OUT3_7
PXP_HW_PXP_WFE_B_STAGE2_5X6_MASKS_0
PXP_HW_PXP_WFE_B_STAGE2_5X6_ADDR_0
PXP_HW_PXP_WFE_B_STG2_5X1_OUT0
PXP_HW_PXP_WFE_B_STG2_5X1_OUT1
PXP_HW_PXP_WFE_B_STG2_5X1_OUT2
PXP_HW_PXP_WFE_B_STG2_5X1_OUT3
PXP_HW_PXP_WFE_B_STG2_5X1_MASKS
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_0
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_1
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_2
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_3
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_4
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_5
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_6
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT0_7
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_0
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_1
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_2
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_3
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_4
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_5
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_6
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT1_7
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_0
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_1
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_2
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_3
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_4
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_5
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_6
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT2_7
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_0
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_1
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_2
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_3
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_4
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_5
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_6
PXP_HW_PXP_WFE_B_STG3_F8X1_OUT3_7
PXP_HW_PXP_WFE_B_STG3_F8X1_MASKS
PXP_HW_PXP_ALU_B_CTRLn
PXP_HW_PXP_ALU_B_BUF_SIZE
PXP_HW_PXP_ALU_B_INST_ENTRY
PXP_HW_PXP_ALU_B_PARAM
PXP_HW_PXP_ALU_B_CONFIG
PXP_HW_PXP_ALU_B_LUT_CONFIGn
PXP_HW_PXP_ALU_B_LUT_DATA0
PXP_HW_PXP_ALU_B_LUT_DATA1
PXP_HW_PXP_ALU_B_DBG
PXP_HW_PXP_HIST_A_CTRL
PXP_HW_PXP_HIST_A_MASK
PXP_HW_PXP_HIST_A_BUF_SIZE
PXP_HW_PXP_HIST_A_TOTAL_PIXEL
PXP_HW_PXP_HIST_A_ACTIVE_AREA_X
PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y
PXP_HW_PXP_HIST_A_RAW_STAT0
PXP_HW_PXP_HIST_A_RAW_STAT1
PXP_HW_PXP_HIST_B_CTRL
PXP_HW_PXP_HIST_B_MASK
PXP_HW_PXP_HIST_B_BUF_SIZE
PXP_HW_PXP_HIST_B_TOTAL_PIXEL
PXP_HW_PXP_HIST_B_ACTIVE_AREA_X
PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y
PXP_HW_PXP_HIST_B_RAW_STAT0
PXP_HW_PXP_HIST_B_RAW_STAT1
PXP_HW_PXP_HIST2_PARAM
PXP_HW_PXP_HIST4_PARAM
PXP_HW_PXP_HIST8_PARAM0
PXP_HW_PXP_HIST8_PARAM1
PXP_HW_PXP_HIST16_PARAM0
PXP_HW_PXP_HIST16_PARAM1
PXP_HW_PXP_HIST16_PARAM2
PXP_HW_PXP_HIST16_PARAM3
PXP_HW_PXP_HIST32_PARAM0
PXP_HW_PXP_HIST32_PARAM1
PXP_HW_PXP_HIST32_PARAM2
PXP_HW_PXP_HIST32_PARAM3
PXP_HW_PXP_HIST32_PARAM4
PXP_HW_PXP_HIST32_PARAM5
PXP_HW_PXP_HIST32_PARAM6
PXP_HW_PXP_HIST32_PARAM7
PXP_HW_PXP_HANDSHAKE_READY_MUX0
PXP_HW_PXP_HANDSHAKE_DONE_MUX0
Chapter 42: Quad Serial Peripheral Interface (QuadSPI)
Overview
Features
QuadSPI Modes of Operation
Normal Mode
Module Disable Mode
Acronyms and Abbreviations
Glossary for QuadSPI module
External Signals
Driving External Signals
Memory Map and Register Definition
Register Write Access
Serial Flash Address Assignment
AMBA Bus Register Memory Map
AHB Bus Register Memory Map Descriptions
AHB Bus Access Considerations
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B
Parallel Flash Mode
Interrupt Signals
Functional Description
Serial Flash Access Schemes
Modes of Operation
Normal Mode
Programmable Sequence Engine
Flexible AHB buffers
Suspend-Abort Mechanism
Look-up Table
Issuing SFM Commands
Flash Programming
Flash Read
Byte Ordering of Serial Flash Read Data
Normal Mode Interrupt and DMA Requests
TX Buffer Operation
Address scheme
Initialization/Application Information
Power Up and Reset
Available Status/Flag Information
IP Commands
AHB Commands
Overview of Error Flags
IP Bus and AHB Access Command Collisions
Exclusive Access to Serial Flash for AHB Commands
RX Buffer Read via QSPI_ARDB Registers
RX Buffer Read via QSPI_RBDR Registers
Command Arbitration
Flash Device Selection
DMA Usage
DMA Usage in Normal Mode
Bandwidth considerations
Parallel mode
Byte Ordering - Endianness
Programming Flash Data
Reading Flash Data into the RX Buffer
Readout of the RX Buffer via QSPI_RBDRn
Readout of the RX Buffer via ARDBn
Reading Flash Data into the AHB Buffer
Readout of the AHB Buffer via Memory Mapped Read
Serial Flash Devices
Example Sequences
Fast Read Sequence (Macronix/Numonyx/Spansion/Winbond)
Fast Dual I/O DT Read Sequence (Macronix)
Fast Read Quad Output (Winbond)
4 x I/O Read Enhance Performance Mode (XIP) (Macronix)
Dual Command Page Program (Numonyx)
Sector Erase (Macronix/Spansion/Numonyx)
Read Status Register (Macronix/Spansion/Numonyx/Winbond)
Dual Die Flashes
Boot initialization sequence
Sampling of Serial Flash Input Data
Internal Sampling of Serial Flash Input Data
DDR Mode
Serial Flash Data Input Timing
Input timing in SDR mode with internal sampling
Input timing in DDR mode with internal sampling
Input timing in SDR mode with loopback DQS sampling
Input timing in DDR mode with loopback DQS sampling
Input timing in SDR mode with flash DQS sampling
Input timing in DDR mode with flash DQS sampling
Data Strobe Signal functionality
Output timing in SDR mode
Output timing in DDR mode
AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31)
AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31)
ARDBn
Peripheral Bus Register Descriptions
QuadSPI
QuadSPI_MCR
QuadSPI_IPCR
QuadSPI_FLSHCR
QuadSPI_BUF0CR
QuadSPI_BUF1CR
QuadSPI_BUF2CR
QuadSPI_BUF3CR
QuadSPI_BFGENCR
QuadSPI_BUF0IND
QuadSPI_BUF1IND
QuadSPI_BUF2IND
QuadSPI_SFAR
QuadSPI_SMPR
QuadSPI_RBSR
QuadSPI_RBCT
QuadSPI_TBSR
QuadSPI_TBDR
QuadSPI_SR
QuadSPI_FR
QuadSPI_RSER
QuadSPI_SPNDST
QuadSPI_SPTRCLR
QuadSPI_SFA1AD
QuadSPI_SFA2AD
QuadSPI_SFB1AD
QuadSPI_SFB2AD
QuadSPI_RBDRn
QuadSPI_LUTKEY
QuadSPI_LCKCR
QuadSPI_LUT0
QuadSPI_LUT1
QuadSPI_LUTn
Chapter 43: ROM Controller with Patch (ROMC)
Overview
Features
Modes of Operation
Low Power Mode
Clocks
Memory Map
ROM Memory Map in detail
Functional Description
ROM Controller (ROMC) Functional Description
Functionality overview
ROMC Functional Description
ROMC Disabling
ROMC Event Priority
Data Fixing
Opcode Patching
Typical Software Response to Opcode Patch
External Boot Feature
Alternate Masters and ROMC
ROMCP Memory Map/Register Definition
ROMC
ROMC_ROMPATCHnD
ROMC_ROMPATCHCNTL
ROMC_ROMPATCHENH
ROMC_ROMPATCHENL
ROMC_ROMPATCHnA
ROMC_ROMPATCHSR
Chapter 44: Random Number Generator (RNGB)
Introduction
Block diagram
Features
Modes of operation
Self-test mode
Seed-generation mode
Random number generation mode
Memory map/register definition
RNG
RNG_VER
RNG_CMD
RNG_CR
RNG_SR
RNG_ESR
RNG_OUT
Functional description
Pseudo-Random Number Generator (PRNG)
True Random Number Generator (TRNG)
Resets
Power-on/hardware reset
Software reset
RNG interrupts
Initialization/application information
Manual seeding
Automatic seeding
Chapter 45: Synchronous Audio Interface (SAI)
Overview
Features
Block diagram
Modes of operation
External Signals
Functional description
SAI clocking
SAI resets
Synchronous modes
Frame sync configuration
Data FIFO
Data alignment
FIFO pointers
Word mask register
Interrupts and DMA requests
FIFO request flag
FIFO warning flag
FIFO error flag
Sync error flag
Word start flag
Memory map and register definition
I2Sx
I2Sx_TCSR
I2Sx_TCR1
I2Sx_TCR2
I2Sx_TCR3
I2Sx_TCR4
I2Sx_TCR5
I2Sx_TDRn
I2Sx_TFRn
I2Sx_TMR
I2Sx_RCSR
I2Sx_RCR1
I2Sx_RCR2
I2Sx_RCR3
I2Sx_RCR4
I2Sx_RCR5
I2Sx_RDRn
I2Sx_RFRn
I2Sx_RMR
I2Sx_MCR
Chapter 46: Smart Direct Memory Access Controller (SDMA)
Overview
Block Diagram
Features
External Signals
Clocks
Functional Description
SDMA Core
SDMA Core Structure
Program Control Unit (PCU)
Instruction Types
PCU States
SDMA Core Memory
Scheduler
Primary Functions
Channels and DMA Requests
Channels
DMA Requests
Mapping from DMA Requests to Channels and Priorities
Scheduler Functional Description
Scheduler Overview
DMA Requests Scanning
Mapping DMA Requests to Pending Channels
Channel Overflow
Runnable Channels Evaluation
Next Channel Decision Tree
Scheduler State Diagram
Scheduler Pipeline Timing Diagram
Channel-DMA Request Mapping
Examples: How to Start a Channel
Context Switching
Context Switch Modes
Context Switch Procedure
Context Map in Memory
Functional Units
Burst DMA Unit
Burst DMA Structure
Burst DMA Registers
Burst DMA Data Transfers
Data Retrieval from the Arm platform Memory
Storing Data Into the Arm platform Memory
Transferring Data Between Two Arm platform Memory Locations-Burst DMA Unit
Peripheral DMA Unit
Peripheral DMA Structure
Peripheral DMA Registers
Peripheral DMA Data Transfers
Data Retrieval from the Arm platform Memory or Peripheral
Storing Data into the Arm platform Memory or Peripheral
Transferring Data Between Two Arm platform Memory Locations-Peripheral DMA Unit
SDMA Security Support
Locked Mode
OnCE and PCU Debug States
SDMA Clocks and Low Power Modes
Clock Gating and Low Power Modes
Coarse Clock Gating
Refined Clock Gating
Low Power Modes and User Control
SLEEP Mode
RUN Mode
DEBUG Mode
Stop Mode Response
Reset
Software Interface
Initialization Information
Hardware Reset
Channel Script Execution
Initialization and Script Execution Setup Sequence
SDMA Programming Model
State and Registers Per Channel
General Purpose Registers
Functional Unit State
Program Counter Register (PC)
Flags
Return Program Counter (RPC)
Loop Mode Start Program Counter (SPC)
Loop Mode End Program Counter (EPC)
Context Switching-Programming
Address Space
Instruction Memory Map
Data Memory Map
SDMA Initialization
Hardware Reset-SDMA
Standard Boot Sequence
User-Defined Boot Sequence
Script Loading and Context Initialization
Instruction Description
Scheduling Instructions
Conditional Branch Instructions
Unconditional Jump Instructions
Subroutine Return Instructions
Loop Instruction
Miscellaneous Instructions
Logic Instructions
Arithmetic Instructions
Compare Instructions
Test Instructions
Byte Permutation Instructions
Bit Shift Instructions
Bit Manipulation Instructions
SDMA Memory Access Instructions
Functional Unit Instructions
Illegal Instructions
Debug Instructions
Functional Units Programming Model
Burst DMA Unit Programming
Memory Source Address Register (MSA)
Memory Destination Address Register (MDA)
Memory Data Buffer Register (MD)
State Register (MS)
Burst DMA Write (stf)
Burst DMA Read (ldf)
Prefetch/Flush and Auto-Flush Management-Burst DMA Unit
Data Alignment and Endianness-Burst DMA Unit
Burst DMA in Read Mode
Burst DMA in Write Mode
Endianness-Burst DMA Unit
Burst DMA Unit Copy Mode
Burst DMA Unit Error Management
Conditional Yielding-Burst DMA Unit
Peripheral DMA Unit Programming
Peripheral Source Address Register (PSA)
Peripheral Destination Address Register (PDA)
Peripheral Data Register (PD)
Peripheral State Register (PS)
Peripheral DMA Write (stf)-Write Mode
Peripheral DMA Read (ldf)-Read Mode
Peripheral DMA Unit Copy Mode
Error Management
Immediate Errors
Data Transfer Errors
Read Error (First Phase)
Write Error and Read Error (Second Phase)
Copy Mode Errors
Error Check Example
Peripheral DMA Unit Prefetch/Flush Management
OnCE and Real-Time Debug
Memory and Register Access
Hardware Breakpoints
Watchpoints
Software Breakpoints
Core Control
The OnCE Controller
OnCE Commands
Sending Commands to the OnCE Controller
Using the JTAG Interface
Using the Arm platform
Conflicts Between the JTAG and the Arm platform Accesses
Executing a Command from the OnCE
Nature of the Commands
Execution Request
Command Execution
Registers Descriptions
Event Cell Counter Register (ECOUNT)
Event Cell Address Registers (EAA or EAB)
Event Cell Address Mask Register (EAM)
Event Cell Data Register (ED)
Event Cell Data Mask Register (EDM)
Real Time Buffer Register (RTB)
Event Control Register (ECTL)
Trace Buffer (TB)
OnCE Status Register (OSTAT)
JTAG Interface Requirements
TCK Speed Limitation
Synchronization Implementation
JTAG Controller Start-Up Recommended Procedure
Using the OnCE
Activating Clocks in Debug Mode
Getting the Current Status
Methods of Entering Debug Mode
External Debug Request During Reset
Debug Request During Normal Activity
Software Breakpoint Instruction
Event Detection Unit Matching Condition
Executing Instructions in Debug Mode
Command Sequences Examples
Getting the SDMA Status
Saving the Context
Restoring the Context
Accessing the Memory
Resuming Program Execution
Single Stepping in RAM
Single Stepping in ROM
OnCE Event Detection Unit
Clock Gating and Reset
Clocks
Resets
Real Time Features
Trace Buffer
Real Time Buffer
Emulation Pin
Real-Time Debug Outputs
Instruction Set
Instruction Encoding
SDMA Instruction Set
ADD (Addition)
ADDI (Add with Immediate Value)
AND (Logical AND)
ANDI (Logical AND with Immediate Value)
ANDN (Logical AND NOT)
ANDNI (Logical AND with Negated Immediate Value)
ASR1 (Arithmetic Shift Right by 1 Bit)
BCLRI1 (Bit Clear Immediate)
BDF (Conditional Branch if Destination Fault)
BF (Conditional Branch if False)
BSETI (Bit Set Immediate)
BSF (Conditional Branch if Source Fault)
BT (Conditional Branch if True)
BTSTI (Bit Test immediate)
CLRF (Clear Arm platform flags)
CMPEQ (Compare for Equal)
CMPEQI (Compare with Immediate for Equal)
CMPHS (Compare for Higher or Same)
CMPLT (Compare for Less Than)
cpShReg (Update Context of PCU Registers and Flag)
DONE (DONE, Yield)
ILLEGAL (ILLEGAL Instruction)
JMP (Unconditional Jump Immediate)
JMPR (Unconditional Jump)
JSR (Unconditional Jump to Subroutine Immediate)
JSRR (Unconditional Jump to Subroutine)
LD (Load Register)
LDF (Load Register from Functional Unit)
LDI (Load Register with Immediate Value)
LDRPC (Load from RPC to Register)
LOOP (Hardware Loop)
LSL1 (Logical Shift Left by 1 Bit)
LSR1 (Logical Shift Right by 1 Bit)
MOV (Logical Move)
NOTIFY (Notify to Arm platform)
OR (Logical OR)
ORI (Logical OR with Immediate Value)
RET (Return from Subroutine)
REVB (Reverse Byte Order)
Reverse Low Order Bytes(REVBLO)
ROR1 (Rotate Right by 1 Bit)
RORB (Rotate Right by 1 Byte)
SOFTBKPT (Software Breakpoint)
ST (Store Register)
STF (Store Register in Functional Unit)
SUB (Subtract)
SUBI (Subtract with Immediate)
TST (Test with Zero)
TSTI (Test Immediate)
XOR (Logical Exclusive OR)
XORI (Exclusive OR with Immediate)
YIELD, YIELDGE (DONE, Yield)
Software Restrictions
Unsupported Burst DMA Access Sequence
Application Notes
Data Structures for Boot Code and Channel Scripts
Buffer Descriptor Format
Buffer Descriptor Commands for Bootload scripts
Example of Buffer Descriptors for Channel 0.
Channel Context
Typical Data Transfer Supported by SDMA DMA Units
External Memory to External Memory
Peripheral to Peripheral Transfer
Source and Destination Target Have the Same Data Path Width
Source and Destination Target Have a Different Data Path Width
Transfer Between Peripheral and External Memory
Peripheral to External Memory Transfer
External Memory to Peripheral Transfer
Transfer Between External Memory and Internal Memory
Internal Memory to Internal Memory
Transfer Between Peripheral and Internal Memory
Arm Platform Memory Map and Control Register Definitions
SDMAARM
SDMAARM_MC0PTR
SDMAARM_INTR
SDMAARM_STOP_STAT
SDMAARM_HSTART
SDMAARM_EVTOVR
SDMAARM_DSPOVR
SDMAARM_HOSTOVR
SDMAARM_EVTPEND
SDMAARM_RESET
SDMAARM_EVTERR
SDMAARM_INTRMASK
SDMAARM_PSW
SDMAARM_EVTERRDBG
SDMAARM_CONFIG
SDMAARM_SDMA_LOCK
SDMAARM_ONCE_ENB
SDMAARM_ONCE_DATA
SDMAARM_ONCE_INSTR
SDMAARM_ONCE_STAT
SDMAARM_ONCE_CMD
SDMAARM_ILLINSTADDR
SDMAARM_CHN0ADDR
SDMAARM_EVT_MIRROR
SDMAARM_EVT_MIRROR2
SDMAARM_XTRIG_CONF1
SDMAARM_XTRIG_CONF2
SDMAARM_SDMA_CHNPRIn
SDMAARM_CHNENBLn
BP Memory Map and Control Register Definitions
SDMABP
SDMABP_DC0PTR
SDMABP_INTR
SDMABP_STOP_STAT
SDMABP_DSTART
SDMABP_EVTERR
SDMABP_INTRMASK
SDMABP_EVTERRDBG
SDMA Internal (Core) Memory Map and Internal Register Definitions
SDMACORE
SDMACORE_MC0PTR
SDMACORE_CCPTR
SDMACORE_CCR
SDMACORE_NCR
SDMACORE_EVENTS
SDMACORE_CCPRI
SDMACORE_NCPRI
SDMACORE_ECOUNT
SDMACORE_ECTL
SDMACORE_EAA
SDMACORE_EAB
SDMACORE_EAM
SDMACORE_ED
SDMACORE_EDM
SDMACORE_RTB
SDMACORE_TB
SDMACORE_OSTAT
SDMACORE_MCHN0ADDR
SDMACORE_ENDIANNESS
SDMACORE_SDMA_LOCK
SDMACORE_EVENTS2
SDMA Peripheral Registers
Chapter 47: System JTAG Controller (SJC)
Overview
Features
Modes of Operation
External Signals
External Signal Overview
TAP Controller
Accessing ExtraDebug Registers
TAP Selection Block (TSB)
Select Mode Using Software
Boundary Scan Register (BSR)
SoC JTAG Instruction Register (SJIR)
ID_CODE Instruction (IDCODE)
SAMPLE/PRELOAD Instruction
EXTEST Instruction
HIGHZ Instruction
BYPASS Instruction
ENABLE_ExtraDebug Instruction
ENTER_DEBUG instruction
TAP Select Instruction
EXTEST_PULSE instruction
EXTEST_TRAIN instruction
Security
JTAG Security Modes
Mode 1: No Debug - Maximum Security
Mode 2: Secure JTAG - High Security
Challenge/Response Mechanism in System JTAG Mode
Mode 3: JTAG Enabled - Low Security
Software Enabled JTAG
Kill Trace
SJC Disable Fuse
Functional Description
Static Core Debug
Reset Mechanism
Initialization/Application Information
SJC Memory Map/Register Definition
SJC
SJC_GPUSR1
SJC_GPUSR2
SJC_GPUSR3
SJC_GPSSR
SJC_DCR
SJC_SSR
SJC_GPCCR
Chapter 48: Secure Non-Volatile Storage (SNVS)
SNVS overview
SNVS features
Modes of operation
SNVS structure
SNVS_HP (high-power domain)
Non-secure real-time counter
Calibrating the time counter
Time counter alarm
Periodic interrupt
SNVS_LP (low-power domain)
Behavior during system power down
Monotonic Counter (MC)
SNVS reset and system powerup
PMIC interface
SNVS interrupts and alarms
Programming guidelines
RTC control bits setting
RTC value read
General initialization guidelines
SNVS memory map/register definition
SNVS
SNVS_HPLR
SNVS_HPCOMR
SNVS_HPCR
SNVS_HPSR
SNVS_HPRTCMR
SNVS_HPRTCLR
SNVS_HPTAMR
SNVS_HPTALR
SNVS_LPLR
SNVS_LPCR
SNVS_LPSR
SNVS_LPSMCMR
SNVS_LPSMCLR
SNVS_LPGPR
SNVS_HPVIDR1
SNVS_HPVIDR2
Chapter 49: Shared Peripheral Bus Arbiter (SPBA)
Overview
Features
Modes of operation
Clocks
Functional description
Masters arbitration
Resource ownership control
Access control
Peripheral access
Peripheral Right Register access
Owner election
Ending ownership
Software Controlled Ownership Ending
The Un-owned State
SPBA Memory Map/Register Definition
SPBA
SPBA_PRRn
Chapter 50: Sony/Philips Digital Interface (SPDIF)
Overview
External Signals
Clocks
Functional Description
SPDIF Receiver
Audio Data Reception
Application Note
Channel Status Reception
Channel Status Interrupt
User Bit Reception
Validity Flag Reception
SPDIF Receiver Interrupt Exception Definition
Standards Compliance
SPDIF PLOCK Detection and Rxclk Output
Measuring Frequency of SPDIF_RxClk
SPDIF Transmitter
Audio Data Transmission
Channel Status Transmission
Validity Flag Transmission
SPDIF Memory Map/Register Definition
SPDIF
SPDIF_SCR
SPDIF_SRCD
SPDIF_SRPC
SPDIF_SIE
SPDIF_SIS
SPDIF_SIC
SPDIF_SRL
SPDIF_SRR
SPDIF_SRCSH
SPDIF_SRCSL
SPDIF_SRU
SPDIF_SRQ
SPDIF_STL
SPDIF_STR
SPDIF_STCSCH
SPDIF_STCSCL
SPDIF_SRFM
SPDIF_STC
Chapter 51: System Reset Controller (SRC)
SRC Overview
Features
External Signals
Clocks
Top-level resets, power-up sequence and external supply integration
Reset and Power-up Flow
Finite-State Machine (FSM)
Power mode transitions
Power-On Reset and power sequencing
External POR using SRC_POR_B
Internal POR
Functional Description
Reset Control
Reset inputs and outputs
Reset Handling
Reset Qualification
Reset Sequence and De-Assertion
POR (SRC_POR_B)
COLD RESET
WARM RESET
Parallel Reset Requests
Boot Mode Control
BOOT_MODE Pin Latching
SRC Memory Map/Register Definition
SRC
SRC_SCR
SRC_SBMR1
SRC_SRSR
SRC_SISR
SRC_SBMR2
SRC_GPR1
SRC_GPR2
SRC_GPR3
SRC_GPR4
SRC_GPR5
SRC_GPR6
SRC_GPR7
SRC_GPR8
SRC_GPR9
SRC_GPR10
Chapter 52: Temperature Monitor (TEMPMON)
Overview
Software Usage Guidelines
TEMPMON Memory Map/Register Definition
TEMPMON
TEMPMON_TEMPSENSE0n
TEMPMON_TEMPSENSE1n
TEMPMON_TEMPSENSE2n
Chapter 53: Touch Screen Controller (TSC)
Overview
Features
Functional Description
Operating modes
Idle
Pre-charge
Detection
Measurement
Data valid check
Interrupt
Reset
Debug mode
Configuration
TSC configurations
TSC-ADC-TSC analogue configuration
TSC, TSC analogue and ADC connection
TSC and GPIO
ADC-TSC co-working
TSC Memory Map/Register Definition
TSC
TSC_BASIC_SETTING
TSC_PS_INPUT_BUFFER_ADDR
TSC_FLOW_CONTROL
TSC_MEASEURE_VALUE
TSC_INT_EN
TSC_INT_SIG_EN
TSC_INT_STATUS
TSC_DEBUG_MODE
TSC_DEBUG_MODE2
Chapter 54: TrustZone Address Space Controller (TZASC)
Overview
Clocks
Address Mapping in various memory mapping modes
Chapter 55: Universal Asynchronous Receiver/Transmitter (UART)
Overview
Features
Modes of operation
External Signals
Detailed Signal Descriptions
Interrupt Signals
interrupt_uart - UART Interrupt
DMA Request Signals
dma_req_rx - Receiver DMA Request
dma_req_tx - Transmitter DMA Request
Special Signals
stop_req - Stop Mode
doze_req - Doze Mode
debug_req - Debug Mode
Clocks
Functional Description
Interrupts and DMA Requests
Clocks
Clock requirements
Maximum Baud Rate
Clocking in Low-Power Modes
General UART Definitions
RTS_B - UART Request To Send
RTS Edge Triggered Interrupt
DTR_B - Data Terminal Ready
DSR_B - Data Set Ready
DTR_B/DSR_B Edge Triggered Interrupt
DCD_B - Data Carrier Detect
RI_B - Ring Indicator
CTS_B - Clear To Send
Programmable CTS_B Deassertion
TX_DATA - UART Transmit
RX_DATA - UART Receive
Transmitter
Transmitter FIFO Empty Interrupt Suppression
Transmitting a Break Condition
Receiver
Idle Line Detect
Aging Character Detect
Receiver Wake
Receiving a BREAK Condition
Vote Logic
Baud Rate Automatic Detection Logic
Baud Rate Automatic Detection Protocol
New Baud Rate Determination
New Autobaud Counter Stopped bit and Interrupt
Escape Sequence Detection
Binary Rate Multiplier (BRM)
Infrared Interface
Generalities-Infrared
Inverted Transmission and Reception bits (INVT & INVR)
InfraRed Special Case (IRSC) Bit
IrDA interrupt
Conclusion about IrDA
Programming IrDA Interface
High Speed
Low Speed
9-bit RS-485 Mode
Generalities
Transmit 9-bit RS-485 frames
Receive 9-bit RS-485 frames
RS-485 Slave Address Normal Detect Mode
RS-485 Slave Address Automatic Detect Mode
Low Power Modes
UART Operation in System Doze Mode
UART Operation in System Stop Mode
Power Saving Method in UART
UART Operation in System Debug State
Reset
Hardware reset
Software reset
Transfer Error
Functional Timing
IrDA Mode
Initialization
Programming the UART in RS-232 mode
Programming the UART in 9-bit RS-485 mode
References
UART Memory Map/Register Definition
UARTx
UARTx_URXD
UARTx_UTXD
UARTx_UCR1
UARTx_UCR2
UARTx_UCR3
UARTx_UCR4
UARTx_UFCR
UARTx_USR1
UARTx_USR2
UARTx_UESC
UARTx_UTIM
UARTx_UBIR
UARTx_UBMR
UARTx_UBRC
UARTx_ONEMS
UARTx_UTS
UARTx_UMCR
Chapter 56: Universal Serial Bus Controller (USB)
Overview
Features
Modes of Operation
Normal Mode
Low-Power Mode
External Signals
Functional Description
USB 2.0 Controller Core 0
Host Mode
Peripheral (Device) Mode
USB 2.0 Controller Core 1
USB Power Control
Entering Low Power Suspend Mode
Wake-Up Events
Host Mode Events
Interrupts
USB Core Interrupts
USB Wake-Up Interrupts
USB Operation Model
Register Interface
Configuration, Control and Status Register Set
Identification Registers
OTG Operations
Register Bits
Host Data Structures
Periodic Frame List
Asynchronous List Queue Head Pointer
Isochronous (High-Speed) Transfer Descriptor (iTD)
Next Link Pointer
iTD Transaction Status and Control List
iTD Buffer Page Pointer List (Plus)
Split Transaction Isochronous Transfer Descriptor (siTD)
Next Link Pointer
siTD Endpoint Capabilities/Characteristics
siTD Transfer State
siTD Buffer Pointer List (plus)
siTD Back Link Pointer
Queue element transfer descriptor (qTD)
Next qTD Pointer
Alternate Next qTD Pointer
qTD Token
qTD Buffer Page Pointer List
Queue Head
Queue Head Horizontal Link Pointer
Queue Head Endpoint Capabilities/Characteristics
Transfer Overlay-Queue Head
Periodic Frame Span Traversal Node (FSTN)
FSTN Normal Path Pointer
FSTN Back Path Link Pointer
Host Operational Model
Host Controller Initialization
Port Routing and Control
Port Routing Control through EHCI Configured (CF) Bit
Port Routing Control through PortOwner and Disconnect Event
Example Port Routing State Machine
EHCI HC Owner
Companion HC Owner
Port Power
Port Reporting Over-Current
Suspend/Resume-Host Operational Model
Port Suspend/Resume
Schedule Traversal Rules
Example - Preserving Micro-Frame Integrity
Transaction Fit - A Best-Fit Approximation Algorithm
Periodic Schedule Frame Boundaries vs Bus Frame Boundaries
Periodic Schedule
Managing Isochronous Transfers Using iTDs
Host Controller Operational Model for iTDs
Software Operational Model for iTDs
Periodic scheduling threshold
Asynchronous Schedule
Adding Queue Heads to Asynchronous Schedule
Removing Queue Heads from Asynchronous Schedule
Empty Asynchronous Schedule Detection
Restarting Asynchronous Schedule Before EOF
Example Method for Restarting Asynchronous Schedule Traversal
Async Sched Not Active
Async Sched Active
Async Sched Sleeping
Example Derivation for AsyncSchedSleepTime
Asynchronous schedule traversal: Start Event
Reclamation Status Bit (USBSTS Register)
Operational Model for Nak Counter
Nak Count Reload Control
Wait for List Head
Do Reload
Wait for Start Event
Managing Control/Bulk/Interrupt Transfers through Queue Heads
Fetch Queue Head
Advance Queue
Execute Transaction
Interrupt Transfer Pre-condition Criteria
Asynchronous Transfer Pre-operations and Pre-condition Criteria
Transfer Type Independent Pre-operations
Halting a Queue Head
Asynchronous Schedule Park Mode
Write Back qTD
Follow Queue Head Horizontal Pointer
Buffer Pointer List Use for Data Streaming with qTDs
Adding Interrupt Queue Heads to the Periodic Schedule
Managing Transfer Complete Interrupts from Queue Heads
Ping Control
Split Transactions
Split Transactions for Asynchronous Transfers
Asynchronous - Do Start Split
Asynchronous - Do Complete Split
Split Transaction Interrupt
Split Transaction Scheduling Mechanisms for Interrupt
Host Controller Operational Model for FSTNs
Software Operational Model for FSTNs
Tracking Split Transaction Progress for Interrupt Transfers
Split Transaction Execution State Machine for Interrupt
Rebalancing the periodic schedule
Split Transaction Isochronous
Split Transaction Scheduling Mechanisms for Isochronous
Tracking Split Transaction Progress for Isochronous Transfers
Split Transaction Execution State Machine for Isochronous
Periodic Isochronous - Do Start Split
Periodic Isochronous - Do Complete Split
Complete-Split for Scheduling Boundary Cases 2a, 2b
Split Transaction for Isochronous - Processing Examples
Host Controller Pause
Port Test Modes -Host Operational Model
Interrupts-Host Operational Model
Transfer/Transaction Based Interrupts
Transaction Error
Serial Bus Babble
Data Buffer Error
USB Interrupt (Interrupt on Completion (IOC))
Short Packet
Host Controller Event Interrupts
Port Change Events
Frame List Rollover
Interrupt on Async Advance
Host System Error
EHCI Deviation
Embedded Transaction Translator Function
Capability Registers
Operational Registers
Discovery-EHCI Deviation
Data Structures
Operational Model
Micro- frame Pipeline
Split State Machines
Asynchronous Transaction Scheduling and Buffer Management
USB 2.0 - 11.17.3
USB 2.0 - 11.17.4
Periodic Transaction Scheduling and Buffer Management
USB 2.0 - 11.18.6.[1-2]
USB 2.0 - 11.18.[7-8]
Multiple Transaction Translators
Device Operation
USB_USBMODE Register
Non-Zero Fields the Register File
SOF Interrupt
Embedded Design Interface
Frame Adjust Register
Miscellaneous variations from EHCI
Programmable Physical Interface Behaviour
Discovery
Port Reset
Port Speed Detection
Port Test Mode
Device Data Structures
Endpoint Queue Head (dQH)
Endpoint Capabilities/Characteristics
Transfer Overlay-Endpoint Queue Head
Current dTD Pointer
Set-up Buffer
Endpoint Transfer Descriptor (dTD)
Device Operational Model
Device Controller Initialization
Port State and Control
Bus Reset
Suspend/Resume
Suspend
Resume
Managing Endpoints
Endpoint Initialization
Stalling
Data Toggle
Data Toggle Reset
Data Toggle Inhibit
Priming Transmit Endpoints
Priming Receive Endpoints
Operational Model For Packet Transfers
Interrupt/Bulk Endpoint Operational Model
Interrupt/Bulk Endpoint Bus Response Matrix
Control Endpoint Operation Model
Setup Phase
Data Phase
Status Phase
Control Endpoint Bus Response Matrix
Isochronous Endpoint Operational Model
Isochronous Pipe Synchronization
Isochronous Endpoint Bus Response Matrix
Managing Queue Heads
Queue Head Initialization
Operational Model For Setup Transfers
Managing Transfers with Transfer Descriptors
Software Link Pointers
Building a Transfer Descriptor
Executing A Transfer Descriptor
Transfer Completion
Flushing/De-priming an Endpoint
Device Error Matrix
Servicing Interrupts
High-Frequency Interrupts
Low-Frequency Interrupts
Error Interrupts
USB Non-Core Memory Map/Register Definition
USBNC
USBNC_USB_OTG1_CTRL
USBNC_USB_OTG2_CTRL
USBNC_USB_OTG1_PHY_CTRL_0
USBNC_USB_OTG2_PHY_CTRL_0
USB Core Memory Map/Register Definition
USB
USB_nID
USB_nHWGENERAL
USB_nHWHOST
USB_nHWDEVICE
USB_nHWTXBUF
USB_nHWRXBUF
USB_nGPTIMER0LD
USB_nGPTIMER0CTRL
USB_nGPTIMER1LD
USB_nGPTIMER1CTRL
USB_nSBUSCFG
USB_nCAPLENGTH
USB_nHCIVERSION
USB_nHCSPARAMS
USB_nHCCPARAMS
USB_nDCIVERSION
USB_nDCCPARAMS
USB_nUSBCMD
USB_nUSBSTS
USB_nUSBINTR
USB_nFRINDEX
USB_nPERIODICLISTBASE
USB_nDEVICEADDR
USB_nASYNCLISTADDR
USB_nENDPTLISTADDR
USB_nBURSTSIZE
USB_nTXFILLTUNING
USB_nENDPTNAK
USB_nENDPTNAKEN
USB_nCONFIGFLAG
USB_nPORTSC1
USB_nOTGSC
USB_nUSBMODE
USB_nENDPTSETUPSTAT
USB_nENDPTPRIME
USB_nENDPTFLUSH
USB_nENDPTSTAT
USB_nENDPTCOMPLETE
USB_nENDPTCTRL0
USB_nENDPTCTRL1
USB_nENDPTCTRL2
USB_nENDPTCTRL3
USB_nENDPTCTRL4
USB_nENDPTCTRL5
USB_nENDPTCTRL6
USB_nENDPTCTRL7
Chapter 57: Universal Serial Bus 2.0 Integrated PHY (USB-PHY)
USB PHY Overview
Operation
UTMI
Digital Transmitter
Digital Receiver
Analog Receiver
HS Differential Receiver
Squelch Detector
LS/FS Differential Receiver
HS Disconnect Detector
USB Plugged-In Detector
Single-Ended USB_DP Receiver
Single-Ended USB_DN Receiver
9X Oversample Module
Analog Transmitter
Switchable High-Speed 45Ω Termination Resistors
Low-Speed/Full-Speed Differential Driver
High-Speed Differential Driver
Switchable 1.5KΩ USB_DP Pullup Resistor
Switchable 15KΩ USB_DP Pulldown Resistor
Recommended Register Configuration for USB Certification
Charger detection
Charger detect control table
Data pin contact detector
Charger detector
Charger detection software flow
Dead Battery Protect
USB PHY Memory Map/Register Definition
USBPHYx
USBPHYx_PWDn
USBPHYx_TXn
USBPHYx_RXn
USBPHYx_CTRLn
USBPHYx_STATUS
USBPHYx_DEBUGn
USBPHYx_DEBUG0_STATUS
USBPHYx_DEBUG1n
USBPHYx_VERSION
USB Analog Memory Map/Register Definition
USB_ANALOG
USB_ANALOG_USB1_VBUS_DETECTn
USB_ANALOG_USB1_CHRG_DETECTn
USB_ANALOG_USB1_VBUS_DETECT_STAT
USB_ANALOG_USB1_CHRG_DETECT_STAT
USB_ANALOG_USB1_MISCn
USB_ANALOG_USB2_VBUS_DETECTn
USB_ANALOG_USB2_CHRG_DETECTn
USB_ANALOG_USB2_VBUS_DETECT_STAT
USB_ANALOG_USB2_CHRG_DETECT_STAT
USB_ANALOG_USB2_MISCn
USB_ANALOG_DIGPROG
Chapter 58: Ultra Secured Digital Host Controller (uSDHC)
Overview
Features
Modes and Operations
Data Transfer Modes
External Signals
Signals Overview
Clocks
Functional Description
Data Buffer
Write Operation Sequence
Read Operation Sequence
Data Buffer and Block Size
Dividing Large Data Transfer
External DMA Request
DMA AHB Interface
Internal DMA Request
DMA Burst Length
AHB Master Interface
ADMA Engine
ADMA Concept and Descriptor Format
ADMA Interrupt
ADMA Error
Register Bank with IP Bus Interface
SD Protocol Unit
SD control misc
SD Clock control
Command control
Data control
Clock & Reset Manager
Clock Generator
SDIO Card Interrupt
Interrupts in 1-bit Mode
Interrupt in 4-bit Mode
Card Interrupt Handling
Card Insertion and Removal Detection
Power Management and Wake Up Events
Setting Wake Up Events
MMC fast boot
Boot operation
Alternative boot operation
Initialization/Application of uSDHC
Command Send & Response Receive Basic Operation
Card Identification Mode
Card Detect
Reset
Voltage Validation
Card Registry
Card Access
Block Write
Normal Write
DDR Write
Write with Pause
Block Read
Normal Read
DDR Read
Read with Pause
DLL (Delay Line) in Read Path
Suspend Resume
Suspend
Resume
ADMA Usage
Transfer Error
CRC Error
Internal DMA Error
Transfer ADMA Error
Auto CMD12 Error
Card Interrupt
Switch Function
Query, Enable and Disable SDIO High Speed Mode
Query, Enable and Disable SD High Speed Mode/SDR50/SDR104/DDR50
Query, Enable and Disable MMC High Speed Mode
Set MMC Bus Width
ADMA Operation
ADMA1 Operation
ADMA2 Operation
Fast Boot Operation
Normal fast boot flow
Alternative fast boot flow
Fast boot application case (in DMA mode)
Commands for MMC/SD/SDIO
Software Restrictions
Initialization Active
Software Polling Procedure
Suspend Operation
Data Length Setting
(A)DMA Address Setting
Data Port Access
Change Clock Frequency
Multi-block Read
uSDHC Memory Map/Register Definition
uSDHCx
uSDHCx_DS_ADDR
uSDHCx_BLK_ATT
uSDHCx_CMD_ARG
uSDHCx_CMD_XFR_TYP
uSDHCx_CMD_RSP0
uSDHCx_CMD_RSP1
uSDHCx_CMD_RSP2
uSDHCx_CMD_RSP3
uSDHCx_DATA_BUFF_ACC_PORT
uSDHCx_PRES_STATE
uSDHCx_PROT_CTRL
uSDHCx_SYS_CTRL
uSDHCx_INT_STATUS
uSDHCx_INT_STATUS_EN
uSDHCx_INT_SIGNAL_EN
uSDHCx_AUTOCMD12_ERR_STATUS
uSDHCx_HOST_CTRL_CAP
uSDHCx_WTMK_LVL
uSDHCx_MIX_CTRL
uSDHCx_FORCE_EVENT
uSDHCx_ADMA_ERR_STATUS
uSDHCx_ADMA_SYS_ADDR
uSDHCx_DLL_CTRL
uSDHCx_DLL_STATUS
uSDHCx_CLK_TUNE_CTRL_STATUS
uSDHCx_VEND_SPEC
uSDHCx_MMC_BOOT
uSDHCx_VEND_SPEC2
uSDHCx_TUNING_CTRL
Chapter 59: Watchdog Timer (WDOG)
Overview
Features
External signals
Clocks
Watchdog mechanism and system integration
Functional description
Timeout event
Servicing WDOG to reload the counter
Interrupt event
Power-down counter event
Low power modes
STOP and DOZE mode
WAIT mode
Debug mode
Operations
Watchdog reset generation
WDOG_B generation
Reset
Interrupt
Flow Diagrams
Initialization
WDOG Memory Map/Register Definition
WDOGx
WDOGx_WCR
WDOGx_WSR
WDOGx_WRSR
WDOGx_WICR
WDOGx_WMCR
Chapter 60: Crystal Oscillator (XTALOSC)
Overview
External Signals
Crystal Oscillator 24 MHz
Oscillator Configuration (24 MHz)
RC Oscillator (24 MHz)
Crystal Frequency Detection(24 MHz)
Crystal Oscillator 32 kHz
Oscillator Configuration (32 kHz)
Bypass Configuration (32 kHz)
XTALOSC 24MHz Memory Map/Register Definition
XTALOSC24M
XTALOSC24M_MISC0n
XTALOSC24M_LOWPWR_CTRLn
XTALOSC24M_OSC_CONFIG0n
XTALOSC24M_OSC_CONFIG1n
XTALOSC24M_OSC_CONFIG2n
Appendix A: i.MX 6ULL Revision History
Substantive changes from revision 0 to revision 1
Reference Manual Revision History
Introduction Revision History
Memory Maps Revision History
Interrupts and DMA Events Revision History
External Signals Revision History
Fusemap Revision History
External Memory Controllers Revision History
System Debug Revision History
System Boot Revision History
Multimedia Revision History
Power Management Revision History
System Security Revision History
ARM A7 Revision History
ADC Revision History
AIPSTZ Revision History
APBH Revision History
ASRC Revision History
BCH Revision History
CCM Revision History
CSI Revision History
DCP revision history
ECSPI Revision History
EIM Revision History
ENET Revision History
EPDC Revision History
EPIT Revision History
ESAI Revision History
FLEXCAN3 Revision History
GPC Revision History
GPIO Revision History
GPMI Revision History
GPT Revision History
I2C Revision History
IOMUXC Revision History
KPP Revision History
eLCDIF Revision History
MMDC Revision History
MQS Revision History
OCOTP Revision History
OCRAM Revision History
PMU Revision History
PWM Revision History
PXP Revision History
QSPI Revision History
ROMCP Revision History
SAI Revision History
SDMA Revision History
SJC Revision History
SNVS Revision History
SPBA Revision History
SPDIF Revision History
SRC Revision History
TEMPMON Revision History
TSC Revision History
TZASC Revision History
UART Revision History
USB Revision History
USB PHY Revision History
USDHC Revision History
WDOG Revision History
XTALOSC Revision History
i.MX 6ULL Applications Processor
Reference Manual
Document Number: IMX6ULLRM
Rev. 1, 11/2017
i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017
2
NXP Semiconductors
Section number
Contents
Title
Chapter 1
Introduction
Page
1.1
About This Document...................................................................................................................................................159
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
Audience.................................................................................................................................................... 159
Organization...............................................................................................................................................159
Suggested Reading.....................................................................................................................................160
1.1.3.1
General Information...............................................................................................................160
1.1.3.2
Related Documentation..........................................................................................................160
Conventions............................................................................................................................................... 160
Register Access.......................................................................................................................................... 162
1.1.5.1
Register Diagram Field Access Type Legend........................................................................162
1.1.5.2
Register Macro Usage............................................................................................................163
Signal Conventions.................................................................................................................................... 164
Acronyms and Abbreviations.....................................................................................................................164
1.2
1.3
1.4
1.5
Introduction...................................................................................................................................................................167
Target Applications.......................................................................................................................................................167
Features......................................................................................................................................................................... 167
Architectural Overview.................................................................................................................................................171
1.5.1
1.5.2
1.5.3
1.5.4
Simplified Block Diagram......................................................................................................................... 171
Architectural Partitioning...........................................................................................................................172
Endianness Support....................................................................................................................................174
Memory Interfaces..................................................................................................................................... 174
Chapter 2
Memory Maps
2.1 Memory system overview.............................................................................................................................................175
2.2
2.3
ARM Platform Memory Map....................................................................................................................................... 175
DMA memory map....................................................................................................................................................... 181
Chapter 3
i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017
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Section number
Title
Page
Interrupts and DMA Events
3.1
3.2
3.3
Overview.......................................................................................................................................................................183
Cortex A7 interrupts..................................................................................................................................................... 183
SDMA event mapping.................................................................................................................................................. 188
Chapter 4
External Signals and Pin Multiplexing
4.1
Overview.......................................................................................................................................................................191
4.1.1
Muxing Options......................................................................................................................................... 191
Chapter 5
Fusemap
5.1
5.2
5.3
Boot Fusemap............................................................................................................................................................... 215
Lock Fusemap...............................................................................................................................................................226
Fusemap Descriptions Table.........................................................................................................................................227
Chapter 6
External Memory Controllers
6.1
Overview.......................................................................................................................................................................235
6.2 Multi-mode DDR controller (MMDC) overview and feature summary...................................................................... 235
6.3
EIM-PSRAM/NOR flash controller overview..............................................................................................................236
6.3.1
6.3.2
6.3.3
6.3.4
EIM features...............................................................................................................................................236
EIM boot scenarios.................................................................................................................................... 237
EIM boot configuration..............................................................................................................................237
OneNAND requirements............................................................................................................................238
Chapter 7
System Debug
Overview.......................................................................................................................................................................239
Chip and ARM Platform Debug Architecture.............................................................................................................. 239
7.2.1
7.2.2
Debug Features.......................................................................................................................................... 240
Debug system components.........................................................................................................................240
7.2.2.1
AMBA Trace Bus (ATB).......................................................................................................241
7.2.2.2
ATB replicator....................................................................................................................... 241
i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017
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7.1
7.2
4
Section number
Title
Page
7.2.2.3
Embedded Cross Triggering.................................................................................................. 241
7.2.2.3.1
Cross-Trigger Matrix (CTM)..........................................................................242
7.2.2.3.2
Cross-Trigger Interface (CTI).........................................................................243
7.2.2.4
Debug Access Port (DAP)..................................................................................................... 243
7.2.3
Chip-Specific SJC Features....................................................................................................................... 244
7.2.3.1
JTAG Disable Mode.............................................................................................................. 244
7.2.3.2
JTAG ID.................................................................................................................................244
System JTAG Controller - SJC..................................................................................................................244
System JTAG controller main features......................................................................................................245
SJC TAP Port............................................................................................................................................. 245
SJC main blocks.........................................................................................................................................245
7.2.4
7.2.5
7.2.6
7.2.7
7.3
Smart DMA (SDMA) core............................................................................................................................................246
7.3.1
SDMA On Chip Emulation Module (OnCE) Feature Summary............................................................... 246
7.3.1.1
Other SDMA Debug Functionality........................................................................................ 247
7.3.1.2
SDMA ROM Patching........................................................................................................... 248
7.4 Miscellaneous............................................................................................................................................................... 248
7.4.1
Clock/Reset/Power.....................................................................................................................................248
7.5
Supported tools............................................................................................................................................................. 248
Chapter 8
System Boot
8.1
8.2
Overview.......................................................................................................................................................................249
Boot modes................................................................................................................................................................... 250
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
Boot mode pin settings...............................................................................................................................251
High-level boot sequence...........................................................................................................................251
Boot From Fuses mode (BOOT_MODE[1:0] = 00b)................................................................................252
Serial Downloader......................................................................................................................................253
Internal Boot mode (BOOT_MODE[1:0] = 0b10).................................................................................... 255
Boot security settings................................................................................................................................. 255
8.3
Device configuration.....................................................................................................................................................256
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5
Section number
Title
Page
8.3.1
8.3.2
8.3.3
Boot eFUSE descriptions........................................................................................................................... 256
GPIO boot overrides.................................................................................................................................. 258
Device Configuration Data (DCD)............................................................................................................ 259
8.4
Device initialization...................................................................................................................................................... 259
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
Internal ROM/RAM memory map.............................................................................................................260
Boot block activation ................................................................................................................................ 260
Clocks at boot time.................................................................................................................................... 261
Enabling MMU and caches........................................................................................................................263
Exception handling.................................................................................................................................... 264
Interrupt handling during boot................................................................................................................... 264
Persistent bits............................................................................................................................................. 264
8.5
Boot devices (internal boot)..........................................................................................................................................265
8.5.1
NOR flash/OneNAND using EIM interface.............................................................................................. 266
8.5.1.1
NOR flash boot operation...................................................................................................... 266
8.5.1.2
OneNAND flash boot operation............................................................................................ 267
8.5.1.3
IOMUX configuration for EIM devices.................................................................................268
8.5.2
NAND flash............................................................................................................................................... 269
8.5.2.1
NAND eFUSE configuration................................................................................................. 269
8.5.2.2
NAND flash boot flow and Boot Control Blocks (BCB)...................................................... 271
8.5.2.3
Firmware configuration block................................................................................................275
8.5.2.4
Discovered Bad Block Table (DBBT)................................................................................... 278
8.5.2.5
Bad block handling in ROM.................................................................................................. 278
8.5.2.6
Read-retry handling in the ROM........................................................................................... 279
8.5.2.7
Toggle mode DDR NAND boot............................................................................................ 281
8.5.2.7.1
GPMI and BCH clocks configuration.............................................................281
8.5.2.7.2
Setup DMA for DDR transfers....................................................................... 282
8.5.2.7.3
Reconfigure timing and speed using values in FCB.......................................282
8.5.2.8
Typical NAND page organization......................................................................................... 283
8.5.2.8.1
BCH ECC page organization.......................................................................... 283
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Section number
Title
Page
8.5.2.8.2
Metadata..........................................................................................................284
8.5.2.9
IOMUX configuration for NAND......................................................................................... 284
8.5.3
Expansion device....................................................................................................................................... 285
8.5.3.1
Expansion device eFUSE configuration................................................................................ 285
8.5.3.2
MMC and eMMC boot.......................................................................................................... 288
8.5.3.3
SD, eSD, and SDXC.............................................................................................................. 297
8.5.3.4
IOMUX configuration for SD/MMC.....................................................................................297
8.5.3.5
Redundant boot support for expansion device.......................................................................298
8.5.4
Serial ROM through SPI............................................................................................................................ 300
8.5.4.1
Serial ROM eFUSE configuration......................................................................................... 300
8.5.4.2
ECSPI boot.............................................................................................................................301
8.5.4.2.1
ECSPI IOMUX pin configuration.................................................................. 302
8.6
QuadSPI serial flash memory boot............................................................................................................................... 303
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
QuadSPI eFUSE configuration.................................................................................................................. 303
QuadSPI serial flash BOOT operation.......................................................................................................303
QuadSPI configuration parameters............................................................................................................ 304
IOMUX configuration for QSPI devices................................................................................................... 307
QuadSPI boot flow chart............................................................................................................................308
8.7
Program image.............................................................................................................................................................. 309
8.7.1
Image Vector Table and Boot Data............................................................................................................309
8.7.1.1
Image vector table structure...................................................................................................310
8.7.1.2
Boot data structure................................................................................................................. 311
8.7.2
Device Configuration Data (DCD)............................................................................................................ 311
8.7.2.1
Write data command.............................................................................................................. 312
8.7.2.2
Check data command............................................................................................................. 314
8.7.2.3
NOP command.......................................................................................................................315
8.7.2.4
Unlock command................................................................................................................... 316
8.8
8.9
Plugin image................................................................................................................................................................. 316
Serial Downloader........................................................................................................................................................ 317
i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017
NXP Semiconductors
7
Section number
Title
Page
8.9.1
USB............................................................................................................................................................320
8.9.1.1
USB configuration details......................................................................................................320
8.9.1.2
IOMUX configuration for USB............................................................................................. 321
8.9.2
UART.........................................................................................................................................................321
8.9.2.1
UART configuration details...................................................................................................321
8.9.2.2
UART eFUSE configuration..................................................................................................322
8.9.2.3
IOMUX configuration for UART.......................................................................................... 322
8.9.3
Serial Download Protocol (SDP)............................................................................................................... 322
8.9.3.1
SDP commands...................................................................................................................... 323
8.9.3.1.1
READ_REGISTER.........................................................................................323
8.9.3.1.2
WRITE_REGISTER.......................................................................................324
8.9.3.1.3
WRITE_FILE................................................................................................. 325
8.9.3.1.4
ERROR_STATUS.......................................................................................... 326
8.9.3.1.5
DCD_WRITE................................................................................................. 326
8.9.3.1.6
SKIP_DCD_HEADER................................................................................... 327
8.9.3.1.7
JUMP_ADDRESS.......................................................................................... 328
8.10 Recovery devices.......................................................................................................................................................... 329
8.11 USB low-power boot.................................................................................................................................................... 329
8.12
SD/MMC manufacture mode........................................................................................................................................331
8.13 High-Assurance Boot (HAB)........................................................................................................................................332
8.13.1
HAB API vector table addresses................................................................................................................333
Chapter 9
Multimedia
9.1
Display and graphics subsystem................................................................................................................................... 335
9.1.1
9.1.2
9.1.3
9.1.4
Electrophoretic Display Controller............................................................................................................ 336
PiXel Processing Pipeline (PXP)............................................................................................................... 337
LCD Interface (LCDIF)............................................................................................................................. 337
CMOS Sensor Interface (CSI)................................................................................................................... 337
9.2
Audio subsystem...........................................................................................................................................................338
i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017
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NXP Semiconductors
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