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the zynq book.pdf
Contents
Foreword
Acknowledgements
Introduction
1.1. System-on-Chip with Zynq
1.2. Simple Anatomy of an Embedded SoC
1.3. Design Reuse
1.4. Raising the Abstraction Level
1.5. SoC Design Flow
1.6. Practical Elements
1.7. About This Book
1.8. References
PART A
The Zynq Device (“What is it?”)
2.1. Processing System
2.1.1. Application Processing Unit (APU)
2.1.2. A Note on the ARM Model
2.1.3. Processing System External Interfaces
2.2. Programmable Logic
2.2.1. The Logic Fabric
2.2.2. Special Resources: DSP48E1s and Block RAMs
2.2.3. General Purpose Input/Output
2.2.4. Communications Interfaces
2.2.5. Other Programmable Logic External Interfaces
2.3. Processing System — Programmable Logic Interfaces
2.3.1. The AXI Standard
2.3.2. AXI Interconnects and Interfaces
2.3.3. EMIO Interfaces
2.3.4. Other PL-PS Signals
2.4. Security
2.4.1. Secure Boot
2.4.2. Hardware Support
2.4.3. Runtime Security
Zynq-7000 and ARM TrustZone Technology
2.5. Zynq-7000 Family Members
2.6. Chapter Review
2.7. Architecture Reference Guide
2.8. References
Designing with Zynq (“How do I work with it?”)
3.1. Getting Started
3.1.1. Obtaining Design Tools
3.1.2. Design Tool Editions and Licensing
3.1.3. Design Tool Functionality
3.1.4. Third Party Tools
3.1.5. System Setup and Requirements
3.2. An Outline of the Design Flow
3.2.1. Requirements and Specification
3.2.2. System Design
3.2.3. Hardware Development and Testing
3.2.4. Software Development and Testing
3.2.5. System Integration and Testing
3.3. SoC Design Teams
3.4. System-Level IP-Focused Design with Vivado
3.5. The ISE and Vivado Design Suites
3.5.1. Features Comparison
3.5.2. Upgrading to Vivado
3.6. Development Boards
3.6.1. Zynq-7000 SoC ZC702 Evaluation Kit
3.6.2. Zynq-7000 SoC Video & Imaging Kit
3.6.3. Zynq-7000 ZC706 Evaluation Kit
3.6.4. ZedBoard
3.6.5. ZYBO
3.6.6. Third Party Boards
OZ745 Zynq SoC Video Development Kit
MicroZed Evaluation Kit
The Parallella Board
NI myRIO
3.6.7. Accessories and Expansions
3.6.8. Working with Development Boards
3.7. Support and Documentation
3.8. Chapter Review
3.9. References
Device Comparisons (“Why do I need Zynq?”)
4.1. Device Selection Criteria
4.2. Comparison A: Zynq versus FPGA
4.2.1. MicroBlaze Processor
Configuration
Processing Performance
Other Features and Factors
4.2.2. MicroBlaze MicroController System
4.2.3. PicoBlaze
4.2.4. ARM Cortex-M1
4.2.5. Other Processor Types
Soft Processors
Hard Processors
4.2.6. Summary Comments
4.3. Comparison B: Zynq versus Standard Processor
4.3.1. Processor Operation
Non Real-Time Operation
Real-Time Operation
4.3.2. Execution Profiling
4.3.3. Summary Comments
4.4. Comparison C: Zynq versus a Discrete FPGA-Processor Combination
4.5. Exploiting the Zynq Architecture and Design Flow
4.6. Chapter Review
4.7. References
Applications and Opportunities (“What can I do with it?”)
5.1. An Overview of Applications
5.1.1. Automotive
5.1.2. Communications
5.1.3. Defence and Aerospace
5.1.4. Robotics, Control and Instrumentation
5.1.5. Image and Video Processing
5.1.6. Medical
5.1.7. High Performance Computing (HPC)
5.1.8. Others and Future Applications
5.2. When Can Zynq Really Help...?
5.3. Communications: Software Defined Radio (SDR)
5.3.1. Trends in Wireless Communications
5.3.2. Introducing Software Defined Radio (SDR)
5.3.3. SDR Implementation and Enabling Technologies
5.3.4. Cognitive Radio
5.4. Smart Systems and Smart Networks
5.4.1. What is a Smart System?
5.4.2. Examples of Smart Systems
5.4.3. Smart Networks: Communications for Smart Systems
5.4.4. Related Concepts
5.5. Image and Video Processing, and Computer Vision
5.5.1. Image and Video Processing
5.5.2. Computer Vision
5.5.3. Levels of Abstraction
5.5.4. Implementation of Image Processing Systems
5.5.5. Computer Vision on Zynq Example: Road Sign Recognition
5.6. Dynamic System-on-Chip
5.6.1. Run Time System Flexibility
5.6.2. Dynamic Partial Reconfiguration (DPR)
5.6.3. DPR Application Examples
5.6.4. Benefits of DPR
5.7. Further Opportunities: the Zynq ‘EcoSystem’
5.7.1. What is the Ecosystem?
5.7.2. What is the Opportunity?
5.8. Chapter Review
5.9. References
The ZedBoard
6.1. Introducing Zed
6.2. ZedBoard System Architecture
6.3. The Design Flow for ZedBoard
6.4. Getting Started with the ZedBoard
6.4.1. What’s in the Box?
6.4.2. Hardware Setup
6.4.3. Programming the ZedBoard
6.5. MicroZed
6.6. Documentation, Tutorials and Support
6.6.1. Documentation about the ZedBoard
6.6.2. Demonstrations and Tutorials
6.6.3. Online Courseware
6.6.4. Other ZedBoard Resources and Support
6.7. ZedBoard.org Community
6.7.1. Community Projects
6.7.2. Blogs
6.7.3. Support Forums
6.8. Chapter Review
6.9. References
Education, Research and Training
7.1. Technology Trends and SoC Education
7.2. University Teaching with Zynq
7.2.1. Teaching with Xilinx Tools and Boards
7.2.2. Digital Design and FPGA Teaching
7.2.3. Computer Science
7.2.4. Embedded Systems and SoC Design
7.2.5. Algorithm Implementation (e.g. Signal, Image, and Video Processing)
7.2.6. Design Reuse
7.2.7. New and Emerging Design Methods
7.2.8. Sensing, Robotics, and Prototyping
7.2.9. An Example Course
7.3. Projects and Competitions
7.4. Academic Research
7.5. The Xilinx University Program (XUP)
7.5.1. Introducing XUP
7.5.2. Software Support and Licenses
7.5.3. XUP Development and Teaching Boards
7.5.4. XUP Workshops and Training Materials
7.5.5. Technical Support for Universities
7.5.6. Eligibility
7.5.7. Getting in Touch with XUP
7.6. Training for Industry
7.6.1. Courses and Authorised Training Providers
7.6.2. Other Resources
7.6.3. Online Videos
7.7. Chapter Review
7.8. References
First Designs on Zynq
8.1. Software Installation Guide
8.2. Aims and Outcomes
8.3. Overview of Exercise 1A
8.4. Overview of Exercise 1B
8.5. Overview of Exercise 1C
8.6. Possible Extensions
8.7. What Next?
8.8. References
PART B
Embedded Systems and FPGAs
9.1. What is an Embedded System?
9.1.1. Applications
9.1.2. Generic Embedded System Architecture
9.2. Processors
9.2.1. Co-processors
9.2.2. Processor Cache
Dynamic RAM (DRAM)
Static RAM (SRAM)
Level 1 (L1) Cache
Level 2 (L2) Cache
Level 3 (L3) Cache
9.2.3. Execution Cycles
Fetch Instruction
Decode Instruction
Execute Instruction
9.2.4. Interrupts
9.3. Buses
9.3.1. System and Peripheral Buses
System Bus
Peripheral Bus
Bus Bridge
9.3.2. Bus Masters and Slaves
9.3.3. Bus Arbitration
9.3.4. Memory Access
Programmable Input/Output (I/O)
Direct Memory Access (DMA)
9.3.5. Bus Bandwidth
9.4. Chapter Review
9.5. References
Zynq System-on-Chip Design Overview
10.1. Interfacing and Signals
10.1.1. PS-PL AXI Interfaces
10.1.2. PL Co-Processing Interfaces
Accelerator Coherency Port (ACP) Interface
ACP Usage
ACP Limitations
10.1.3. Interrupt Interface
10.2. Interconnects
10.2.1. Interconnect Features
10.2.2. Interconnects, Masters and Slaves
Interconnect Switches
Interconnect Masters
Interconnect Slaves
10.2.3. Connectivity
10.2.4. AXI_HP Interfaces
10.2.5. AXI_ACP Interface
10.2.6. AXI_GP Interfaces
10.3. Memory
10.3.1. Memory Interfaces
Dynamic Memory Interface
Static Memory Interface
10.3.2. On-Chip Memory (OCM)
10.3.3. Memory Map
10.4. Interrupts
10.4.1. Interrupt Signals
10.4.2. Generic Interrupt Controller (GIC)
10.4.3. Interrupt Sources
CPU Private Peripheral Interrupts (PPI)
Shared Peripheral Interrupts (SPI)
Software Generated Interrupts (SGI)
10.4.4. Interrupt Prioritisation and Handling
Interrupt Prioritisation
Interrupt Handling
10.4.5. Further Reading
10.5. Chapter Review
10.6. References
Zynq System-on-Chip Development
11.1. Hardware/Software Partitioning
11.2. Profiling
11.3. Software Development Tools
11.3.1. Software Tools
11.3.2. Hardware Configuration Tools
Vivado IP Integrator
Xilinx Platform Studio
11.3.3. Software Development Kit (SDK)
11.3.4. Microprocessor Debugger
11.3.5. Sourcery CodeBench Lite Edition for Xilinx Cortex-A9 Compiler Toolchain
11.3.6. Logic Analysers
11.3.7. System Generator for DSP
11.4. Chapter Review
11.5. References
Next Steps in Zynq SoC Design
12.1. Prerequisites
12.2. Aims and Outcomes
12.3. Overview of Exercise 2A
12.4. Overview of Exercise 2B
12.5. Overview of Exercise 2C
12.6. Overview of Exercise 2D
12.7. Possible Extensions
12.8. What Next?
IP Block Design
13.1. Overview
13.2. Industry Trends and Philosophy
13.3. IP Core Design Methods
13.3.1. HDL
13.3.2. System Generator
13.3.3. HDL Coder
13.3.4. Vivado High-Level Synthesis
13.3.5. Choosing the Right IP Creation Method
13.4. Simulation and Documentation
13.4.1. Simulation
RTL Simulation
System Generator
HDL Coder
Vivado HLS
13.4.2. Documentation
System Generator
HDL Coder
13.5. Chapter Review
13.6. References
Spotlight on High-Level Synthesis
14.1. High-Level Synthesis Concepts
14.1.1. What is High-Level Synthesis (HLS)?
14.1.2. Motivations for High-Level Synthesis
14.1.3. Design Metrics and Hardware Architectures
14.2. Development of HLS Tools
14.3. HLS Source Languages
14.3.1. C
14.3.2. C++
14.3.3. SystemC
14.3.4. Other Languages for High-Level Synthesis
14.4. Introducing Vivado HLS
14.4.1. What Does Vivado HLS Do?
Algorithm Synthesis
Interfaces I: Interface Synthesis
Interfaces II: Manual Specification
14.4.2. Vivado HLS Design Flow
Inputs to the HLS Process
Functional Verification
High-Level Synthesis
C/RTL Cosimulation
Evaluation of Implementation
Design Iterations
RTL Export
14.4.3. C Functional Verification and C/RTL Cosimulation
14.4.4. Implementation Metrics and Considerations
14.4.5. Overview of the High-Level Synthesis Process
Extraction of Datapath and Control
Scheduling and Binding
Optimisations
A Note on the RTL Output
14.4.6. Solutions: Exploring the Design Space
14.4.7. Vivado HLS Library Support
14.5. HLS in the Design Flow for Zynq
14.6. Chapter Review
14.7. References
Vivado HLS: A Closer Look
15.1. Anatomy of a Vivado HLS Project
15.2. Vivado HLS User Interfaces
15.2.1. Graphical User Interface
Synthesis Perspective: Project Organisation
Synthesis Perspective: Directives Pane
Synthesis Perspective: Synthesis Report
Analysis Perspective
15.2.2. Command Line Interface (CLI)
15.3. Data Types
15.3.1. C and C++ Native Data Types
15.3.2. Vivado HLS Arbitrary Precision Data Types for C and C++
Arbitrary Precision Integer Types
Arbitrary Precision Fixed Point Types
15.3.3. Arbitrary Precision Types for SystemC
15.3.4. Floating Point Data Types and Operators
15.3.5. Validation of Arbitrary Precision Models
15.4. Interface Specification and Synthesis
15.4.1. C/C++ Function Definition
15.4.2. Synthesis of Port-Level Interfaces
Port Name
Port Direction
Data Type and Dimension
15.4.3. Port Interface Protocol Types
15.4.4. Synthesis of Port Interface Protocols
15.4.5. Block-Level Interface Ports and Protocols
15.4.6. Interface Synthesis Directives
Directive Types
Further Options
Source File or Directive File?
15.4.7. Manual Interface Specification
Interface Specification in SystemC
Interface Specification in C/C++
15.5. Algorithm Synthesis
15.5.1. Implementation Metrics and Constraints
Area / Resources
Clock Period, Clock Rate, and Clock Uncertainty
Latency
Initiation Interval and Throughput
15.5.2. Data Types
15.5.3. Pipelining
Algorithm Execution and Data Dependency
Pipelining an Algorithm
15.5.4. Dataflow
15.5.5. Algorithm Case Study: Loops
Default Loop Synthesis
Simple Loop Architecture Variations
Optimisation: Merging Loops
Nested Loops
Optimisation: Flattening Loops
Pipelining Loops
15.5.6. Arrays
15.6. Design Evaluation and Optimisation
15.6.1. Design Constraints
15.6.2. Synthesis Directives
15.6.3. Statistics and Reports
15.6.4. Design Iterations and Optimisation
15.7. Exporting from Vivado HLS
15.7.1. Vivado IP Catalog (IP-XACT Format)
15.7.2. System Generator for DSP
15.7.3. Pcore for XPS
15.8. Chapter Review
15.9. References
Designing With Vivado High Level Synthesis
16.1. Prerequisites
16.2. Aims and Outcomes
16.3. Overview of Exercise 3A
16.4. Overview of Exercise 3B
16.5. Overview of Exercise 3C
16.6. Possible Extensions
16.7. What Next?
IP Creation
17.1. Aims and Outcomes
17.2. Overview of Exercise 4A
17.3. Overview of Exercise 4B
17.4. Overview of Exercise 4C
17.5. Possible Extensions
17.6. What Next?
IP Reuse and Integration
18.1. Overview
18.2. System Design — A System-Level Approach
18.3. IP-XACT
18.4. IP Libraries
18.4.1. Vivado IP Catalog
18.4.2. Third-Party
18.4.3. Custom IP
18.5. IP Integration
18.5.1. IP Integrator
18.5.2. IP Packager
18.6. Chapter Review
18.7. References
AXI Interfacing
19.1. Development of AXI
19.2. Variations of AXI4
19.3. AXI Architecture
19.3.1. Address Channels
19.3.2. Write Data Channel
19.3.3. Read Data Channel
19.3.4. Write Response Channel
19.4. Examples of Applications
19.5. AXI Transactions
19.5.1. AXI Write-Burst Transaction
19.5.2. AXI Read-Burst Transaction
19.6. AXI in the Xilinx Toolflow
19.7. Summary
19.8. References
Adventures with IP Integrator
20.1. Aims and Outcomes
20.2. Exercise 4A
20.3. Exercise 4B
20.4. Exercise 4C
20.5. Possible Extensions
20.6. What Next?
PART C
Introduction to Operating Systems on Zynq
21.1. Why Use an Embedded Operating System?
21.1.1. Reducing Time to Market
21.1.2. Make Use of Existing Features
21.1.3. Reduce Maintenance and Development Costs
21.2. Choosing the Right Type of Operating System
21.2.1. Standalone Operating Systems
21.2.2. Real-Time Operating Systems (RTOS)
21.2.3. Other Embedded Operating Systems
Linux
Android
21.2.4. Further Considerations
21.3. Applications
21.4. Multi-Processor Systems
21.5. Zynq Operating Systems
21.5.1. Linux
Xilinx Zynq-Linux
Petalogix® - Petalinux
Xillybus - Xillinux
21.5.2. RTOS
FreeRTOS
21.5.3. Further Operating Systems
21.6. Chapter Review
21.7. References
Linux: An Overview
22.1. A Brief History
22.2. Linux System Overview
22.3. Licensing
22.3.1. GNU General Public licence
22.4. Development Tools and Resources
22.4.1. Virtual Machines
22.4.2. Version Control
22.4.3. Git
22.4.4. Debugging Linux
22.5. Chapter Review
22.6. References
The Linux Kernel
23.1. Linux Kernel Hierarchy
23.2. System Call Interface
23.3. Memory Management
23.3.1. Virtual Memory
23.3.2. High and Low Memory
23.4. Process Management
23.4.1. Process Representation
23.4.2. Process Creation, Scheduling and Destruction
23.5. File System
23.5.1. Linux File Systems
23.5.2. Virtual File System
23.6. Architecture-Dependent Code
23.7. Linux Device Drivers
23.7.1. A Note on Mechanisms Vs. Policies
23.7.2. Module/Device Classification
23.8. Chapter Review
23.9. References
Linux Booting
24.1. Overview
24.2. Stages of the Desktop Linux Boot Process
24.2.1. BIOS
24.2.2. First-Stage Bootloader (FSBL)
24.2.3. Second-Stage Bootloader (SSBL)
24.2.4. Kernel
24.2.5. Init
24.3. Booting Zynq
24.3.1. Zynq Boot Files
The first of these files, BOOT.BIN, is the zynq boot image file. It is actually the combination of 2 compulsory files, the FSBL and SSBL executable and linkable format (.elf) files, and an optional bitstream (.bit) file. The FSBL and SSBL files, as t...
24.3.2. Stage-0 (Boot ROM)
24.3.3. Stage-1 (First-Stage Bootloader)
Boot Image Format (BIF)
Authentication Certificate
BootGen
24.3.4. Stage-2 (Second-Stage Bootloader)
24.4. Chapter Review
24.5. References
Postscript
Glossary
List of Acronyms
Index
The Zynq Book
Embedded Processing with the
ARM® Cortex®-A9 on the Xilinx®
Zynq®-7000 All Programmable SoC
The Zynq Book
Embedded Processing with the
ARM® Cortex®-A9 on the Xilinx®
Zynq®-7000 All Programmable SoC
Louise H. Crockett
Ross A. Elliot
Martin A. Enderwitz
Robert W. Stewart
Department of Electronic and Electrical Engineering
University of Strathclyde
Glasgow, Scotland, UK
1st Edition
This edition first published July 2014 by Strathclyde Academic Media.
© Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz and Robert W. Stewart.
Open Source Licence to Use and Reproduce
This book is available in print and as an electronic book (PDF format).
Text and diagrams from this book may be reproduced in their entirety and used for non-profit academic purposes, provided
that a clear reference to the original source is made in all derivative documents. This reference should be of the following
form:
L. H. Crockett, R. A. Elliot, M. A. Enderwitz and R. W. Stewart, The Zynq Book: Embedded Processing with the ARM Cortex-
A9 on the Xilinx Zynq-7000 All Programmable SoC, First Edition, Strathclyde Academic Media, 2014.
Requests to use content from this book for other than non-profit academic purposes should be made to info@zynqbook.com.
This book may not be reproduced in its original form and sold by any unauthorised third party.
Tutorial Materials
Tutorial materials are distributed via the book’s companion website: www.zynqbook.com.
The tutorials are provided with the same Open Source License to Use and Reproduce, and the same Warning and Disclaimer, as
detailed elsewhere on this page in reference to the main book.
Warning and Disclaimer
The best efforts of the authors and publisher have been used to ensure that accurate and current information is presented in
this book. This includes researching the topics covered and developing examples. The material included is provided on an “as
is” basis in the best of faith, and neither the authors and publishers make any warranty of any kind, expressed or implied, with
regard to the documentation contained in this book. The authors and publisher shall not be held liable for any loss or damage
resulting directly or indirectly from any information contained herein.
Trademarks
ARM, Cortex, AMBA, Thumb and TrustZone are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/
or elsewhere. All rights reserved.
NEON is a trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
This publication is independent and it is not affiliated with, or endorsed, sponsored or authorised by ARM Limited.
Xilinx, the Xilinx logo, Artix, ISE, Kintex, LogiCORE, Petalogix, Spartan, Virtex, Vivado, Zynq, and WebPACK are registered
trademarks of Xilinx. All rights reserved.
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All other trademarks used in this book are acknowledged as belonging to their respective companies. The use of trademarks
in this book does not imply any affiliation with, or endorsement of, this book by trademark owners.
Contents
Foreword
Acknowledgements
xxi
xxiii
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Introduction
1
System-on-Chip with Zynq ................................................................2
Simple Anatomy of an Embedded SoC ............................................5
Design Reuse ........................................................................................7
Raising the Abstraction Level ............................................................7
SoC Design Flow ..................................................................................8
Practical Elements .............................................................................10
About This Book ................................................................................10
References ...........................................................................................12
PART A
Getting to Know Zynq
13
CHAPTER 2
2.1
2.2
The Zynq Device (“What is it?”)
15
Processing System ..............................................................................16
2.1.1
Application Processing Unit (APU) .................................17
A Note on the ARM Model ...............................................20
2.1.2
2.1.3
Processing System External Interfaces .............................21
Programmable Logic .........................................................................22
vii
The Logic Fabric .................................................................23
2.2.1
Special Resources: DSP48E1s and Block RAMs .............25
2.2.2
General Purpose Input/Output .........................................28
2.2.3
2.2.4
Communications Interfaces ..............................................29
2.2.5 Other Programmable Logic External Interfaces .............29
Processing System — Programmable Logic Interfaces ................30
The AXI Standard ...............................................................30
2.3.1
AXI Interconnects and Interfaces .....................................31
2.3.2
2.3.3
EMIO Interfaces ..................................................................34
2.3.4 Other PL-PS Signals ...........................................................34
Security ................................................................................................35
2.4.1
Secure Boot ..........................................................................35
2.4.2 Hardware Support ..............................................................36
2.4.3
Runtime Security ................................................................36
Zynq-7000 Family Members ............................................................39
Chapter Review ..................................................................................40
Architecture Reference Guide .........................................................41
References ...........................................................................................44
Designing with Zynq (“How do I work with it?”)
47
Getting Started ...................................................................................48
3.1.1 Obtaining Design Tools .....................................................48
3.1.2
Design Tool Editions and Licensing ................................49
Design Tool Functionality .................................................50
3.1.3
3.1.4
Third Party Tools ................................................................51
3.1.5
System Setup and Requirements ......................................51
An Outline of the Design Flow ........................................................53
Requirements and Specification .......................................54
3.2.1
3.2.2
System Design .....................................................................54
3.2.3 Hardware Development and Testing ...............................55
Software Development and Testing .................................58
3.2.4
3.2.5
System Integration and Testing ........................................60
SoC Design Teams .............................................................................60
System-Level IP-Focused Design with Vivado ..............................62
The ISE and Vivado Design Suites .................................................64
3.5.1
Features Comparison .........................................................64
2.3
2.4
2.5
2.6
2.7
2.8
CHAPTER 3
3.1
3.2
3.3
3.4
3.5
viii
3.6
3.7
3.8
3.9
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
CHAPTER 5
5.1
3.5.2
Upgrading to Vivado ..........................................................66
Development Boards .........................................................................67
Zynq-7000 SoC ZC702 Evaluation Kit ............................67
3.6.1
Zynq-7000 SoC Video & Imaging Kit ..............................69
3.6.2
Zynq-7000 ZC706 Evaluation Kit ....................................69
3.6.3
3.6.4
ZedBoard ..............................................................................69
ZYBO ....................................................................................69
3.6.5
Third Party Boards .............................................................70
3.6.6
3.6.7
Accessories and Expansions ..............................................71
3.6.8 Working with Development Boards ................................72
Support and Documentation ...........................................................72
Chapter Review ..................................................................................72
References ...........................................................................................73
Device Comparisons (“Why do I need Zynq?”)
77
Device Selection Criteria ..................................................................78
Comparison A: Zynq versus FPGA .................................................80
4.2.1 MicroBlaze Processor .........................................................80
4.2.2 MicroBlaze MicroController System ...............................84
PicoBlaze ..............................................................................85
4.2.3
4.2.4
ARM Cortex-M1 .................................................................85
4.2.5 Other Processor Types .......................................................85
4.2.6
Summary Comments .........................................................87
Comparison B: Zynq versus Standard Processor ..........................89
Processor Operation ...........................................................89
4.3.1
4.3.2
Execution Profiling .............................................................92
4.3.3
Summary Comments .........................................................94
Comparison C: Zynq versus a Discrete FPGA-Processor
Combination ......................................................................................94
Exploiting the Zynq Architecture and Design Flow .....................96
Chapter Review ..................................................................................98
References ...........................................................................................99
Applications and Opportunities
(“What can I do with it?”)
101
An Overview of Applications .........................................................102
ix
Automotive ........................................................................102
5.1.1
Communications ..............................................................102
5.1.2
Defence and Aerospace ....................................................103
5.1.3
Robotics, Control and Instrumentation ........................103
5.1.4
5.1.5
Image and Video Processing ...........................................104
5.1.6 Medical ...............................................................................105
5.1.7 High Performance Computing (HPC) ..........................105
5.1.8 Others and Future Applications .....................................105
5.2 When Can Zynq Really Help...? ....................................................106
Communications: Software Defined Radio (SDR) .....................107
5.3
Trends in Wireless Communications ............................107
5.3.1
5.3.2
Introducing Software Defined Radio (SDR) .................108
SDR Implementation and Enabling Technologies .......108
5.3.3
5.3.4
Cognitive Radio .................................................................110
Smart Systems and Smart Networks .............................................111
5.4.1 What is a Smart System? ..................................................111
Examples of Smart Systems .............................................112
5.4.2
Smart Networks: Communications for Smart Systems 114
5.4.3
5.4.4
Related Concepts ..............................................................115
Image and Video Processing, and Computer Vision .................115
Image and Video Processing ...........................................115
5.5.1
5.5.2
Computer Vision ..............................................................116
Levels of Abstraction ........................................................117
5.5.3
Implementation of Image Processing Systems .............118
5.5.4
Computer Vision on Zynq Example: Road Sign
5.5.5
Recognition ........................................................................120
Dynamic System-on-Chip ..............................................................121
Run Time System Flexibility ...........................................121
5.6.1
5.6.2
Dynamic Partial Reconfiguration (DPR) ......................121
DPR Application Examples .............................................122
5.6.3
5.6.4
Benefits of DPR .................................................................124
Further Opportunities: the Zynq ‘EcoSystem’ .............................125
5.7.1 What is the Ecosystem? ....................................................125
5.7.2 What is the Opportunity? ................................................126
Chapter Review ................................................................................128
References .........................................................................................128
5.8
5.9
5.6
5.4
5.5
5.7
x
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