THE DESIGNER’S GUIDE TO VERILOG-AMS.pdf

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front-matter

Contents

1. Introduction

1 Hardware Description Languages

2 The Verilog Family of Languages

3 Mixed-Signal Simulators

4 Applications of Verilog-AMS

2. Top-Down Design

1 Mixed-Signal Design Productivity

2 Traditional Approaches to Mixed-Signal Design

3 Principles of Top-Down Design

4 A Rigorous Top-Down Design Process

5 Further Benefits of Top-Down Design

6 Final Words on Top-Down Design

3. Analog Modeling

1 Resistor

2 A Simple Circuit

3 Motor

4 Junction Diode

5 Resistive Port

6 Relay

7 Voltage-Controlled Oscillator

8 Periodic Sample and Hold

9 Time Interval Measurement

10 Analog to Digital Converter

11 Digital to Analog Converter

12 Lossy Inductor

13 Tolerances

14 Elements of Style

What’s Next

4. Mixed-Signal Modeling

1 Mixed Signal Models

2 Modeling Discrete Behavior

3 Modeling Mixed-Signal Behavior

4 Structural Verilog-AMS

What’s Next

5. Language Reference

1 Basics

2 Data Types

3 Signals

4 Expressions

5 System Functions and Tasks

6 Analog Behavior

7 Discrete-Event Behavior

8 Mixed Behavior

9 Hierarchy

10 Other Features of Verilog-HDL

What’s Next

Compatibility A

1 Verilog-HDL Compatibility

2 SPICE Compatibility

3 Spectre Compatibility

4 AMS Designer Compatibility

References

Index

THE DESIGNER’S GUIDE TO VERILOG-AMS

THE DESIGNER’S GUIDE BOOK SERIES Consulting Editor Kenneth S. Kundert Books in the series: The Designer’s Guide to Verilog-AMS ISBN: 1-4020-8044-1 The Designer’s Guide to SPICE AND Spectre® ISBN: 0-7923-9571-9

THE DESIGNER’S GUIDE TO VERILOG-AMS First Edition June 2004 KENNETH S. KUNDERT Cadence Design Systems OLAF ZINKE Cadence Design Systems KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: Print ISBN: 1-4020-8045-X 1-4020-8044-1 ©2004 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2004 Kluwer Academic Publishers Boston All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: http://kluweronline.com http://ebooks.kluweronline.com

Contents Chapter 1 Introduction 1 2 3 4 Hardware Description Languages The Verilog Family of Languages Mixed-Signal Simulators Applications of Verilog-AMS 4.1 4.2 4.3 4.4 4.5 Component Modeling Test Benches Simulation Acceleration Mixed-Signal Design Top-Down Design Chapter 2 Top-Down Design 1 2 3 4 5 A Shared Design Representation Every Change is Verified Verification Planning Multiple Passes Executable Specifications and Plans Simulation and Modeling Plans System-Level Verification Mixed-Level Simulation Bottom-Up Verification Final Verification Test Mixed-Signal Design Productivity Traditional Approaches to Mixed-Signal Design 2.1 Bottom-Up Design Moving to Top-Down Design 2.2 Principles of Top-Down Design 3.1 3.2 3.3 3.4 3.5 A Rigorous Top-Down Design Process 4.1 4.2 4.3 4.4 4.5 4.6 Further Benefits of Top-Down Design 5.1 5.2 5.3 5.4 5.5 Improves Communications Between Engineers Improves Productivity Improves Ability to Handle Complex Designs Allows Parallel Execution of Design Tasks Supports IP Reuse 1 1 2 5 8 8 10 10 11 11 13 13 16 17 17 19 20 21 22 23 23 24 24 26 27 28 29 30 30 30 30 31 31 31

Contents 32 35 35 39 40 41 41 46 50 51 54 58 60 63 65 67 69 71 73 73 77 79 80 84 87 88 94 96 99 99 100 100 109 111 113 115 118 121 122 123 128 131 6 Final Words on Top-Down Design Chapter 3 Analog Modeling 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Conservative Systems Natures and Disciplines Junction Diode with Series Resistor Probes and Sources Series and Parallel RLC Capacitor Inductor Voltage and Current Sources Resistor 1.1 1.2 1.3 A Simple Circuit 2.1 Motor 3.1 Junction Diode 4.1 4.2 4.3 Resistive Port Relay 6.1 6.2 6.3 Voltage-Controlled Oscillator Periodic Sample and Hold 8.1 Time Interval Measurement Analog to Digital Converter Digital to Analog Converter Lossy Inductor Tolerances Elements of Style Non-Ideal Relay Ideal Mechanical Stop Ideal Diode Smoothing the Output Chapter 4 Mixed-Signal Modeling Language Basics Integers and Reals Mixed Signal Models Modeling Discrete Behavior 2.1 2.2 Modeling Mixed-Signal Behavior 3.1 3.2 3.3 Structural Verilog-AMS 4.1 4.2 4.3 4.4 Connecting Analog and Digital Discipline Resolution Automatic Connect Module Insertion Modeling Connect Modules Analog and Digital Contexts From Digital to Analog From Analog to Digital 1 2 3 4 vi

Contents Chapter 5 Language Reference 1 Basics Comments Identifiers Keywords Compiler Directives Constants Variables Parameters Natures and Disciplines Ports, Nets, and Nodes Branches 1.1 1.2 1.3 1.4 Data Types 2.1 2.2 2.3 2.4 2.5 2.6 Signals 3.1 3.2 Expressions Operators 4.1 Functions 4.2 Mathematical Functions 4.3 Logical Functions 4.4 Environment Functions 4.5 Analog Operators 4.6 Thresholding Functions 4.7 Limiting Functions 4.8 Small-Signal Stimulus Functions 4.9 4.10 User-Defined Functions Continuous-Time Signal Access Contributions 2 3 4 5 6 7 Simulator Interface Display Tasks File Operation Tasks Random Numbers System Functions and Tasks 5.1 5.2 5.3 5.4 Analog Behavior 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Discrete-Event Behavior 7.1 7.2 Analog Processes Procedural Blocks Assignments Contributions Conditionals Iterators User-Defined Analog Functions Analog Events Initial and Always Processes Procedural Blocks 149 149 149 149 150 151 152 152 155 157 159 164 167 167 168 169 172 172 172 175 175 175 177 188 188 189 190 190 190 191 193 194 195 196 196 198 198 200 202 204 204 208 209 209 vii

Contents 211 212 215 216 220 220 220 222 223 225 225 225 226 226 226 227 229 230 233 234 235 235 236 236 237 239 241 241 241 244 247 248 249 257 257 Concurrent Blocks Assignments Nets and Registers Timing Control Conditionals Iterators User-Defined Functions and Tasks 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Mixed Behavior 8.1 8.2 8.3 8.4 8.5 Hierarchy 9.1 9.2 9.3 9.4 9.5 Other Features of Verilog-HDL Modules Instantiation Gate-Level Descriptions Hierarchical Names Mixed Signal Structure Discrete-Event Values in an Analog Process Discrete Events in an Analog Process Continuous-Time Values in an Initial or Always Process Continuous Events in an Initial or Always Process Calling Functions Appendix A Compatibility 8 9 10 1 2 3 4 viii Scope of Compatibility Accessing SPICE Objects from Verilog-A/MS Preferred Primitive, Parameter and Port Names Other Issues Verilog-HDL Compatibility SPICE Compatibility 2.1 2.2 2.3 2.4 Spectre Compatibility 3.1 3.2 3.3 AMS Designer Compatibility 4.1 4.2 4.3 Using Verilog-A with Spectre Accessing Spectre Objects from Verilog-A Spectre’s Implementation of Verilog-A Using Verilog-AMS with AMS Designer Referencing SPICE Referencing VHDL-AMS

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