3D NAND Flash:
Gen3 X3 128Gb 2-Plane
Revision 1.0
August 16, 2017
Marketing Part Numbers
TSOP
Die
SDTNBIAMA-016G
1 die
Western Digital Proprietary and Confidential
Copyright ©2017 Western Digital Corporation or its affiliates.
All rights reserved.
This specification is confidential and is subject to any Western Digital
Corporation or its affiliates’ handbooks or terms of use provided or made
available to the customer. This specification is subject to change and/or being
updated without notice. The customer assumes sole and exclusive
responsibility for compliance with safety, environmental, export, trade, and
other applicable laws and regulations with respect to this specification. In
addition, the customer assumes sole and exclusive responsibility for any use,
embedded or otherwise, of device(s) described by this specification in any
medical, aviation, nuclear, or ultra-hazardous applications, as well as in
applications that could cause property damage, bodily injury, or death.
All specifications are subject to change without notice.
a Western Digital brand
Western Digital Proprietary and Confidential
3D NAND Flash: Gen3 X3 128Gb 2-Plane
a Western Digital brand
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Ball/Pin Functions, Definitions, and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
TSOP Package Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
Device Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
3.4.1
Erase Before Initial Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.2 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.3
Invalid Blocks (Bad Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.4
Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4.5 Dynamic Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 NAND Flash Logic, Commands, and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
Logic Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Command Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
NAND Flash Command Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
4.3.1
SLC Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TLC Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.2
4.3.3
Six-Address-Cycle Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Operating Modes and Device Initiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Status Read Cycle Following a Power-On Sequence or User Reset . . . . . . . . . . . . . . 24
5.1.1
5.1.2
Power Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.3 WPn Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chip Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
5.3
Read ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Device Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
DC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1
AC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2
7.2.1
SDR Mode AC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.2
Toggle Mode AC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.3 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.4
Ready/Busy (R/Bn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2.5 AC Differential Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.6 AC Characteristics: Differential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Read, Program, and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3
Toggle Mode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4
7.4.1
AC Overshoot/Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I/O Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5
7.6
Input/Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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©2017 Western Digital Corporation, All rights reserved
Western Digital Proprietary and Confidential
3D NAND Flash: Gen3 X3 128Gb 2-Plane
a Western Digital brand
7.6.1
Input Slew Rate De-Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8 Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Switching Between SDR and Toggle Mode Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1
8.2
Single-Level-Cell (SLC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Switching to SLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.2.1
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9
9.1
SLC Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
TLC Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2
TLC Pages and Wordlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.1
9.2.2
TLC Page Read with Change Read Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.2.3 Data Out after TLC Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.2.4
TLC Random Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10 Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1
SLC Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SLC Program Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.1
TLC Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.2
10.2.1
TLC Program Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.2 TLC Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.3 Copy-Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.4 Copy-Back Program with Change Write Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.2.5 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3
Program Functions Supported in both SLC and TLC . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.3.1
Supported Commands Following Serial Data Input (80h) . . . . . . . . . . . . . . . . . . . . . . 80
10.3.2 Programming Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.3 Peak Current Reduction During Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3.4 Program with Change Write Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11
SLC Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1
11.2
TLC Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.3
Erase Suspend/Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12 Device Status Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.1
Read Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.2
Read Status Enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Reset Command Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.1
13.2
Reset by Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Set Features Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13.3
13.3.1
Power-On Reset During Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14 Set Features Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Toggle 2.0-Specific Setting (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.1
Output Drive Settings (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.2
14.3
Vendor-Specific Setting (80h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.4 Warm-up/Latency Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.4.1
Input Warm-up/Latency Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.4.2 Output Warm-up/Latency Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.4.3 Warm-up/Latency Cycle Options and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Western Digital Proprietary and Confidential
3D NAND Flash: Gen3 X3 128Gb 2-Plane
a Western Digital brand
15 Get Features Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
16 ZQ Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
16.1
RZQ Values and Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
17 SDR Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
18 Toggle Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
18.1
Pause and Hold Options During Data-out and Data-in . . . . . . . . . . . . . . . . . . . . . . . . . 128
18.1.1
Data-out Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
18.1.2 Data-out Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
18.1.3 Data-in Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
18.1.4 Data-in Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
19 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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3D NAND Flash: Gen3 X3 128Gb 2-Plane
Features
Description
18,336 x 8 bits x 768 pages x 758 blocks
2
TLC: 12MB
(18,336 × 768 = 14,082,048 bytes)
1516
4
64
18,336 bytes (16,384 + 1952 ECC)
TLC: 768 pages
SLC: 256 pages
SLC: 4MB
(18,336 × 256 = 4,694,016 bytes)
a Western Digital brand
1
Features
Table 1: Device Features
Feature
Organization
Memory cell array (per plane)
Planes per die
Block size
Blocks per die
Shared strings
Wordlines (WLs) per block
Page size
Pages per block
Number of valid blocks (NVBD)
Minimum valid blocks per die
Modes
ID Read
Set/Get Features
Dynamic Read
Status Read
Reset operation
1384
TLC Page Read
Cache Read
SLC Read
TLC Block Erase
SLC Erase
TLC Program
Cache Program
SLC Program
TLC Program Suspend/Resume
*All modes are functional in single- or multi-plane operations
Access time
Cell array to register (tR)
Program/Erase time
Program (typ)
Single Block Erase (typ)
Power supply
I/O Interface
Toggle Mode data transfer rate1
Conventional SDR data transfer
rate
Operating temperature
TCASE
Lower page:
Middle page:
Upper page:
SLC:
65µs (typ)
80µs (typ)
65µs (typ)
40µs (typ)
TLC: (average of l/m/u pages)
SLC: (per page)
(typ) per block
2400µs
320µs
6.5ms
VCC: 2.35–3.6V
DDR2 max: (1.8V range only)
266 MHz (533 Mbps)
50 MHz (50 Mbps)
VCCQ: 2.7–3.6V (3.3V range)
or 1.7–1.95V (1.8V range)
DDR1 max: (1.8/3.3V ranges)
100 MHz (200 Mbps)
0°C to 70°C
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a Western Digital brand
Table 1: Device Features (cont’d)
Feature
Operating current
Read (random data)
Program (avg)
Erase (avg)
Standby:
Package
TSOP
TLC: 40mA max
TLC: 35mA max
TLC: 25mA max
100µA max per die
48-pin TSOP
3D NAND Flash: Gen3 X3 128Gb 2-Plane
Features
Description
SLC: 40mA max
SLC: 35mA max
SLC: 25mA max
Note 1. To determine whether a device supports toggle mode, refer to the marketing part numbers on
the cover page and Figure 1, “Part Numbering Decoder with Example Part Number,” on page 3.
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a Western Digital brand
1.1
Part Numbering
3D NAND Flash: Gen3 X3 128Gb 2-Plane
Part Numbering
Figure 1: Part Numbering Decoder with Example Part Number
SD
T
N
B
I
A
M
A –016G
SanDisk:
Slot 1–2
Package Type: Slot 3
T = 48-pin TSOP
X = 132-ball BGA, 12mm x 18mm x x.xmm
Y = 132-ball BGA, 13mm x 18mm x x.xmm
Family: Slot 4
N = NAND components
Process: Slot 5
A = 3D Gen2
B = 3D Gen3
C = 3D Gen4
Customizations:
Slot 14
TBD
Slot 15
TBD
Capacity: Slot 10–13
G = gigabyte (GB)
T = terabyte (TB)
CE R/B
Signal Count: Slot 9
A =
1
B = 2
C = 4
G = 2
H = 4
I = 8
M = 4
1
1
1
2
2
2
4
Memory: Slot 6
C = Eight-level cell (8LC) 1-plane
F = Four-level cell (4LC) 1-plane
G = Four-level cell (4LC) 2-plane
H = Four-level cell (4LC) 4-plane
I = Eight-level cell (8LC) 2-plane
Assembly: Slot 8
M = Pb-free (100% tin)
P = Pb-free (Sn/Ag/Cu—SAC 105)
R = Pb-free (others)
Die Count: Slot 7
A = 1 die
B = 2 die
C = 4 die
D = 8 die
E = 16 die
3d_gen3_x3_128_2p__1.fm
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©2017 Western Digital Corporation, All rights reserved
Western Digital Proprietary and Confidential
a Western Digital brand
2 Device Overview
3D NAND Flash: Gen3 X3 128Gb 2-Plane
Device Overview
The SanDisk® 3D NAND Flash: Gen3 X3 128Gb memory device
contains a single 128Gb device in a 48-pin TSOP package. All
possible configurations may not be available. For a list of current
part numbers, see "Marketing Part Numbers” on page 0, and
Figure 1 on page 3 for part number decoding.
This device supports a Toggle Mode interface speed of up to
100 MHz (200 Mbps) for DDR1, and up to 266 MHz (533 Mbps)
for DDR2.
Toggle Mode is a NAND Flash interface for high-performance
applications that support data-in (DIN) and data-out (DOUT)
operations on both the rising and falling edges of the data strobe
(DQS) signal.
Toggle Mode NAND implements “Double Data Rate” operation
which is backward compatible with the commands supported in
conventional SDR (Legacy Mode) NAND, and provides a high
data-transfer rate based on the high-speed Toggle Mode interface.
Differential signals (DQS, DQSn, REn, RE) are used in DDR2
Toggle Mode. Single-ended signals DQS and REn are used in DDR1
Toggle Mode.
NOTE: From this point on:
• Conventional SDR (single data rate) operation will be referred to
simply as “SDR.”
• Single-level-cell (SLC) and three-level-cell (TLC) operation are
most often referred to by their respective acronyms, SLC and
TLC. The term three-bits-per-cell (3bpc) may also occur and is
used interchangeably with TLC.
3d_gen3_x3_128_2p__1.fm
8/16/17__Rev. 1.0
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©2017 Western Digital Corporation, All rights reserved