IEEE verilog 2001 标准文档.pdf

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IEEE Std 1364-2001 (Revision of IEEE Std 1364-1995) IEEE Computer Society Sponsored by the Design Automation Standards Committee Description Language s s IEEE Standard Verilog® Hardware d d r r a a d d n n a a t t S S E E E E E E I I Published by The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA 28 September 2001 Print: SH94921 PDF: SS94921

IEEE Std 1364-2001 (Revision of IEEE Std 1364-1995) ® IEEE Standard Verilog Description Language Hardware Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 17 March 2001 IEEE-SA Standards Board ¤ Abstract: Hardware Description Language (HDL) is defined in this standard. Verilog The Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Be- cause it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language. Keywords: computer, computer languages, digital systems, electronic systems, hardware, hard- ware description languages, hardware design, HDL, PLI, programming language interface, Verilog HDL, Verilog PLI, Verilog ¤ The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright © 2001 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 28 September 2001. Printed in the United States of America. Print: PDF: ISBN 0-7381-2826-0 SH94921 ISBN 0-7381-2827-9 SS94921 No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher.

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Introduction (This introduction is not part of IEEE Std 1364-2001, IEEE Standard Verilog Hardware Description Language.) ® ¤ The Verilog Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers. Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches, and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in which expressions of both variables and nets can continuously drive values onto nets, provide the basic structural construct. Procedural assignments, in which the results of calculations involving variable and net values can be stored into variables, provide the basic behavioral construct. A design consists of a set of mod- ules, each of which has an I/O interface, and a description of its function, which can be structural, behav- ioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets. The Verilog language is extensible via the Programming Language Interface (PLI) and the Verilog Proce- dural Interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to access information contained in a Verilog HDL description of the design and facilitates dynamic interaction with simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation and CAD systems, customized debugging tasks, delay calculators, and annotators. The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel Univer- sity in England under a contract to produce a test generation system for the British Ministry of Defense. HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification simulation, timing analysis, fault simulation, and test generation. In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of Direc- tors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE Working Group was formed and after 18 months of focused efforts Verilog became an IEEE standard as IEEE Std 1364-1995. After the standardization process was complete the 1364 Working Group started looking for feedback from 1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five year effort to get a much better Verilog standard in IEEE Std 1364-2001. Objective of the IEEE Std 1364-2001 effort The starting point for the IEEE 1364 Working Group for this standard was the feedback received from the IEEE Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in all aspects of the language. Users at the higher levels wanted to expand and improve the language at the RTL and behavioral levels, while users at the lower levels wanted improved capability for ASIC designs and signoff. It was for this reason that the 1364 Working Group was organized into three task forces: Behavioral, ASIC, and PLI. Copyright © 2001 IEEE. All rights reserved. iii

The clear directive from the users for these three task forces was to start by solving some of the following problems: Consolidate existing IEEE Std 1364-1995 Verilog Generate statement Multi-dimensional arrays Enhanced Verilog file I/O Re-entrant tasks Standardize Verilog configurations Enhance timing representation Enhance the VPI routines Achievements Over a period of four years the 1364 Verilog Standards Group (VSG) has produced five drafts of the LRM. The three task forces went through the IEEE Std 1364-1995 LRM very thoroughly and in the process of con- solidating the existing LRM have been able to provide nearly three hundred clarifications and errata for the Behavioral, ASIC, and PLI sections. In addition, the VSG has also been able to agree on all the enhance- ments that were requested (including the ones stated above). Three new sections have been added. Clause 13, Configuring the contents of a design, deals with configu- ration management and has been added to facilitate both the sharing of Verilog designs between designers and/or design groups and the repeatability of the exact contents of a given simulation session. Clause 15, Timing checks, has been broken out of Clause 17, System tasks and functions, and details more fully how timing checks are used in specify blocks. Clause 16, Backannotation using the Standard Delay Format (SDF), addresses using back annotation (IEEE Std 1497-1999) within IEEE Std 1364-2001. Extreme care has been taken to enhance the VPI routines to handle all the enhancements in the Behavioral and other areas of the LRM. Minimum work has been done on the PLI routines and most of the work has been concentrated on the VPI routines. Some of the enhancements in the VPI are the save and restart, simu- lation control, work area access, error handling, assign/deassign and support for array of instances, generate, and file I/O. Work on this standard would not have been possible without funding from the CAS society of the IEEE and Open Verilog International. The IEEE Std 1364-2001 Verilog Standards Group organization Many individuals from many different organizations participated directly or indirectly in the standardization process. The main body of the IEEE Std 1364-2001 working group is located in the United States, with a subgroup in Japan (EIAJ/1364HDL). The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to be approved by this group to be implemented. The three task forces focused on their specific areas and their recommendations were eventually voted on by the IEEE Std 1364-2001 working group. iv Copyright © 2001 IEEE. All rights reserved.

At the time this document was approved, the IEEE Std 1364-2001 working group had the following membership: Maqsoodul (Maq) Mannan, Chair Kasumi Hamaguchi, Chair (Japan) Vice Alec G. Stanculescu, Vice Chair (USA) Lynn A. Horobin, Secretary Yatin Trivedi, Technical Editor The Behavioral Task Force consisted of the following members: Clifford E. Cummings, Leader Kurt Baty Stefen Boyd Shalom Bresticker Tom Fitzpatrick Adam Krolnik James A. Markevitch Michael McNamara Anders Nordstrom Karen Pieper Steven Sharp Chris Spear Stuart Sutherland The ASIC Task Force consisted of the following members: Steve Wadsworth, Leader Leigh Brady Paul Colwill Tom Dewey Ted Elkind Naveen Gupta Prabhakaran Krishnamurthy Marek Ryniejski Lukasz Senator The PLI Task Force consisted of the following members: Deborah J. Dalio Charles Dawson Andrew T. Lynch, Leader Stuart Sutherland, Co-Leader and Editor Steve Meyer Girish S. Rao David Roberts The IEEE 1364 Japan subgroup (EIAJ/1364HDL) consisted of the following members: Kasumi Hamaguchi, Vice Chair (Japan) Yokozeki Atsushi Yasuaki Hatta Makoto Makino Takashima Mitsuya Tatsuro Nakamura Hiroaki Nishi Tsutomu Someya Copyright © 2001 IEEE. All rights reserved. v

The following members of the balloting committee voted on this standard: Guy Adam Shigehiro Asano Peter J. Ashenden Victor Berman J Bhasker Stefan Boyd Dennis B. Brophy Keith Chow Clifford E. Cummings Brian A. Dalio Timothy R. Davis Charles Dawson Douglas D. Dunlop Ted Elkind Joerg-Oliver Fischer-Binder Peter Flake Robert A. Flatt Masahiro Fukui Kenji Goto Naveen Gupta Andrew Guyler Yoshiaki Hagiwara Anne C. Harris Lynn A. Horobin ChiLai Huang Takahiro Ichinomiya Masato Ikeda Mitsuaki Ishikawa Neil G. Jacobson Richard O. Jones Osamu Karatsu Jake Karrfalt Masayuki Katakura Kaoru Kawamura Masamichi Kawarabayashi Satoshi Kojima Masuyoshi Kurokawa Gunther Lehmann Andrew T. Lynch Serge Maginot Maqsoodul Mannan James A. Markevitch Francoise Martinolle Yoshio Masubuchi Paul J. Menchini Hiroshi Mizuno Egbert Molenkamp John T. Montague Akira Motohara Hiroaki Nishi Anders Nordstrom Ryosuke Okuda Yoichi Onishi Uma P. Parvathy William R. Paulsen Karen L. Pieper Girish S. Rao Jaideep Roy Francesco Sforza Charles F. Shelor Chris Spear Alec G. Stanculescu Steve Start Stuart Sutherland Masahiko Toyonaga Yatin K. Trivedi Cary Ussery Steven D. Wadsworth Sui-Ki Wan Ronald Waxman John M. Williams John Willis Takashi Yamada Lun Ye Hirokazu Yonezawa Tetsuo Yutani Mark Zwolinski When the IEEE-SA Standards Board approved this standard on 17 March 2001, it had the following membership: Donald N. Heirman, Chair James T. Carlo, Vice Chair Judith Gorman, Secretary James H. Gurney Richard J. Holleman Lowell G. Johnson Robert J. Kennelly Joseph L. Koepﬁnger* Peter H. Lips L. Bruce McClung Daleep C. Mohla James W. Moore Robert F. Munzner Ronald C. Petersen Gerald H. Peterson John B. Posey Gary S. Robinson Akio Tojo Donald W. Zipse Satish K. Aggarwal Mark D. Bowman Gary R. Engmann Harold E. Epstein H. Landis Floyd Jay Forster* Howard M. Frazier Ruben D. Garzon *Member Emeritus Also included is the following nonvoting IEEE-SA Standards Board liaison: Alan Cookson, Donald R. Volzka, NIST Representative TAB Representative Andrew D. Ickowicz IEEE Standards Project Editor Verilog is a registered trademark of Cadence Design Systems, Inc. vi Copyright © 2001 IEEE. All rights reserved.

Contents 1. Overview.............................................................................................................................................. 1 1.1 Objectives of this standard........................................................................................................... 1 1.2 Conventions used in this standard................................................................................................ 1 1.3 Syntactic description.................................................................................................................... 2 1.4 Contents of this standard.............................................................................................................. 2 1.5 Header file listings ....................................................................................................................... 4 1.6 Examples...................................................................................................................................... 5 1.7 Prerequisites................................................................................................................................. 5 2. Lexical conventions ............................................................................................................................. 6 2.1 Lexical tokens .............................................................................................................................. 6 2.2 White space.................................................................................................................................. 6 2.3 Comments .................................................................................................................................... 6 2.4 Operators...................................................................................................................................... 6 2.5 Numbers....................................................................................................................................... 6 2.6 Strings ........................................................................................................................................ 10 2.7 Identifiers, keywords, and system names .................................................................................. 12 2.8 Attributes.................................................................................................................................... 14 3. Data types........................................................................................................................................... 20 3.1 Value set..................................................................................................................................... 20 3.2 Nets and variables ...................................................................................................................... 20 3.3 Vectors ....................................................................................................................................... 23 3.4 Strengths .................................................................................................................................... 24 3.5 Implicit declarations................................................................................................................... 25 3.6 Net initialization......................................................................................................................... 25 3.7 Net types .................................................................................................................................... 25 3.8 regs............................................................................................................................................. 31 3.9 Integers, reals, times, and realtimes ........................................................................................... 31 3.10 Arrays......................................................................................................................................... 33 3.11 Parameters.................................................................................................................................. 34 3.12 Name spaces............................................................................................................................... 38 4. Expressions ........................................................................................................................................ 40 4.1 Operators.................................................................................................................................... 40 4.2 Operands .................................................................................................................................... 52 4.3 Minimum, typical, and maximum delay expressions ................................................................ 57 4.4 Expression bit lengths ................................................................................................................ 59 4.5 Signed expressions..................................................................................................................... 62 5. Scheduling semantics......................................................................................................................... 64 5.1 Execution of a model ................................................................................................................. 64 5.2 Event simulation ........................................................................................................................ 64 5.3 The stratified event queue.......................................................................................................... 64 5.4 The Verilog simulation reference model ................................................................................... 65 5.5 Race conditions.......................................................................................................................... 66 Copyright © 2001 IEEE. All rights reserved. vii

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