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SH
l CIC Design Flow
l VHDL Syntax
l Synthesis Constrains
l Frequency Used Designs
l VHDL System Simulator (VSS)
l LAB Excise
VHDL: Day1
l Introduction
l CIC Design Flow
l VHDL
– Basic
– Data Types & Operators
– Structural Modeling
l Basic Concepts of VSS
VHDL: Day2
l VHDL Syntax
– Sequential Statements
– Concurrent Statements
l Design Recommendations
l Frequency Used Circuits Modeling
VHDL vs. Verilog
VHDL vs. Verilog
'
'074
425,943
-7,708
#08:,-9
#0,/,-9
,8 94 0,73 Less intuitive EA SY
Compile
Y es
Package
A D A
interpretative
N o
`include
C & A D A
VHDL vs. Verilog
l USA-IBM, TI, AT&T, INTEL…
l USA-Silicon Valley
l Europe
l Japan
l Korea
l Taiwan
VHDL Advantages
l Clear definition of design requirements
l Efficiency in design cycle time
l Flexibility in adapting to design changes
l Reuse of designs and packages
l Technology independent
l Easy analysis of various
architecture/implementations
VHDL Advantages
l Design verification and auto-regression
tests
l VHDL is recommended for government
contracts
l VHDL commercial models are available for
purchase
l VHDL is a documentation language
l VHDL is a simulation language
VHDL History
l 1980
– The USA Department of Defense (DOD)
– project under the Very High Speed Integrated
Circuit (VHSIC)
VHDL History
l 1983
– IBM, Texas Instruments and Intermetrics.
– The DOD mandated that all digital electronic
circuits be described in VHDL.
– IEEE standard 1076.
l The F22 advanced tactical fighter aircraft
F22 Raptor
l YF-23 1990/8
l 8 B YF-22 1990/9
l 92/4/24 10m high pitch too much and crash
for 2000m, can repair
l 750->648->422->339 (1 9T
l 1997/9/7
l 2000HDB
l 2013;«M
F22 Raptor
l 2 Common Integrated Processors, CIP
l KH
l 1.050 S/
l Memory 300MB
l 170T
– 88.6%FI^
– 1=^Œ
l Language ADA
F22 ADF from DID
http://www.did.com
VHDL History
l 1993
– IEEE 1076 '93.
l 1996
– Both commercial simulation and synthesis tools
became available adhering to IEEE 1076 '93
standard.
– A VHDL package for use with synthesis tools,
IEEE 1076.3.
– IEEE 1076.4 (VITAL)
VHDL History
l 1997
VHDL-AMS