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AX88772C Datasheet v120.pdf
1 Introduction
1.1 General Description
1.2 Block Diagram
1.3 Pinout Diagram
2 Signal Description
2.1 Pinout Description
2.2 Hardware Setting For Operation Mode and Multi-Function Pins
3 Function Description
3.1 USB Core and Interface
3.2 10/100M Ethernet PHY
3.3 MAC Core
3.4 Checksum Offload Engine (COE)
3.5 Operation Mode
3.6 Station Management (STA)
3.7 Memory Arbiter
3.8 USB to Ethernet Bridge
3.8.1 Ethernet/USB Frame Format Bridge
3.9 Serial EEPROM Loader
3.10 General Purpose I/O
3.11 Clock Generation
3.12 Reset Generation
3.13 Voltage Regulator
4 Serial EEPROM Memory Map
4.1 Detailed Description
4.2 Internal ROM Default Settings
4.2.1 Internal ROM Description
4.2.2 External EEPROM Description
5 USB Configuration Structure
5.1 USB Configuration
5.2 USB Interface
5.3 USB Endpoints
6 Electrical Specifications
6.1 DC Characteristics
6.1.1 Absolute Maximum Ratings
6.1.2 Recommended Operating Condition
6.1.3 Leakage Current and Capacitance
6.1.4 DC Characteristics of 3.3V I/O Pins
6.1.5 DC Characteristics of 3.3V with 5V Tolerance I/O Pins
6.1.6 DC Characteristics of Voltage Regulator
6.1.7 DC Characteristics of Fiber Interface
6.2 Thermal Characteristics
6.3 Power Consumption
6.4 Power-up Sequence
6.5 AC Timing Characteristics
6.5.1 Clock Timing
6.5.2 Reset Timing
6.5.3 Serial EEPROM Timing
6.5.4 Station Management Timing
6.5.5 RMII / Reverse-RMII Timing
6.5.6 10/100M Ethernet PHY Interface Timing
6.5.7 USB Transceiver Interface Timing
7 Package Information
7.1 AX88772C 64-pin LQFP package
8 Ordering Information
9 Revision History
APPENDIX A. Default Wake-On-LAN (WOL) Ready Mode
APPENDIX B. Ethernet PHY Power and Reset Control
Features
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Document No: AX88772C/V1.20/05/14/14
Single chip USB 2.0 to 10/100M Fast Ethernet
Support Wake-on-LAN Function
controller
Single chip USB 2.0 to RMII, support
HomePNA and HomePlug PHY
Supports Suspend Mode and Remote Wakeup
via Link-change, Magic packet, MS wakeup
frame and external wakeup pin
Single chip USB 2.0 to Reverse-RMII, supports
Supports Protocol Offload (ARP & NS) for
glueless MAC-to-MAC connections
USB Device Interface
Integrates on-chip USB 2.0 transceiver and
SIE compliant to USB Spec 1.1 and 2.0
Supports USB Full and High Speed modes
with Bus-Power or Self-Power capability
Supports 4 endpoints on USB interface
Supports AutoDetach power saving. Detach
from USB host when Ethernet cable is
unplugged
High performance packet transfer rate over
USB bus using proprietary burst transfer
mechanism (US Patent Approval)
Fast Ethernet Controller
Fast
Ethernet
10/100Mbps
Integrates
MAC/PHY
IEEE
compatible
IEEE 802.3 100BASE-FX compatible
802.3
10BASE-T/100BASE-TX
Supports twisted pair crossover detection and
auto-correction (HP Auto-MDIX)
Embedded SRAM
for RX/TX packet
buffering
Supports
IPv4/
IPv6 packet Checksum
Offload Engine(COE) to reduce CPU loading,
including IPv4 IP/TCP/UDP/ICMP/IGMP &
IPv6 TCP/UDP/ICMPv6 checksum check &
generation
Supports full duplex operation with IEEE
802.3x flow control and half duplex operation
with back-pressure flow control
Supports 2 VLAN ID filtering, received
VLAN Tag (4 bytes) can be stripped off or
preserved
PHY loop-back diagnostic capability
Supports multiple unicast MAC destination
address filter
Windows 7 Networking Power Management
Optional PHY power down during Suspend
Mode
Supports 32 MS Wakeup Patterns
Supports Wakeup packet indication
Supports Receive Filter Wakeup
Versatile External Media Interface
Optional RMII interface in MAC mode allows
AX88772C to work with HomePNA and
HomePlug PHY
Optional Reverse-RMII interface in PHY
mode allows AX88772C to support glueless
MAC-to-MAC connections
Advanced Power Management Features
Supports dynamic power management to
reduce power dissipation during idle or light
traffic
Supports very low power Wake-on-LAN
(WOL) mode when the system enters suspend
mode and waits for network events to wake it
up.
Supports 256/512 bytes (93c56/93c66) of serial
EEPROM (for storing USB Descriptors)
Supports automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM after power-on initialization
Integrates on-chip voltage regulator and only
requires a single 3.3V power supply
Single 25MHz clock input from either crystal or
oscillator source
Integrates on-chip power-on reset circuit
Small form factor with 64-pin LQFP RoHS
compliant package
Operating commercial temperature range 0°C to
70°C
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500
FAX: 886-3-579-9558
Released Date: 05/14/2014
http://www.asix.com.tw/
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
PC/Internet
Target Applications
Consumer Electronics
Figure 1
: Target Applications
Copyright © 2013-2014 ASIX Electronics Corporation. All rights reserved.
2
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Typical System Block Diagrams
Hosted by USB to operate with internal Ethernet PHY only
Figure 2
: USB 2.0 to LAN Adaptor (MAC mode)
Hosted by USB to operate with either internal Ethernet PHY or RMII (in MAC
mode)
Figure 3
: USB 2.0 to Fast Ethernet and external PHYceiver Combo (MAC mode)
Copyright © 2013-2014 ASIX Electronics Corporation. All rights reserved.
3
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Hosted by USB to operate with either internal Ethernet PHY (in MAC mode) or
Reverse-RMII (in PHY mode)
Figure 4
: Bridging Embedded MCU to USB 2.0 Host Interface (PHY mode)
Figure 5
: USB 2.0 to HomePlug Adaptor (PHY mode)
Copyright © 2013-2014 ASIX Electronics Corporation. All rights reserved.
4
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make
changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or
“NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a
design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of
their respective owners.
Copyright © 2013-2014 ASIX Electronics Corporation. All rights reserved.
5
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Table of Contents
3.8.1
1
2
3
1.1
1.2
1.3
2.1
2.2
INTRODUCTION .................................................................................................................................................... 9
GENERAL DESCRIPTION ....................................................................................................................................... 9
BLOCK DIAGRAM ................................................................................................................................................ 9
PINOUT DIAGRAM .............................................................................................................................................. 10
SIGNAL DESCRIPTION ...................................................................................................................................... 11
PINOUT DESCRIPTION ........................................................................................................................................ 11
HARDWARE SETTING FOR OPERATION MODE AND MULTI-FUNCTION PINS ...................................................... 14
FUNCTION DESCRIPTION ................................................................................................................................ 16
USB CORE AND INTERFACE .............................................................................................................................. 16
3.1
3.2
10/100M ETHERNET PHY ................................................................................................................................. 16
3.3 MAC CORE ....................................................................................................................................................... 16
3.4
CHECKSUM OFFLOAD ENGINE (COE) ................................................................................................................ 17
OPERATION MODE ............................................................................................................................................. 17
3.5
3.6
STATION MANAGEMENT (STA) ......................................................................................................................... 20
3.7 MEMORY ARBITER ............................................................................................................................................ 21
3.8
USB TO ETHERNET BRIDGE ............................................................................................................................... 22
Ethernet/USB Frame Format Bridge ........................................................................................................ 22
3.9
SERIAL EEPROM LOADER ................................................................................................................................ 22
3.10 GENERAL PURPOSE I/O ...................................................................................................................................... 22
3.11 CLOCK GENERATION ......................................................................................................................................... 23
3.12 RESET GENERATION .......................................................................................................................................... 24
3.13 VOLTAGE REGULATOR ...................................................................................................................................... 24
SERIAL EEPROM MEMORY MAP ................................................................................................................... 25
DETAILED DESCRIPTION .................................................................................................................................... 26
INTERNAL ROM DEFAULT SETTINGS ................................................................................................................ 29
Internal ROM Description ........................................................................................................................ 30
External EEPROM Description ................................................................................................................ 32
5 USB CONFIGURATION STRUCTURE ............................................................................................................. 33
USB CONFIGURATION ....................................................................................................................................... 33
USB INTERFACE ................................................................................................................................................ 33
USB ENDPOINTS ................................................................................................................................................ 33
6 ELECTRICAL SPECIFICATIONS ..................................................................................................................... 34
DC CHARACTERISTICS ...................................................................................................................................... 34
Absolute Maximum Ratings ...................................................................................................................... 34
Recommended Operating Condition ......................................................................................................... 34
Leakage Current and Capacitance ........................................................................................................... 35
DC Characteristics of 3.3V I/O Pins ........................................................................................................ 35
DC Characteristics of 3.3V with 5V Tolerance I/O Pins .......................................................................... 36
DC Characteristics of Voltage Regulator ................................................................................................. 36
DC Characteristics of Fiber Interface ...................................................................................................... 37
THERMAL CHARACTERISTICS ............................................................................................................................ 38
POWER CONSUMPTION ...................................................................................................................................... 38
POWER-UP SEQUENCE ....................................................................................................................................... 39
AC TIMING CHARACTERISTICS .......................................................................................................................... 40
Clock Timing ............................................................................................................................................. 40
Reset Timing ............................................................................................................................................. 40
Serial EEPROM Timing ............................................................................................................................ 41
Station Management Timing ..................................................................................................................... 42
RMII / Reverse-RMII Timing .................................................................................................................... 43
10/100M Ethernet PHY Interface Timing ................................................................................................. 44
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.2
6.3
6.4
6.5
5.1
5.2
5.3
6.1
4
4.1
4.2
4.2.1
4.2.2
Copyright © 2013-2014 ASIX Electronics Corporation. All rights reserved.
6
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
7
6.5.7
USB Transceiver Interface Timing ........................................................................................................... 45
PACKAGE INFORMATION ................................................................................................................................ 47
AX88772C 64-PIN LQFP PACKAGE .................................................................................................................. 47
8 ORDERING INFORMATION .............................................................................................................................. 48
7.1
9 REVISION HISTORY ........................................................................................................................................... 49
APPENDIX A. DEFAULT WAKE-ON-LAN (WOL) READY MODE .................................................................... 50
APPENDIX B. ETHERNET PHY POWER AND RESET CONTROL .................................................................... 53
Copyright © 2013-2014 ASIX Electronics Corporation. All rights reserved.
7
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
List of Figures
: TARGET APPLICATIONS ................................................................................................................................. 2
: USB 2.0 TO LAN ADAPTOR (MAC MODE) .................................................................................................... 3
: USB 2.0 TO FAST ETHERNET AND EXTERNAL PHYCEIVER COMBO (MAC MODE) ........................................ 3
: BRIDGING EMBEDDED MCU TO USB 2.0 HOST INTERFACE (PHY MODE)..................................................... 4
: USB 2.0 TO HOMEPLUG ADAPTOR (PHY MODE) .......................................................................................... 4
: BLOCK DIAGRAM .......................................................................................................................................... 9
: PINOUT DIAGRAM ........................................................................................................................................ 10
: INTERNAL DATA PATH DIAGRAM OF 10/100M ETHERNET PHY AND RMII/REVERSE-RMII INTERFACES .. 16
: RMII TO EXTERNAL PHY CHIP WITH 50MHZ OSC .................................................................................... 18
: RMII INTERFACE TO EXTERNAL PHY CHIP ............................................................................................. 18
: REVERSE-RMII TO EXTERNAL MAC DEVICE WITH 50MHZ OSC .......................................................... 19
: REVERSE-RMII INTERFACE TO EXTERNAL MAC DEVICE ....................................................................... 19
: INTERNAL CONTROL MUX OF STATION MANAGEMENT INTERFACE IN MAC MODE ............................... 20
: INTERNAL CONTROL MUX OF STATION MANAGEMENT INTERFACE IN PHY MODE ................................ 21
: ONE EXTERNAL 1M OHM RESISTOR ON 25MHZ CRYSTAL OSCILLATOR IS NECESSARY ............................ 24
: WATER LEVEL SETTING FOR FLOW CONTROL ........................................................................................... 28
: ETHERNET PHY OSCILLATOR/PLL BLOCK DIAGRAM ............................................................................. 53
: ETHERNET PHY POWER-UP & RESET TIMING DIAGRAM ......................................................................... 54
List of Tables
: PINOUT DESCRIPTION .................................................................................................................................. 13
: MFA_3 ~ MFA_0 PIN CONFIGURATION ....................................................................................................... 14
: PHY_ID DEFINITION SOURCE ..................................................................................................................... 17
: THE EXTERNAL 25MHZ CRYSTAL UNITS SPECIFICATIONS .......................................................................... 23
: SERIAL EEPROM MEMORY MAP ................................................................................................................ 25
: INTERNAL ROM MEMORY MAP .................................................................................................................. 29
: INTERNAL ROM DESCRIPTION .................................................................................................................... 30
: POWER CONSUMPTION ................................................................................................................................. 38
: REMOTE WAKEUP TRUTH TABLE ................................................................................................................ 51
FIGURE 1
FIGURE 2
FIGURE 3
FIGURE 4
FIGURE 5
FIGURE 6
FIGURE 7
FIGURE 8
FIGURE 9
FIGURE 10
FIGURE 11
FIGURE 12
FIGURE 13
FIGURE 14
FIGURE 15
FIGURE 16
FIGURE 17
FIGURE 18
TABLE 1
TABLE 2
TABLE 3
TABLE 4
TABLE 5
TABLE 6
TABLE 7
TABLE 8
TABLE 9
Copyright © 2013-2014 ASIX Electronics Corporation. All rights reserved.
8
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