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IT5570_A_V0.3.1.pdf
1. Features .
2. General Description
3. System Block Diagram
3.1 Block Diagram
3.2 EC Mapped Memory Space
3.3 Register Abbreviation
4. Pin Configuration
4.1 Top View
5. Pin Descriptions
5.1 Pin Descriptions
5.2 Chip Power Planes and Power States
5.3 Pin Power Planes and States
5.4 Reset Sources and Types
5.4.1 Related Interrupts to INTC
5.5 Chip Power Mode and Clock Domain
5.6 Pins with Pull, Schmitt-Trigger or Open-Drain Function
5.7 Pins with 1.8V Input/Output
5.8 Power Consumption Consideration
6. Host Domain Functions
6.1 The Enhanced Serial Peripheral Interface (eSPI)
6.1.1 Overview
6.1.2 Features
6.1.3 Function Description
6.1.3.1 Peripheral Channel
6.1.3.2 Flash Access Channel (MAFS)
6.1.3.3 Flash Access Channel (SAFS)
1.
2.
3.
4.
5.
6.
6.1
6.1.1
6.1.2
6.1.3
6.1.3.1
6.1.3.2
6.1.3.4 OOB Message Channel
1.
2.
3.
4.
5.
6.
6.1
6.1.1
6.1.2
6.1.3
6.1.3.1
6.1.3.2
6.1.3.3
6.1.3.5 Virtual Wires Channel
1.
2.
3.
4.
5.
6.
6.1
6.1.1
6.1.2
6.1.3
6.1.3.1
6.1.3.2
6.1.3.3
6.1.3.4
6.1.3.6 Expression of eSPI Interrupt Events
6.1.4 EC Interface Registers, eSPI slave
6.1.4
6.1.4.1 Device Identification
6.1.4.2 General Capabilities and Configurations
6.1.4.3 Channel 0 Capabilities and Configurations
6.1.4.4 Channel 1 Capabilities and Configurations
6.1.4.5 Channel 2 Capabilities and Configurations
6.1.4.6 Channel 3 Capabilities and Configurations
6.1.4.7 Channel 3 Capabilities and Configurations 2
6.1.4.8 eSPI PC Control 0 (ESPCTRL0)
6.1.4.9 eSPI PC Control 1 (ESPCTRL1)
6.1.4.10 eSPI PC Control 2 (ESPCTRL2)
6.1.4.11 eSPI PC Control 3 (ESPCTRL3)
6.1.4.12 eSPI PC Control 4 (ESPCTRL4)
6.1.4.13 eSPI PC Control 5 (ESPCTRL5)
6.1.4.14 eSPI PC Control 6 (ESPCTRL6)
6.1.4.15 eSPI PC Control 7 (ESPCTRL7)
6.1.4.16 eSPI General Control 0 (ESGCTRL0)
6.1.4.17 eSPI General Control 1 (ESGCTRL1)
6.1.4.18 eSPI General Control 2 (ESGCTRL2)
6.1.4.19 eSPI General Control 3 (ESGCTRL3)
6.1.4.20 eSPI Upstream Control 0 (ESUCTRL0)
6.1.4.21 eSPI Upstream Control 1 (ESUCTRL1)
6.1.4.22 eSPI Upstream Control 2 (ESUCTRL2)
6.1.4.23 eSPI Upstream Control 3 (ESUCTRL3)
6.1.4.24 eSPI Upstream Control 6 (ESUCTRL6)
6.1.4.25 eSPI Upstream Control 7 (ESUCTRL7)
6.1.4.26 eSPI Upstream Control 8 (ESUCTRL8)
6.1.4.27 eSPI OOB Control 0 (ESOCTRL0)
6.1.4.28 eSPI OOB Control 1 (ESOCTRL1)
6.1.4.29 eSPI OOB Control 4 (ESOCTRL4)
6.1.4.30 eSPI SAFS Control 0 (ESPISAFSC0)
6.1.4.31 eSPI SAFS Control 1 (ESPISAFSC1)
6.1.4.32 eSPI SAFS Control 2 (ESPISAFSC2)
6.1.4.33 eSPI SAFS Control 3 (ESPISAFSC3)
6.1.4.34 eSPI SAFS Control 4 (ESPISAFSC4)
6.1.4.35 eSPI SAFS Control 5 (ESPISAFSC5)
6.1.4.36 eSPI SAFS Control 6 (ESPISAFSC6)
6.1.4.37 eSPI SAFS Control 7 (ESPISAFSC7)
6.1.5 EC Interface Registers, eSPI VW
6.1.4
6.1.5
6.1.5.1 VW Index 0 (VWIDX0)
6.1.5.2 VW Index 2-7 (VWIDX2-7)
6.1.5.3 VW Index 40-47 (VWIDX40-47)
6.1.5.4 VW Contrl 0 (VWCTRL0)
6.1.5.5 VW Contrl 1 (VWCTRL1)
6.1.5.6 VW Contrl 2 (VWCTRL2)
6.1.5.7 VW Contrl 3 (VWCTRL3)
6.1.5.8 VW Contrl 5 (VWCTRL5)
6.1.5.9 VW Contrl 6 (VWCTRL6)
6.1.5.10 VW Contrl 7 (VWCTRL7)
6.1.6 EC Interface Registers, eSPI Queue 0
6.1.6
6.1.6.1 PUT_PC Data Byte 0-63 (PUTPCDB0-63)
6.1.6.2 PUT_OOB Data Byte 0-79 (PUTOOBDB0-79)
6.1.7 EC Interface Registers, eSPI Queue 1
6.1.7
6.1.7.1 Upstream Data Byte 0-79 (UDB0-79)
6.1.7.2 PUT_FLASH_NP Data Byte 0-63 (PUTFLASHNPDB0-63)
6.2 Low Pin Count Interface
6.2.1 Overview
6.2.2 Features
6.2.3 Accepted LPC Cycle Type
6.2.4 Debug Port Function
6.2.5 Serialized IRQ (SERIRQ)
6.2.6 Related Interrupts to WUC
6.2.7 LPCPD# and CLKRUN#
6.2.8 Check Items
6.3 Plug and Play Configuration (PNPCFG)
6.3.1 Logical Device Assignment
6.3.2 Super I/O Configuration Registers
6.3.2.1 Logical Device Number (LDN)
6.3.2.2 Chip ID Byte 1 (CHIPID1)
6.3.2.3 Chip ID Byte 2 (CHIPID2)
6.3.2.4 Chip Version (CHIPVER)
6.3.2.5 Super I/O Control Register (SIOCTRL)
6.3.2.6 Super I/O IRQ Configuration Register (SIOIRQ)
6.3.2.7 Super I/O General Purpose Register (SIOGP)
6.3.2.8 Super I/O Power Mode Register (SIOPWR)
6.3.2.9 Depth 2 I/O Address (D2ADR)
6.3.2.10 Depth 2 I/O Data (D2DAT)
6.3.3 Standard Logical Device Configuration Registers
6.3.3.1 Logical Device Activate Register (LDA)
6.3.3.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.3.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.3.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.3.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.3.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.3.7 Interrupt Request Type Select (IRQTP)
6.3.3.8 DMA Channel Select 0 (DMAS0)
6.3.3.9 DMA Channel Select 1 (DMAS1)
6.3.4 Serial Port 1 (UART1) Configuration Registers
6.3.4.1 Logical Device Activate Register (LDA)
6.3.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.4.7 Interrupt Request Type Select (IRQTP)
6.3.4.8 High Speed Baud Rate Select (HHS)
6.3.5 Serial Port 2 (UART2) Configuration Registers
6.3.5.1 Logical Device Activate Register (LDA)
6.3.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.5.7 Interrupt Request Type Select (IRQTP)
6.3.5.8 High Speed Baud Rate Select (HHS)
6.3.6 System Wake-Up Control (SWUC) Configuration Registers
6.3.6.1 Logical Device Activate Register (LDA)
6.3.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.6.7 Interrupt Request Type Select (IRQTP)
6.3.7 KBC / Mouse Interface Configuration Registers
6.3.7.1 Logical Device Activate Register (LDA)
6.3.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.7.7 Interrupt Request Type Select (IRQTP)
6.3.8 KBC / Keyboard Interface Configuration Registers
6.3.8.1 Logical Device Activate Register (LDA)
6.3.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.8.7 Interrupt Request Type Select (IRQTP)
6.3.9 Consumer IR Configuration Registers
6.3.9.1 Logical Device Activate Register (LDA)
6.3.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.9.4 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.9.5 Interrupt Request Type Select (IRQTP)
6.3.10 Shared Memory/Flash Interface (SMFI) Configuration Registers
6.3.10.1 Logical Device Activate Register (LDA)
6.3.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.10.7 Interrupt Request Type Select (IRQTP)
6.3.10.8 LPC Memory Window Base Address [31:24] (LPCMWBA[31:24])
6.3.10.9 LPC Memory Window Base Address [23:16] (LPCMWBA[23:16])
6.3.10.10 LPC Memory Window Mapping Region Select (LPCMWMRS)
6.3.10.11 LPC Memory Window Control Register (LPCMWCR)
6.3.10.12 Shared Memory Configuration Register (SHMC)
6.3.10.13 H2RAM-HLPC Base Address [15:12] (HLPCRAMBA[15:12])
6.3.10.14 H2RAM-HLPC Base Address [23:16] (HLPCRAMBA[23:16])
6.3.10.15 H2RAM Host Semaphore Interrupt Enable (H2RAMHSIE)
6.3.10.16 H2RAM Host Semaphore Address (H2RAMHSA)
6.3.10.17 H2RAM EC Semaphore Status (H2RAMECSS)
6.3.10.18 H2RAM-HLPC Base Address [24] (HLPCRAMBA[24])
6.3.11 RTC-like Timer Configuration Registers
6.3.11.1 Logical Device Activate Register (LDA)
6.3.11.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.11.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.11.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.11.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.11.6 I/O Port Base Address Bits [15:8] for Descriptor 2 (IOBAD2[15:8])
6.3.11.7 I/O Port Base Address Bits [7:0] for Descriptor 2 (IOBAD2[7:0])
6.3.11.8 I/O Port Base Address Bits [15:8] for Descriptor 3 (IOBAD3[15:8])
6.3.11.9 I/O Port Base Address Bits [7:0] for Descriptor 3 (IOBAD3[7:0])
6.3.11.10 I/O Port Base Address Bits [15:8] for Descriptor 4 (IOBAD4[15:8])
6.3.11.11 I/O Port Base Address Bits [7:0] for Descriptor 4 (IOBAD4[7:0])
6.3.11.12 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.11.13 Interrupt Request Type Select (IRQTP)
6.3.11.14 RAM Lock Register (RLR)
6.3.11.15 Date of Month Alarm Register Offset (DOMAO)
6.3.11.16 Month Alarm Register Offset (MONAO)
6.3.11.17 P80L Begin Index (P80LB)
6.3.11.18 P80L End Index (P80LE)
6.3.11.19 P80L Current Index (P80LC)
6.3.12 Power Management I/F Channel 1 Configuration Registers
6.3.12.1 Logical Device Activate Register (LDA)
6.3.12.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.12.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.12.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.12.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.12.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.12.7 Interrupt Request Type Select (IRQTP)
6.3.13 Power Management I/F Channel 2 Configuration Registers
6.3.13.1 Logical Device Activate Register (LDA)
6.3.13.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.13.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.13.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.13.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.13.6 I/O Port Base Address Bits [15:8] for Descriptor 2 (IOBAD2[15:8])
6.3.13.7 I/O Port Base Address Bits [7:0] for Descriptor 2 (IOBAD2[7:0])
6.3.13.8 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.13.9 Interrupt Request Type Select (IRQTP)
6.3.13.10 General Purpose Interrupt (GPINTR)
6.3.14 Power Management I/F Channel 3 Configuration Registers
6.3.14.1 Logical Device Activate Register (LDA)
6.3.14.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.14.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.14.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.14.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.14.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.14.7 Interrupt Request Type Select (IRQTP)
6.3.15 Power Management I/F Channel 4 Configuration Registers
6.3.15.1 Logical Device Activate Register (LDA)
6.3.15.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.15.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.15.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.15.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.15.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.15.7 Interrupt Request Type Select (IRQTP)
6.3.16 Power Management I/F Channel 5 Configuration Registers
6.3.16.1 Logical Device Activate Register (LDA)
6.3.16.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.16.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.16.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.16.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.16.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.16.7 Interrupt Request Type Select (IRQTP)
6.3.17 Serial Peripheral Interface (SSPI) Configuration Registers
6.3.17.1 Logical Device Activate Register (LDA)
6.3.17.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.17.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.17.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.17.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.17.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.17.7 Interrupt Request Type Select (IRQTP)
6.3.18 Platform Environment Control Interface (PECI) Configuration Registers
6.3.18.1 Logical Device Activate Register (LDA)
6.3.18.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.18.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
6.3.18.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
6.3.18.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])
6.3.18.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
6.3.18.7 Interrupt Request Type Select (IRQTP)
6.3.19 Programming Guide
6.4 Shared Memory Flash Interface Bridge (SMFI)
6.4.1 Overview
6.4.2 Features
6.4.3 Function Description
6.4.3.1 Supported Interface
6.4.3.2 Supported Flash
6.4.3.3 HLPC: Host Translation
6.4.3.4 EC-Indirect Memory Read/Write Transaction
6.4.3.5 Flash Shared between Host and EC Domains
6.4.3.6 Response to a Forbidden Access
6.4.3.7 DMA for Scratch SRAM
6.4.3.8 HLPC: Flash Programming via Host LPC Interface with Scratch SRAM
6.4.3.9 HLPC: Serial Flash Programming
6.4.3.10 Host Side to EC DLM Lower 4K RAM (H2RAM)
6.4.3.10.1 HLPC to EC DLM Lower 4K RAM (H2RAM-HLPC) through LPC Memory/FWH Cycles
6.4.3.10.2 HLPC to EC DLM Lower 4K RAM (H2RAM-HLPC) through LPC IO Cycles
6.4.3.10.3 H2RAM EC/Host Semaphore
6.4.3.11 E-flash Power-on Detection
6.4.3.11.1 16B-signature and Implicit/Explicit EC Code Base Address
6.4.3.11.2 Detection Sequence
6.4.4 EC Interface Registers
6.4.4.1 FBIU Configuration Register (FBCFG)
6.4.4.2 Flash Programming Configuration Register (FPCFG)
6.4.4.3 Shared Memory EC Control and Status Register (SMECCS)
6.4.4.4 Shared Memory Host Semaphore Register (SMHSR)
6.4.4.5 Flash Control 1 Register (FLHCTRL1R)
6.4.4.6 Flash Control 2 Register (FLHCTRL2R)
6.4.4.7 uC Control Register (UCCTRLR)
6.4.4.8 Host Control 2 Register (HCTRL2R)
6.4.4.9 EC-Indirect Memory Address Register 0 (ECINDAR0)
6.4.4.10 EC-Indirect Memory Address Register 1 (ECINDAR1)
6.4.4.11 EC-Indirect Memory Address Register 2 (ECINDAR2)
6.4.4.12 EC-Indirect Memory Address Register 3 (ECINDAR3)
6.4.4.13 EC-Indirect Memory Data Register (ECINDDR)
6.4.4.14 Scratch SRAM 0 Address Low Byte Register (SCAR0L)
6.4.4.15 Scratch SRAM 0 Address Middle Byte Register (SCAR0M)
6.4.4.16 Scratch SRAM 0 Address High Byte Register (SCAR0H)
6.4.4.17 Protect 0 Base Addr Register 0 (P0BA0R)
6.4.4.18 Protect 0 Base Addr Register 1 (P0BA1R)
6.4.4.19 Protect 0 Size Register (P0ZR)
6.4.4.20 Protect 1 Base Addr Register 0 (P1BA0R)
6.4.4.21 Protect 1 Base Addr Register 1 (P1BA1R)
6.4.4.22 Protect 1 Size Register (P1ZR)
6.4.4.23 Protect 2 Base Addr Register 0 (P2BA0R)
6.4.4.24 Protect 2 Base Addr Register 1 (P2BA1R)
6.4.4.25 Protect 2 Size Register (P2ZR)
6.4.4.26 Protect 3 Base Addr Register 0 (P3BA0R)
6.4.4.27 Protect 3 Base Addr Register 1 (P3BA1R)
6.4.4.28 Protect 3 Size Register (P3ZR)
6.4.4.29 Deferred SPI Instruction (DSINST)
6.4.4.30 Deferred SPI Address 15-12 (DSADR1)
6.4.4.31 Deferred SPI Address 23-16 (DSADR2)
6.4.4.32 Host Instruction Control 1 (HINSTC1)
6.4.4.33 Host Instruction Control 2 (HINSTC2)
6.4.4.34 Flash Control Register 3 (FLHCTRL3R)
6.4.4.35 Flash Control Register 4 (FLHCTRL4R)
6.4.4.36 Security Host View Block Mode Select [15:8] (SHVBMS[15:8])
6.4.4.37 Security Host View Block Mode Select [7:0] (SHVBMS[7:0])
6.4.4.38 Host RAM Window Control (HRAMWC)
6.4.4.39 Host RAM Window 0 Base Address (HRAMW0BA[11:4])
6.4.4.40 Host RAM Window 1 Base Address (HRAMW1BA[11:4])
6.4.4.41 Host RAM Window 0 Access Allow Size (HRAMW0AAS)
6.4.4.42 Host RAM Window 1 Access Allow Size (HRAMW1AAS)
6.4.4.43 Host RAM Window 2 Base Address (HRAMW2BA[11:4])
6.4.4.44 Host RAM Window 3 Base Address (HRAMW3BA[11:4])
6.4.4.45 Host RAM Window 2 Access Allow Size (HRAMW2AAS)
6.4.4.46 Host RAM Window 3 Access Allow Size (HRAMW3AAS)
6.4.4.47 H2RAM EC Semaphore Interrupt Enable (H2RAMECSIE)
6.4.4.48 H2RAM EC Semaphore Address (H2RAMECSA)
6.4.4.49 H2RAM Host Semaphore Status (H2RAMHSS)
6.4.4.50 Host Protect Authentication Data Register (HPADR)
6.4.4.51 Flash Control 5 Register (FLHCTRL5R)
6.4.4.52 Flash Control 6 Register (FLHCTRL6R)
6.4.4.53 Scratch SRAM SMBus Address Low Byte Register (SCARSL)
6.4.4.54 Scratch SRAM SMBus Address Middle Byte Register (SCARSM)
6.4.4.55 Scratch SRAM SMBus Address High Byte Register (SCARSH)
6.4.5 Host Interface Registers
6.4.5.1 Shared Memory Indirect Memory Address Register 0 (SMIMAR0)
6.4.5.2 Shared Memory Indirect Memory Address Register 1 (SMIMAR1)
6.4.5.3 Shared Memory Indirect Memory Address Register 2 (SMIMAR2)
6.4.5.4 Shared Memory Indirect Memory Address Register 3 (SMIMAR3)
6.4.5.5 Shared Memory Indirect Memory Data Register (SMIMDR)
6.4.5.6 Security Key Index Register (SECKIR)
6.4.5.7 Security Key Data Register (SECKDR)
6.4.5.8 Shared Memory Host Semaphore Register (SMHSR)
6.5 System Wake-Up Control (SWUC)
6.5.1 Overview
6.5.2 Features
6.5.3 Functional Description
6.5.3.1 Wake-Up Status
6.5.3.2 Wake-Up Events
6.5.3.3 Wake-Up Output Events
6.5.3.4 Other SWUC Controlled Options
6.5.4 Host Interface Registers
6.5.4.1 Wake-Up Event Status Register (WKSTR)
6.5.4.2 Wake-Up Event Enable Register (WKER)
6.5.4.3 Wake-Up Signals Monitor Register (WKSMR)
6.5.4.4 Wake-Up ACPI Status Register (WKACPIR)
6.5.4.5 Wake-Up SMI# Enable Register (WKSMIER)
6.5.4.6 Wake-Up IRQ Enable Register (WKIRQER)
6.5.5 EC Interface Registers
6.5.5.1 SWUC Control Status 1 Register (SWCTL1)
6.5.5.2 SWUC Control Status 2 Register (SWCTL2)
6.5.5.3 SWUC Control Status 3 Register (SWCTL3)
6.5.5.4 SWUC Host Configuration Base Address Low Byte Register (SWCBALR)
6.5.5.5 SWUC Host Configuration Base Address High Byte Register (SWCBAHR)
6.5.5.6 SWUC Interrupt Enable Register (SWCIER)
6.5.5.7 SWUC Host Event Status Register (SWCHSTR)
6.5.5.8 SWUC Host Event Interrupt Enable Register (SWCHIER)
6.6 Keyboard Controller (KBC)
6.6.1 Overview
6.6.2 Features
6.6.3 Functional Description
6.6.4 Host Interface Registers
6.6.4.1 KBC Data Input Register (KBDIR)
6.6.4.2 KBC Data Output Register (KBDOR)
6.6.4.3 KBC Command Register (KBCMDR)
6.6.4.4 KBC Status Register (KBSTR)
6.6.5 EC Interface Registers
6.6.5.1 KBC Host Interface Control Register (KBHICR)
6.6.5.2 KBC Interrupt Control Register (KBIRQR)
6.6.5.3 KBC Host Interface Keyboard/Mouse Status Register (KBHISR)
6.6.5.4 KBC Host Interface Keyboard Data Output Register (KBHIKDOR)
6.6.5.5 KBC Host Interface Mouse Data Output Register (KBHIMDOR)
6.6.5.6 KBC Host Interface Keyboard/Mouse Data Input Register (KBHIDIR)
6.7 Power Management Channel (PMC)
6.7.1 Overview
6.7.2 Features
6.7.3 Functional Description
6.7.3.1 General Description
6.7.3.2 Compatible Mode
6.7.3.3 Enhanced PM mode
6.7.3.4 PMC2EX
6.7.3.5 PMC3/4/5
6.7.4 Host Interface Registers
6.7.4.1 PMC Data Input Register (PMDIR)
6.7.4.2 PMC Data Output Register (PMDOR)
6.7.4.3 PMC Command Register (PMCMDR)
6.7.4.4 Status Register (PMSTR)
6.7.5 EC Interface Registers
6.7.5.1 PM Status Register (PMSTS)
6.7.5.2 PM Data Out Port (PMDO)
6.7.5.3 PM Data Out Port with SCI# (PMDOSCI)
6.7.5.4 PM Data Out Port with SMI# (PMDOSMI)
6.7.5.5 PM Data In Port (PMDI)
6.7.5.6 PM Data In Port with SCI# (PMDISCI)
6.7.5.7 PM Control (PMCTL)
6.7.5.8 PM Interrupt Control (PMIC)
6.7.5.9 PM Interrupt Enable (PMIE)
6.7.5.10 Mailbox Control (MBXCTRL)
6.7.5.11 PMC3 Status Register (PM3STS)
6.7.5.12 PMC3 Data Out Port (PM3DO)
6.7.5.13 PMC3 Data In Port (PM3DI)
6.7.5.14 PMC3 Control (PM3CTL)
6.7.5.15 PMC3 Interrupt Control (PM3IC)
6.7.5.16 PMC3 Interrupt Enable (PM3IE)
6.7.5.17 PMC4 Status Register (PM4STS)
6.7.5.18 PMC4 Data Out Port (PM4DO)
6.7.5.19 PMC4 Data In Port (PM4DI)
6.7.5.20 PMC4 Control (PM4CTL)
6.7.5.21 PMC4 Interrupt Control (PM4IC)
6.7.5.22 PMC4 Interrupt Enable (PM4IE)
6.7.5.23 PMC5 Status Register (PM5STS)
6.7.5.24 PMC5 Data Out Port (PM5DO)
6.7.5.25 PMC5 Data In Port (PM5DI)
6.7.5.26 PMC5 Control (PM5CTL)
6.7.5.27 PMC5 Interrupt Control (PM5IC)
6.7.5.28 PMC5 Interrupt Enable (PM5IE)
6.7.5.29 16-byte PMC2EX Mailbox 0-15 (MBXEC0-15)
6.8 RTC-like Timer (RTCT)
6.8.1 Overview
6.8.2 Features
6.8.3 Functional Description
6.8.3.1 Timekeeping
6.8.3.2 Update Cycles
6.8.3.3 Interrupts
6.8.4 Host Interface Registers
6.8.4.1 RTCT Bank 0 Register
6.8.4.1.1 Seconds Register (SECREG)
6.8.4.1.2 Seconds Alarm 1 Register (SECA1REG)
6.8.4.1.3 Minutes Register (MINREG)
6.8.4.1.4 Minutes Alarm 1 Register (MINA1REG)
6.8.4.1.5 Hours Register (HRREG)
6.8.4.1.6 Hours Alarm 1 Register (HRA1REG)
6.8.4.1.7 Day Of Week Register (DOWREG)
6.8.4.1.8 Date Of Month Register (DOMREG)
6.8.4.1.9 Month Register (MONREG)
6.8.4.1.10 Year Register (YRREG)
6.8.4.1.11 RTCT Control Register A (CTLREGA)
6.8.4.1.12 RTCT Control Register B (CTLREGB)
6.8.4.1.13 RTCT Control Register C (CTLREGC)
6.8.4.1.14 RTCT Control Register D (CTLREGD)
6.8.4.1.15 Date of Week Alarm 1 Register (DOWA1REG)
6.8.4.1.16 Date of Month Alarm 1 Register (DOMA1REG)
6.8.4.1.17 Month Alarm 1 Register (MONA1REG)
6.8.4.2 RTCT Bank 1 Register
6.8.4.2.1 Seconds Alarm 2 Register (SECA2REG)
6.8.4.2.2 Minutes Alarm 2 Register (MINA2REG)
6.8.4.2.3 Hours Alarm 2 Register (HRA2REG)
6.8.4.2.4 Date of Month Alarm 2 Register (DOMA2REG)
6.8.4.2.5 Month Alarm 2 Register (MONA2REG)
6.8.4.2.6 Date of Week Alarm 2 Register (DOWA2REG)
6.8.4.3 RTCT I/O Register
6.8.4.3.1 RTCT Index Register of Bank 0 (RIRB0)
6.8.4.3.2 RTCT Data Register of Bank 0 (RDRB0)
6.8.4.3.3 RTCT Index Register of Bank 1 (RIRB1)
6.8.4.3.4 RTCT Data Register of Bank 1 (RDRB1)
6.9 Consumer IR (CIR) in Host Domain
6.9.1 Overview
6.10 Serial Peripheral Interface (SSPI) in Host Domain
6.10.1 Overview
6.11 Platform Environment Control Interface (PECI) in Host Domain
6.11.1 Overview
6.12 Serial Port 1/2 (UART1/UART2) in Host Domain
6.12.1 Overview
7. EC Domain Functions
7.1 8051 Embedded Controller (EC)
7.1.1 Overview
7.1.2 Features
7.1.3 General Description
7.1.4 Idle and Doze/Deep Doze/Sleep Mode
7.1.5 EC Internal Register Description
7.1.5.1 Port 0 Register (P0R)
7.1.5.2 Stack Pointer Register (SPR)
7.1.5.3 Data Pointer Low Register (DPLR)
7.1.5.4 Data Pointer High Register (DPHR)
7.1.5.5 Data Pointer 1 Low Register (DP1LR)
7.1.5.6 Data Pointer 1 High Register (DP1HR)
7.1.5.7 Data Pointer Select Register (DPSR)
7.1.5.8 Power Control Register (PCON)
7.1.5.9 Timer Control Register (TCON)
7.1.5.10 Timer Mode Register (TMOD)
7.1.5.11 Timer 0 Low Byte Register (TL0R)
7.1.5.12 Timer 1 Low Byte Register (TL1R)
7.1.5.13 Timer 0 High Byte Register (TH0R)
7.1.5.14 Timer 1 Low Byte Register (TH1R)
7.1.5.15 Clock Control Register (CKCON)
7.1.5.16 Port 1 Register (P1R)
7.1.5.17 Serial Port Control Register (SCON)
7.1.5.18 Serial Port Buffer Register (SBUFR)
7.1.5.19 Port 2 Register (P2R)
7.1.5.20 Interrupt Enable Register (IE)
7.1.5.21 Port 3 Register (P3R)
7.1.5.22 Interrupt Priority Register (IP)
7.1.5.23 Timer 2 Control Register (T2CON)
7.1.5.24 Timer Mode Register (T2MOD)
7.1.5.25 Timer 2 Capture Low Byte Register (RCAP2LR)
7.1.5.26 Timer 2 Capture High Byte Register (RCAP2HR)
7.1.5.27 Timer 2 Low Byte Register (TL2R)
7.1.5.28 Timer 2 High Byte Register (TH2R)
7.1.5.29 Program Status Word Register (PSW)
7.1.5.30 Accumulator Register (ACC)
7.1.5.31 B Register (BR)
7.1.6 Programming Guide
7.1.6.1 Code Snippet of Entering Idle/Doze/Deep Doze/Sleep Mode
7.2 Interrupt Controller (INTC)
7.2.1 Overview
7.2.2 Features
7.2.3 Functional Description
7.2.3.1 Programmable Interrupts
7.2.4 EC Interface Registers
7.2.4.1 Interrupt Status Register 0-21 (ISR0 – ISR21)
7.2.4.2 Interrupt Enable Register 0-21 (IER0 – IER21)
7.2.4.3 Interrupt Edge/Level-Triggered Mode Register 0-21 (IELMR0 – IELMR21)
7.2.4.4 Interrupt Polarity Register 0-21 (IPOLR0 – IPOLR21)
7.2.4.5 Interrupt Vector Register (IVCT)
7.2.5 INTC Interrupt Assignments
7.2.6 Programming Guide
7.3 Wake-Up Control (WUC)
7.3.1 Overview
7.3.2 Features
7.3.3 Functional Description
7.3.4 EC Interface Registers
7.3.4.1 Wake-Up Edge Mode Register 1-14 (WUEMR1-WUEMR14)
7.3.4.2 Wake-Up Edge Sense Register 1-14 (WUESR1-WUESR14)
7.3.4.3 Wake-Up Enable Register 1/3/4 (WUENR1, WUENR3, WUENR4)
7.3.5 WUC Input Assignments
7.3.6 Programming Guide
7.4 Keyboard Matrix Scan Controller
7.4.1 Overview
7.4.2 Features
7.4.3 Functional Description
7.4.4 EC Interface Registers
7.4.4.1 Keyboard Scan Out Low Byte Data Register (KSOL)
7.4.4.2 Keyboard Scan Out High Byte Data 1 Register (KSOH1)
7.4.4.3 Keyboard Scan Out Control Register (KSOCTRL)
7.4.4.4 Keyboard Scan Out High Byte Data 2 Register (KSOH2)
7.4.4.5 Keyboard Scan In Data Register (KSIR)
7.4.4.6 Keyboard Scan In Control Register (KSICTRLR)
7.4.4.7 Keyboard Scan In [7:0] GPIO Control Register (KSIGCTRLR)
7.4.4.8 Keyboard Scan In [7:0] GPIO Output Enable Register (KSIGOENR)
7.4.4.9 Keyboard Scan In [7:0] GPIO Data Register (KSIGDATR)
7.4.4.10 Keyboard Scan In [7:0] GPIO Data Mirror Register (KSIGDMRRR)
7.4.4.11 Keyboard Scan Out [15:8] GPIO Control Register (KSOHGCTRLR)
7.4.4.12 Keyboard Scan Out [15:8] GPIO Output Enable Register (KSOHGOENR)
7.4.4.13 Keyboard Scan Out [15:8] GPIO Data Mirror Register (KSOHGDMRRR)
7.4.4.14 Keyboard Scan Out [7:0] GPIO Control Register (KSOLGCTRLR)
7.4.4.15 Keyboard Scan Out [7:0] GPIO Output Enable Register (KSOLGOENR)
7.4.4.16 Keyboard Scan Out [7:0] GPIO Data Mirror Register (KSOLGDMRRR)
7.4.4.17 KSO0 Low Scan Data Register (KSO0LSDR)
7.4.4.18 KSO1 Low Scan Data Register (KSO1LSDR)
7.4.4.19 KSO2 Low Scan Data Register (KSO2LSDR)
7.4.4.20 KSO3 Low Scan Data Register (KSO3LSDR)
7.4.4.21 KSO4 Low Scan Data Register (KSO4LSDR)
7.4.4.22 KSO5 Low Scan Data Register (KSO5LSDR)
7.4.4.23 KSO6 Low Scan Data Register (KSO6LSDR)
7.4.4.24 KSO7 Low Scan Data Register (KSO7LSDR)
7.4.4.25 KSO8 Low Scan Data Register (KSO8LSDR)
7.4.4.26 KSO9 Low Scan Data Register (KSO9LSDR)
7.4.4.27 KSO10 Low Scan Data Register (KSO10LSDR)
7.4.4.28 KSO11 Low Scan Data Register (KSO11LSDR)
7.4.4.29 KSO12 Low Scan Data Register (KSO12LSDR)
7.4.4.30 KSO13 Low Scan Data Register (KSO13LSDR)
7.4.4.31 KSO14 Low Scan Data Register (KSO14LSDR)
7.4.4.32 KSO15 Low Scan Data Register (KSO15LSDR)
7.4.4.33 KSO16 Low Scan Data Register (KSO16LSDR)
7.4.4.34 KSO17 Low Scan Data Register (KSO17LSDR)
7.4.4.35 Scan Data Control1 Register (SDC1R)
7.4.4.36 Scan Data Control2 Register (SDC2R)
7.4.4.37 Scan Data Control3 Register (SDC3R)
7.4.4.38 Scan Data Status Register (SDSR)
7.5 General Purpose I/O Port (GPIO)
7.5.1 Overview
7.5.2 Features
7.5.3 EC Interface Registers
7.5.3.1 General Control Register (GCR)
7.5.3.2 General Control 1 Register (GCR1)
7.5.3.3 General Control 2 Register (GCR2)
7.5.3.4 General Control 3 Register (GCR3)
7.5.3.5 General Control 4 Register (GCR4)
7.5.3.6 General Control 5 Register (GCR5)
7.5.3.7 General Control 6 Register (GCR6)
7.5.3.8 General Control 7 Register (GCR7)
7.5.3.9 General Control 8 Register (GCR8)
7.5.3.10 General Control 9 Register (GCR9)
7.5.3.11 General Control 10 Register (GCR10)
7.5.3.12 General Control 11 Register (GCR11)
7.5.3.13 General Control 12 Register (GCR12)
7.5.3.14 General Control 13 Register (GCR13)
7.5.3.15 General Control 14 Register (GCR14)
7.5.3.16 General Control 15 Register (GCR15)
7.5.3.17 General Control 16 Register (GCR16)
7.5.3.18 General Control 17 Register (GCR17)
7.5.3.19 General Control 18 Register (GCR18)
7.5.3.20 General Control 19 Register (GCR19)
7.5.3.21 General Control 20 Register (GCR20)
7.5.3.22 General Control 21 Register (GCR21)
7.5.3.23 General Control 22 Register (GCR22)
7.5.3.24 General Control 23 Register (GCR23)
7.5.3.25 Power Good Watch Control Register (PGWCR)
7.5.3.26 Port Data Registers A-J,M (GPDRA-J,M)
7.5.3.27 Port Data Mirror Registers A-J,M (GPDMRA-J,M)
7.5.3.28 Port Control n Registers (GPCRn, n = A0-M6)
7.5.3.29 Output Type Registers A/B/D/E/F/H/J (GPOT A/B/D/E/F/H/J)
7.5.4 Alternate Function Selection
7.5.5 Programming Guide
7.6 EC Clock and Power Management Controller (ECPM)
7.6.1 Overview
7.6.2 Features
7.6.3 EC Interface Registers
7.6.3.1 Clock Gating Control 1 Register (CGCTRL1R)
7.6.3.2 Clock Gating Control 2 Register (CGCTRL2R)
7.6.3.3 Clock Gating Control 3 Register (CGCTRL3R)
7.6.3.4 PLL Control (PLLCTRL)
7.6.3.5 Auto Clock Gating (AUTOCG)
7.6.3.6 PLL Frequency (PLLFREQR)
7.6.3.7 Clock Gating Control 4 Register (CGCTRL4R)
7.7 SMBus Interface (SMB)
7.7.1 Overview
7.7.2 Features
7.7.3 Functional Description
7.7.3.1 SMBus Master Interface
7.7.3.2 SMBus Slave Interface
7.7.3.3 SMBus Porting Guide
7.7.3.4 SMBus Master Programming Guide
7.7.3.5 Description of SMCLK and SMDAT Line Control in Software Mode
7.7.3.6 Description of SMBus Master and Slave Interface Select
7.7.3.7 SMBus Waveform
7.7.3.8 Expression of SMBus Interrupt Events
7.7.4 EC Interface Registers
7.7.4.1 Host Status Register (HOSTA)
7.7.4.2 Host Control Register (HOCTL)
7.7.4.3 Host Command Register (HOCMD)
7.7.4.4 Transmit Slave Address Register (TRASLA)
7.7.4.5 Data 0 Register (D0REG)
7.7.4.6 Data 1 Register (D1REG)
7.7.4.7 Host Block Data Byte Register (HOBDB)
7.7.4.8 Master PIO Packet Error Check Register (PECERC)
7.7.4.9 Receive Slave Address Register (RESLADR)
7.7.4.10 Receive Slave Address Register 2 (RESLADR2)
7.7.4.11 Slave Data Register (SLDA)
7.7.4.12 SMBus Pin Control Register (SMBPCTL)
7.7.4.13 Slave Status Register (SLSTA)
7.7.4.14 Slave Interrupt Control Register (SICR)
7.7.4.15 Notify Device Address Register (NDADR)
7.7.4.16 Notify Data Low Byte Register (NDLB)
7.7.4.17 Notify Data High Byte Register (NDHB)
7.7.4.18 Host Control Register 2 (HOCTL2)
7.7.4.19 4.7 (s Low Register (4P7USL)
7.7.4.20 4.0 (s Low Register (4P0USL)
7.7.4.21 250 ns Register (250NSREG)
7.7.4.22 25 ms Register (25MSREG)
7.7.4.23 45.3 (s Low Register (45P3USLREG)
7.7.4.24 45.3 (s High Register (45P3USHREG)
7.7.4.25 4.7 (s And 4.0 (s High Register (4p7A4P0H)
7.7.4.26 Slave Bridge Control Register (SLVISELR)
7.7.4.27 SMCLK Timing Setting Register A (SCLKTS_A)
7.7.4.28 SMCLK Timing Setting Register B (SCLKTS_B)
7.7.4.29 SMCLK Timing Setting Register C (SCLKTS_C)
7.7.4.30 SMCLK Timing Setting Register D (SCLKTS_D)
7.7.4.31 Master FIFO Control 1 Register (MSTFCTRL1)
7.7.4.32 Master FIFO Status 1 Register (MSTFSTS1)
7.7.4.33 Master FIFO Control 2 Register (MSTFCTRL2)
7.7.4.34 Master FIFO Status 2 Register (MSTFSTS2)
7.7.4.35 Host Nack Source (HONACKSRC)
7.7.4.36 Slave Dedicated FIFO Threshold (SLVFTH)
7.7.4.37 DMA from Flash to SMB Dedicated FIFO Selection (DFTSDFSEL)
7.7.4.38 Master Dedicated FIFO Threshold (MSTFTH)
7.7.4.39 Master Dedicated FIFO Threshold Enable (MFTHEN)
7.7.4.40 Master Dedicated FIFO Threshold Interrupt Status (MFTISTA)
7.7.4.41 Slave Dedicated FIFO Threshold Enable (SFTHEN)
7.7.4.42 Slave Dedicated FIFO Threshold Interrupt Status (SFTISTA)
7.7.4.43 Slave A Dedicated FIFO Pre-defined Control Register (SADFPCTL)
7.7.4.44 Slave A Dedicated FIFO Status (SFFSTA)
7.7.4.45 SMBus Design Switch Interface Control (SDSIC)
7.7.4.46 SMBus Design Switch Interface Control 2 (SDSIC2)
7.7.4.47 Slave B Dedicated FIFO Pre-defined Control Register (SBDFPCTL)
7.7.4.48 Slave B Dedicated FIFO Status (SBDFFSTA)
7.7.4.49 Slave C Dedicated FIFO Control Register (SCDFFCTL)
7.7.4.50 Slave C Dedicated FIFO Status (SCDFFSTA)
7.7.4.51 I2C Wr to Rd FIFO Register (I2CW2RF)
7.7.4.52 I2C Wr to Rd FIFO Interrupt Status (IWRFISTA)
7.7.4.53 Shared FIFO Function Enable (SFFE)
7.7.4.54 Master Shared FIFO Size Select (MSFSS)
7.7.4.55 Slave Shared FIFO Size Select1 (SSFSS1)
7.7.4.56 Shared FIFO Base Address for Master A (SFBAMA)
7.7.4.57 Shared FIFO Base Address for Master BCD (SFBAMBCD)
7.7.4.58 Shared FIFO Base Address for Slave A (SFBASA)
7.7.4.59 Shared FIFO Base Address for Slave B (SFBASB)
7.7.4.60 Shared FIFO Base Address for Slave C (SFBASC)
7.7.4.61 Slave Shared FIFO Size Select2 (SSFSS2)
7.7.4.62 Hardwired PEC Register (HWPEC)
7.7.4.63 Hardwired PEC Error Status (HWPES)
7.7.4.64 Slave Transaction PEC Control Register (SLVTPECC)
7.7.4.65 Slave Hardwired PEC VALUE (SHWPECV)
7.7.4.66 Bridge Timeout Interrupt Enable Register (BTOIER)
7.7.4.67 I2C Shared FIFO Byte Count H (ISFBCH)
7.7.4.68 SMBus Interface Switch Pin control (SISPC)
7.7.4.69 SMBus Design Switch Interface Control 3(SDSIC3)
7.7.4.70 Master Dedicated FIFO Threshold Enable 2 (MFTHEN2)
7.7.4.71 Master Dedicated FIFO Threshold Interrupt Status 2 (MFTISTA2)
7.7.4.72 Hardwired PEC Register 2 (HWPEC2)
7.7.4.73 Hardwired PEC Error Status 2 (HWPES2)
7.7.4.74 SMCLK Timing Setting Register E (SCLKTS_E)
7.7.4.75 SMCLK Timing Setting Register F (SCLKTS_F)
7.8 Platform Environment Control Interface (PECI)
7.8.1 Overview
7.8.2 Features
7.8.3 Functional Description
7.8.3.1 PECI Porting Guide
7.8.3.2 PECI Programming Guide
7.8.4 Host Interface Registers
7.8.5 EC Interface Registers
7.8.5.1 Host Status Register (HOSTAR)
7.8.5.2 Host Control Register (HOCTLR)
7.8.5.3 Host Command (Write Data 1) Register (HOCMDR)
7.8.5.4 Host Target Address Register (HOTRADDR)
7.8.5.5 Host Write Length Register (HOWRLR)
7.8.5.6 Host Read Length Register (HORDLR)
7.8.5.7 Host Write Data (2-16) Register (HOWRDR)
7.8.5.8 Host Read Data (1-16) Register (HORDDR)
7.8.5.9 Host Control 2 Register (HOCTL2R)
7.8.5.10 Pad Control Register (PADCTLR)
7.8.5.11 Received Write FCS Value (RWFCSV)
7.8.5.12 Received Read FCS Value (RRFCSV)
7.8.5.13 Write FCS Value (WFCSV)
7.8.5.14 Read FCS Value (RFCSV)
7.8.5.15 Assured Write FCS Value (AWFCSV)
7.9 PS/2 Interface
7.9.1 Overview
7.9.2 Features
7.9.3 Functional Description
7.9.3.1 Hardware Mode Selected
7.9.3.2 Software Mode Selected
7.9.4 EC Interface Registers
7.9.4.1 PS/2 Control Register 1/3 (PSCTL1/3)
7.9.4.2 PS/2 Interrupt Control Register 1/3 (PSINT1/3)
7.9.4.3 PS/2 Status Register 1/3 (PSSTS1/3)
7.9.4.4 PS/2 Data Register 1/3 (PSDAT1/3)
7.10 Digital to Analog Converter (DAC)
7.10.1 Overview
7.10.2 Feature
7.10.3 Functional Description
7.10.4 EC Interface Registers
7.10.4.1 DAC Power Down Register (DACPDREG)
7.10.4.2 DAC Data Channel 2~5 Register (DACDAT2~5)
7.11 Analog to Digital Converter (ADC)
7.11.1 Overview
7.11.2 Features
7.11.3 Functional Description
7.11.3.1 ADC General Description
7.11.3.2 Voltage Measurement and Automatic Hardware Calibration
7.11.3.3 ADC Operation
7.11.4 EC Interface Registers
7.11.4.1 ADC Status Register (ADCSTS)
7.11.4.2 ADC Configuration Register (ADCCFG)
7.11.4.3 ADC Clock Control Register (ADCCTL)
7.11.4.4 ADC General Control Register (ADCGCR)
7.11.4.5 Voltage Channel 0 Control Register (VCH0CTL)
7.11.4.6 Calibration Data Control Register (KDCTL)
7.11.4.7 Voltage Channel 1 Control Register (VCH1CTL)
7.11.4.8 Voltage Channel 1 Data Buffer LSB (VCH1DATL)
7.11.4.9 Voltage Channel 1 Data Buffer MSB (VCH1DATM)
7.11.4.10 Voltage Channel 2 Control Register (VCH2CTL)
7.11.4.11 Voltage Channel 2 Data Buffer LSB (VCH2DATL)
7.11.4.12 Voltage Channel 2 Data Buffer MSB (VCH2DATM)
7.11.4.13 Voltage Channel 3 Control Register (VCH3CTL)
7.11.4.14 Voltage Channel 3 Data Buffer LSB (VCH3DATL)
7.11.4.15 Voltage Channel 3 Data Buffer MSB (VCH3DATM)
7.11.4.16 Voltage Channel 0 Data Buffer LSB (VCH0DATL)
7.11.4.17 Voltage Channel 0 Data Buffer MSB (VCH0DATM)
7.11.4.18 Voltage Comparator Scan Period (VCMPSCP)
7.11.4.19 Voltage Channel 4 Control Register (VCH4CTL)
7.11.4.20 Voltage Channel 4 Data Buffer MSB (VCH4DATM)
7.11.4.21 Voltage Channel 4 Data Buffer LSB (VCH4DATL)
7.11.4.22 Voltage Channel 5 Control Register (VCH5CTL)
7.11.4.23 Voltage Channel 5 Data Buffer MSB (VCH5DATM)
7.11.4.24 Voltage Channel 5 Data Buffer LSB (VCH5DATL)
7.11.4.25 Voltage Channel 6 Control Register (VCH6CTL)
7.11.4.26 Voltage Channel 6 Data Buffer MSB (VCH6DATM)
7.11.4.27 Voltage Channel 6 Data Buffer LSB (VCH6DATL)
7.11.4.28 Voltage Channel 7 Control Register (VCH7CTL)
7.11.4.29 Voltage Channel 7 Data Buffer MSB (VCH7DATM)
7.11.4.30 Voltage Channel 7 Data Buffer LSB (VCH7DATL)
7.11.4.31 ADC Data Valid Status (ADCDVSTS)
7.11.4.32 Voltage Comparator Status (VCMPSTS)
7.11.4.33 Voltage Comparator 0 Control Register (VCMP0CTL)
7.11.4.34 Voltage Comparator 0 Threshold Data Buffer MSB (VCMP0THRDATM)
7.11.4.35 Voltage Comparator 0 Threshold Data Buffer LSB (VCMP0THRDATL)
7.11.4.36 Voltage Comparator 1 Control Register (VCMP1CTL)
7.11.4.37 Voltage Comparator 1 Threshold Data Buffer MSB (VCMP1THRDATM)
7.11.4.38 Voltage Comparator 1 Threshold Data Buffer LSB (VCMP1THRDATL)
7.11.4.39 Voltage Comparator 2 Control Register (VCMP2CTL)
7.11.4.40 Voltage Comparator 2 Threshold Data Buffer MSB (VCMP2THRDATM)
7.11.4.41 Voltage Comparator 2 Threshold Data Buffer LSB (VCMP2THRDATL)
7.11.4.42 Voltage Comparator Output Type Register (VCMPOTR)
7.11.4.43 Voltage Comparator 0 Hysteresis Data Buffer MSB (VCMP0HYDATM)
7.11.4.44 Voltage Comparator 0 Hysteresis Data Buffer LSB (VCMP0HYDATL)
7.11.4.45 Voltage Comparator Lock Register (VCMPLR)
7.11.4.46 ADC Input Voltage Mapping Full-Scale Code Selection 1 (ADCIVMFSCS1)
7.11.4.47 ADC Input Voltage Mapping Full-Scale Code Selection 2 (ADCIVMFSCS2)
7.11.5 ADC Programming Guide
7.11.6 Voltage Comparator Programming Guide
7.12 PWM .
7.12.1 Overview
7.12.2 Features
7.12.3 Functional Description
7.12.3.1 General Description
7.12.3.2 Manual Fan Control Mode
7.12.3.3 PWM Dimming Mode
7.12.4 EC Interface Registers
7.12.4.1 Channel 0 Clock Prescaler Register (C0CPRS)
7.12.4.2 Cycle Time Register 0 (CTR0)
7.12.4.3 Cycle Time Register 1 (CTR1)
7.12.4.4 Cycle Time Register 1 MSB (CTR1M)
7.12.4.5 Cycle Time Register 2 (CTR2)
7.12.4.6 Cycle Time Register 3 (CTR3)
7.12.4.7 PWM Duty Cycle Register 0 to 7(DCRi)
7.12.4.8 PWM Duty Cycle Register 2 MSB (DCR2M)
7.12.4.9 PWM Duty Cycle Register 3 MSB (DCR3M)
7.12.4.10 PWM Polarity Register (PWMPOL)
7.12.4.11 Prescaler Clock Frequency Select Register (PCFSR)
7.12.4.12 Prescaler Clock Source Select Group Low (PCSSGL)
7.12.4.13 Prescaler Clock Source Select Group High (PCSSGH)
7.12.4.14 Prescaler Clock Source Gating Register (PCSGR)
7.12.4.15 Fan 1 Tachometer LSB Reading Register (F1TLRR)
7.12.4.16 Fan 1 Tachometer MSB Reading Register (F1TMRR)
7.12.4.17 Fan 2 Tachometer LSB Reading Register (F2TLRR)
7.12.4.18 Fan 2 Tachometer MSB Reading Register (F2TMRR)
7.12.4.19 Zone Interrupt Status Control Register (ZINTSCR)
7.12.4.20 PWM Clock Control Register (ZTIER)
7.12.4.21 Channel 4 Clock Prescaler Register (C4CPRS)
7.12.4.22 Channel 4 Clock Prescaler MSB Register (C4MCPRS)
7.12.4.23 Channel 6 Clock Prescaler Register (C6CPRS)
7.12.4.24 Channel 6 Clock Prescaler MSB Register (C6MCPRS)
7.12.4.25 Channel 7 Clock Prescaler Register (C7CPRS)
7.12.4.26 Channel 7 Clock Prescaler MSB Register (C7MCPRS)
7.12.4.27 PWM Clock 6MHz Select Register (CLK6MSEL)
7.12.4.28 PWM5 Timeout Control Register (PWM5TOCTRL)
7.12.4.29 Fan 3 Tachometer LSB Reading (F3TLRR)
7.12.4.30 Fan 3 Tachometer MSB Reading (F3TMRR)
7.12.4.31 Tachometer Switch Control Register 2 (TSWCTLR2)
7.12.4.32 Tachometer Switch Control Register (TSWCTLR)
7.12.4.33 PWM Output Open-Drain Enable Register (PWMODENR)
7.12.4.34 Backlight Duty Register (BLDR)
7.12.4.35 PWM0 LED Dimming Enable (PWM0LHE)
7.12.4.36 PWM0 LED Dimming Control Register 1 (PWM0LCR1)
7.12.4.37 PWM0 LED Dimming Control Register 2 (PWM0LCR2)
7.12.4.38 PWM1 LED Dimming Enable (PWM1LHE)
7.12.4.39 PWM1 LED Dimming Control Register 1 (PWM1LCR1)
7.12.4.40 PWM1 LED Dimming Control Register 2 (PWM1LCR2)
7.12.4.41 PWM Load Counter Control Register (PWMLCCR)
7.12.5 PWM Programming Guide
7.13 8-bit Timer (TMR)
7.13.1 Overview
7.13.2 Features
7.13.3 Functional Description
7.13.3.1 General Description
7.13.3.2 TMR Counter (CNT)
7.13.3.3 TMR Duty Cycle (DCR)
7.13.3.4 TMR Cycle Time (CTR)
7.13.3.5 TMR Mode
7.13.3.6 TMR Interrupt
7.13.4 EC Interface Registers
7.13.4.1 TMR Prescaler Register (PRSC)
7.13.4.2 Group Clock Source and Mode Select Register (GCSMS)
7.13.4.3 A0 Cycle Time Register (CTR_A0)
7.13.4.4 A1 Cycle Time Register (CTR_A1)
7.13.4.5 B0 Cycle Time Register (CTR_B0)
7.13.4.6 B1 Cycle Time Register (CTR_B1)
7.13.4.7 A0 Duty Cycle Register (DCR_A0)
7.13.4.8 A1 Duty Cycle Register (DCR_A1)
7.13.4.9 B0 Duty Cycle Register (DCR_B0)
7.13.4.10 B1 Duty Cycle Register (DCR_B1)
7.13.4.11 Channel Clock Group Select Register (CCGSR)
7.13.4.12 TMR Clock Enable Register (TMRCE)
7.13.4.13 TMR Interrupt Enable Register (TMRIE)
7.13.5 TMR Programming Guide
7.14 Consumer Electronics Control (CEC)
7.14.1 Overview
7.14.1.1 General Description
7.14.1.2 CEC TX Flow
7.14.1.3 CEC RX Flow
7.14.2 EC Interface Registers
7.14.2.1 CEC Data Register (CECDR)
7.14.2.2 CEC FIFO Status Register (CECFSTS)
7.14.2.3 CEC Device Logical Address Register (CECDLA)
7.14.2.4 CEC Control Register (CECCTRL)
7.14.2.5 CEC Status Register (CECSTS)
7.14.2.6 CEC Interrupt Enable Register (CECIE)
7.14.2.7 CEC Operation Status Register (CECOPSTS)
7.14.2.8 CEC Received Header Register (CECRH)
7.15 EC Access to the Host Controlled Modules (EC2I Bridge)
7.15.1 Overview
7.15.2 Features
7.15.3 Functional Description
7.15.4 EC Interface Registers
7.15.4.1 Indirect Host I/O Address Register (IHIOA)
7.15.4.2 Indirect Host Data Register (IHD)
7.15.4.3 EC to I-Bus Modules Access Enable Register (IBMAE)
7.15.4.4 I-Bus Control Register (IBCTL)
7.15.5 EC2I Programming Guide
7.16 External Timer and External Watchdog (ETWD)
7.16.1 Overview
7.16.2 Features
7.16.3 Functional Description
7.16.3.1 External Timer Operation
7.16.3.2 External WDT Operation
7.16.4 EC Interface Registers
7.16.4.1 External Timer 1/WDT Configuration Register (ETWCFG)
7.16.4.2 External Timer 1 Prescaler Register (ET1PSR)
7.16.4.3 External Timer 1 Counter High Byte (ET1CNTLHR)
7.16.4.4 External Timer 1 Counter Low Byte (ET1CNTLLR)
7.16.4.5 External Timer 2 Prescaler Register (ET2PSR)
7.16.4.6 External Timer 2 Counter High Byte (ET2CNTLHR)
7.16.4.7 External Timer 2 Counter Low Byte (ET2CNTLLR)
7.16.4.8 External Timer 2 Counter High Byte 2 (ET2CNTLH2R)
7.16.4.9 External Timer 3 Prescaler Register (ET3PSR)
7.16.4.10 External Timer 3 Counter High Byte (ET3CNTLHR)
7.16.4.11 External Timer 3 Counter Low Byte (ET3CNTLLR)
7.16.4.12 External Timer 3 Counter High Byte 2 (ET3CNTLH2R)
7.16.4.13 External Timer/WDT Control Register (ETWCTRL)
7.16.4.14 External WDT Counter High Byte (EWDCNTLHR)
7.16.4.15 External WDT Counter Low Byte (EWDCNTLLR)
7.16.4.16 External WDT Key Register (EWDKEYR)
7.17 General Control (GCTRL)
7.17.1 Overview
7.17.2 Features
7.17.3 Functional Description
7.17.4 EC Interface Registers
7.17.4.1 Chip ID Byte 1 (ECHIPID1)
7.17.4.2 Chip ID Byte 2 (ECHIPID2)
7.17.4.3 Chip Version (ECHIPVER)
7.17.4.4 Identify Input Register (IDR)
7.17.4.5 Reset Status (RSTS)
7.17.4.6 Reset Control 1 (RSTC1)
7.17.4.7 Reset Control 2 (RSTC2)
7.17.4.8 Reset Control 3 (RSTC3)
7.17.4.9 Reset Control 4 (RSTC4)
7.17.4.10 Reset Control DMM (RSTDMMC)
7.17.4.11 Reset Control 6 (RSTC6)
7.17.4.12 Base Address Select (BADRSEL)
7.17.4.13 Wait Next Clock Rising (WNCKR)
7.17.4.14 Special Control 5 (SPCTRL5)
7.17.4.15 Special Control 1 (SPCTRL1)
7.17.4.16 Reset Control Host Side (RSTCH)
7.17.4.17 Generate IRQ (GENIRQ)
7.17.4.18 Special Control 2 (SPCTRL2)
7.17.4.19 Special Control 3 (SPCTRL3)
7.17.4.20 Special Control 4 (SPCTRL4)
7.17.4.21 Port I2EC High-Byte Register (PI2ECH)
7.17.4.22 Port I2EC Low-Byte Register (PI2ECL)
7.17.4.23 BRAM Interrupt Address 0 Register (BINTADDR0R)
7.17.4.24 BRAM Interrupt Address 1 Register (BINTADDR1R)
7.17.4.25 BRAM Interrupt Control Register (BINTCTRLR)
7.17.4.26 Port 80h/81h Status Register (P80H81HSR)
7.17.4.27 Port 80h Data Register (P80HDR)
7.17.4.28 Port 81h Data Register (P81HDR)
7.18 External GPIO Controller (EGPC)
7.18.1 Overview
7.18.2 Features
7.18.3 Functional Description
7.18.4 EC Interface Registers
7.18.4.1 External GPIO Address Register (EADDR)
7.18.4.2 External GPIO Data Register (EDAT)
7.18.4.3 External GPIO Control Register (ECNT)
7.18.4.4 External GPIO Status Register (ESTS)
7.18.4.5 External GPIO Auto Read Control Register (EARCR)
7.18.4.6 External GPIO Read Enable 1 Register (ERE1R)
7.18.4.7 External GPIO Read Enable 2 Register (ERE2R)
7.18.4.8 External GPIO Read Enable 3 Register (ERE3R)
7.18.4.9 External GPIO Read Enable 4 Register (ERE4R)
7.18.4.10 External GPIO Read Enable 5 Register (ERE5R)
7.18.4.11 External GPIO Status Vector Register (ESVR)
7.18.4.12 External GPIO Status Change Flag 1 Register (ESCF1R)
7.18.4.13 External GPIO Status Change Flag 2 Register (ESCF2R)
7.18.4.14 External GPIO Status Change Flag 3 Register (ESCF3R)
7.18.4.15 External GPIO Status Change Flag 4 Register (ESCF4R)
7.18.4.16 External GPIO Status Change Flag 5 Register (ESCF5R)
7.19 BRAM .
7.19.1 Overview
7.19.2 Features
7.19.3 Functional Description
7.19.3.1 P80L
7.19.4 Host Interface Registers
7.19.5 EC Interface Registers
7.19.5.1 SRAM Byte n Registers (SBTn, n= 0-191)
7.20 Consumer IR (CIR)
7.20.1 Overview
7.20.2 Features
7.20.3 Functional Description
7.20.3.1 Transmit Operation
7.20.3.2 Receive Operation
7.20.3.3 Wakeup (Power On) Controller Programming Sequence
7.20.4 Host Interface Registers
7.20.5 EC Interface Registers
7.20.5.1 CIR Data Register (C0DR)
7.20.5.2 CIR Master Control Register (C0MSTCR)
7.20.5.3 CIR Interrupt Enable Register (C0IER)
7.20.5.4 CIR Interrupt Identification Register (C0IIR)
7.20.5.5 CIR Carrier Frequency Register (C0CFR)
7.20.5.6 CIR Receiver Control Register (C0RCR)
7.20.5.7 CIR Transmitter Control Register (C0TCR)
7.20.5.8 CIR Slow Clock Control Register (C0SCK)
7.20.5.9 CIR Baud Rate Divisor Low Byte Register (C0BDLR)
7.20.5.10 CIR Baud Rate Divisor High Byte Register (C0BDHR)
7.20.5.11 CIR Transmitter FIFO Status Register (C0TFSR)
7.20.5.12 CIR Receiver FIFO Status Register (C0RFSR)
7.20.5.13 CIR Wake-Code Set Select Register (C0WCSSR)
7.20.5.14 CIR Wakeup Code Length Register (C0WCL)
7.20.5.15 CIR Wakeup Code Read/Write Register (C0WCR)
7.20.5.16 CIR Wakeup Power Control/Status Register (C0WPS)
7.20.5.17 CIR Scratch Register (CSCRR)
7.20.5.18 CIR General Purpose Interrupt (CGPINTR)
7.21 Serial Peripheral Interface (SSPI)
7.21.1 Overview
7.21.2 Features
7.21.3 Functional Description
7.21.3.1 Data Transmissions
7.21.3.2 SPI Mode
7.21.3.3 Blocking and Non-blocking mode
7.21.4 Host Interface Registers
7.21.5 EC Interface Registers
7.21.5.1 SPI Data Register (SPIDATA)
7.21.5.2 SPI Control Register 1 (SPICTRL1)
7.21.5.3 SPI Control Register 2 (SPICTRL2)
7.21.5.4 SPI Start and End Status Register (SPISTS)
7.21.5.5 SPI Control Register 3 (SPICTRL3)
7.21.6 Programming Guide
7.22 Serial Port (UART)
7.22.1 Overview
7.22.2 Features
7.22.3 Functional Description
7.22.4 Host Interface Registers
7.22.5 EC Interface Registers
7.22.5.1 Receiver Buffer Register (RBR)
7.22.5.2 Transmitter Holding Register (THR)
7.22.5.3 Interrupt Enable Register (IER)
7.22.5.4 Interrupt Identification Register (IIR)
7.22.5.5 FIFO Control Register (FCR)
7.22.5.6 Divisor Latch LSB (DLL)
7.22.5.7 Divisor Latch MSB (DLM)
7.22.5.8 Scratch Pad Register (SCR)
7.22.5.9 Line Control Register (LCR)
7.22.5.10 Modem Control Register (MCR)
7.22.5.11 Line Status Register (LSR)
7.22.5.12 Modem Status Register (MSR)
7.22.5.13 EC Serial Port Mode Register (ECSPMR)
7.22.6 Programming Guide
7.22.6.1 Programming Sequence
7.22.7 Software Reset
7.22.8 Clock Input Operation
7.22.9 FIFO Interrupt Mode Operation
7.22.10 High Speed Baud Rate Activation
7.23 Debugger (DBGR)
7.23.1 Overview
7.23.2 Features
7.23.3 Functional Description
7.23.3.1 DBGR/EPP
7.23.3.2 DBGR/SMB
7.23.3.3 In-system Programming Operation
7.23.3.4 In-system Debugging Operation
7.23.3.5 EC Memory Snoop (ECMS)
7.23.3.6 Other Debug Topics
7.24 Parallel Port (PP)
7.24.1 Overview
7.24.2 Features
7.24.3 Functional Description
7.24.3.1 KBS Connection with Parallel Port Connector
8. Register List
9. DC Characteristics
10. AC Characteristics
11. Analog Device Characteristics
12. Package Information
13. Ordering Information
14. Top Marking Information
IT5570E-128/IT5570VG-128
IT5570E-256/IT5570VG-256
Embedded Controller
Preliminary Specification V0.3.1
(For A Version)
ITE TECH. INC.
This specification is subject to Change without notice. It is provided “AS IS” and for reference only. For
purchasing information, please contact the nearest sales representatives.
Please note that the IT5570 V0.3.1 is applicable to the A version.
CONFIDENTIAL
CONFIDENTIAL
Copyright 2017 ITE Tech. Inc.
This is a Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous material issued for the products herein
referenced. Please contact ITE Tech. Inc. for the latest document(s).
All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE, IT5570 is a trademark of ITE Tech. Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
If you have any marketing or sales questions, please contact:
P.Y. Chang, at ITE Taiwan:
E-mail: p.y.chang@ite.com.tw, Tel: 886-2-29126889 X6052, Fax: 886-2-29102551
You may also find the local sales representative nearest you on the ITE web site.
To find out more about ITE, visit our World Wide Web at:
http://www.ite.com.tw
Or e-mail itesupport@ite.com.tw for more product information/services
ITE Tech. Inc.
Marketing Department
7F, No.233-1, Baociao Rd., Sindian City,
Taipei County 23145, Taiwan, ROC
Phone:
Fax:
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(02) 2910-2551, 2910-2552
CONFIDENTIAL
CONFIDENTIAL
Section
-
Revision History
Revision
Chapters regarding registers added
Revision History
Page No.
-
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IT5570 V0.3.1
CONFIDENTIAL
CONFIDENTIAL
CONTENTS
Contents
1. Features . .............................................................................................................................................. 1
2. General Description ....................................................................................................................................... 3
3. System Block Diagram................................................................................................................................... 5
3.1 Block Diagram ..................................................................................................................................... 5
3.2 EC Mapped Memory Space ................................................................................................................ 6
3.3 Register Abbreviation .......................................................................................................................... 8
4. Pin Configuration ........................................................................................................................................... 9
4.1 Top View ............................................................................................................................................. 9
5. Pin Descriptions ........................................................................................................................................... 13
5.1 Pin Descriptions ................................................................................................................................ 13
5.2 Chip Power Planes and Power States .............................................................................................. 20
5.3 Pin Power Planes and States ........................................................................................................... 21
5.4 Reset Sources and Types ................................................................................................................. 24
5.4.1 Related Interrupts to INTC ................................................................................................... 24
5.5 Chip Power Mode and Clock Domain ............................................................................................... 25
5.6 Pins with Pull, Schmitt-Trigger or Open-Drain Function ................................................................... 29
5.7 Pins with 1.8V Input/Output .............................................................................................................. 30
5.8 Power Consumption Consideration .................................................................................................. 31
6. Host Domain Functions................................................................................................................................ 33
6.1 The Enhanced Serial Peripheral Interface (eSPI) ............................................................................. 33
6.1.1 Overview ............................................................................................................................... 33
6.1.2 Features ............................................................................................................................... 33
6.1.3 Function Description ............................................................................................................. 33
6.1.3.1 Peripheral Channel .................................................................................................. 33
6.1.3.2 Flash Access Channel (MAFS) ............................................................................... 35
6.1.3.3 Flash Access Channel (SAFS) ................................................................................ 39
6.1.3.4 OOB Message Channel ........................................................................................... 41
6.1.3.5 Virtual Wires Channel .............................................................................................. 43
6.1.3.6 Expression of eSPI Interrupt Events ........................................................................ 45
6.1.4 EC Interface Registers, eSPI slave ...................................................................................... 45
6.1.4.1 Device Identification................................................................................................. 46
6.1.4.2 General Capabilities and Configurations ................................................................. 46
6.1.4.3 Channel 0 Capabilities and Configurations ............................................................. 48
6.1.4.4 Channel 1 Capabilities and Configurations ............................................................. 49
6.1.4.5 Channel 2 Capabilities and Configurations ............................................................. 50
6.1.4.6 Channel 3 Capabilities and Configurations ............................................................. 51
6.1.4.7 Channel 3 Capabilities and Configurations 2 .......................................................... 53
6.1.4.8 eSPI PC Control 0 (ESPCTRL0) ............................................................................. 55
6.1.4.9 eSPI PC Control 1 (ESPCTRL1) ............................................................................. 55
6.1.4.10 eSPI PC Control 2 (ESPCTRL2) ............................................................................. 55
6.1.4.11 eSPI PC Control 3 (ESPCTRL3) ............................................................................. 55
6.1.4.12 eSPI PC Control 4 (ESPCTRL4) ............................................................................. 56
6.1.4.13 eSPI PC Control 5 (ESPCTRL5) ............................................................................. 56
6.1.4.14 eSPI PC Control 6 (ESPCTRL6) ............................................................................. 56
6.1.4.15 eSPI PC Control 7 (ESPCTRL7) ............................................................................. 56
6.1.4.16 eSPI General Control 0 (ESGCTRL0) ..................................................................... 57
6.1.4.17 eSPI General Control 1 (ESGCTRL1) ..................................................................... 57
6.1.4.18 eSPI General Control 2 (ESGCTRL2) ..................................................................... 58
6.1.4.19 eSPI General Control 3 (ESGCTRL3) ..................................................................... 58
6.1.4.20 eSPI Upstream Control 0 (ESUCTRL0) .................................................................. 58
6.1.4.21 eSPI Upstream Control 1 (ESUCTRL1) .................................................................. 59
6.1.4.22 eSPI Upstream Control 2 (ESUCTRL2) .................................................................. 59
6.1.4.23 eSPI Upstream Control 3 (ESUCTRL3) .................................................................. 59
IT5570 V0.3.1
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IT5570 (For A Version)
6.1.4.24 eSPI Upstream Control 6 (ESUCTRL6) .................................................................. 59
6.1.4.25 eSPI Upstream Control 7 (ESUCTRL7) .................................................................. 59
6.1.4.26 eSPI Upstream Control 8 (ESUCTRL8) .................................................................. 60
6.1.4.27 eSPI OOB Control 0 (ESOCTRL0) .......................................................................... 60
6.1.4.28 eSPI OOB Control 1 (ESOCTRL1) .......................................................................... 60
6.1.4.29 eSPI OOB Control 4 (ESOCTRL4) .......................................................................... 60
6.1.4.30 eSPI SAFS Control 0 (ESPISAFSC0) ..................................................................... 60
6.1.4.31 eSPI SAFS Control 1 (ESPISAFSC1) ..................................................................... 61
6.1.4.32 eSPI SAFS Control 2 (ESPISAFSC2) ..................................................................... 61
6.1.4.33 eSPI SAFS Control 3 (ESPISAFSC3) ..................................................................... 61
6.1.4.34 eSPI SAFS Control 4 (ESPISAFSC4) ..................................................................... 61
6.1.4.35 eSPI SAFS Control 5 (ESPISAFSC5) ..................................................................... 61
6.1.4.36 eSPI SAFS Control 6 (ESPISAFSC6) ..................................................................... 61
6.1.4.37 eSPI SAFS Control 7 (ESPISAFSC7) ..................................................................... 62
6.1.5 EC Interface Registers, eSPI VW ........................................................................................ 62
6.1.5.1 VW Index 0 (VWIDX0) ............................................................................................. 62
6.1.5.2 VW Index 2-7 (VWIDX2-7) ...................................................................................... 62
6.1.5.3 VW Index 40-47 (VWIDX40-47) .............................................................................. 63
6.1.5.4 VW Contrl 0 (VWCTRL0) ......................................................................................... 63
6.1.5.5 VW Contrl 1 (VWCTRL1) ......................................................................................... 63
6.1.5.6 VW Contrl 2 (VWCTRL2) ......................................................................................... 64
6.1.5.7 VW Contrl 3 (VWCTRL3) ......................................................................................... 64
6.1.5.8 VW Contrl 5 (VWCTRL5) ......................................................................................... 65
6.1.5.9 VW Contrl 6 (VWCTRL6) ......................................................................................... 65
6.1.5.10 VW Contrl 7 (VWCTRL7) ......................................................................................... 65
6.1.6 EC Interface Registers, eSPI Queue 0 ................................................................................ 66
6.1.6.1 PUT_PC Data Byte 0-63 (PUTPCDB0-63).............................................................. 66
6.1.6.2 PUT_OOB Data Byte 0-79 (PUTOOBDB0-79) ....................................................... 66
6.1.7 EC Interface Registers, eSPI Queue 1 ................................................................................ 66
6.1.7.1 Upstream Data Byte 0-79 (UDB0-79) ...................................................................... 66
6.1.7.2 PUT_FLASH_NP Data Byte 0-63 (PUTFLASHNPDB0-63) .................................... 66
6.2 Low Pin Count Interface .................................................................................................................... 67
6.2.1 Overview ............................................................................................................................... 67
6.2.2 Features ............................................................................................................................... 67
6.2.3 Accepted LPC Cycle Type ................................................................................................... 67
6.2.4 Debug Port Function ............................................................................................................ 68
6.2.5 Serialized IRQ (SERIRQ) ..................................................................................................... 68
6.2.6 Related Interrupts to WUC ................................................................................................... 68
6.2.7 LPCPD# and CLKRUN# ....................................................................................................... 68
6.2.8 Check Items.......................................................................................................................... 69
6.3 Plug and Play Configuration (PNPCFG) ........................................................................................... 70
6.3.1 Logical Device Assignment .................................................................................................. 73
6.3.2 Super I/O Configuration Registers ....................................................................................... 74
6.3.2.1 Logical Device Number (LDN) ................................................................................. 74
6.3.2.2 Chip ID Byte 1 (CHIPID1) ........................................................................................ 74
6.3.2.3 Chip ID Byte 2 (CHIPID2) ........................................................................................ 74
6.3.2.4 Chip Version (CHIPVER) ......................................................................................... 75
6.3.2.5 Super I/O Control Register (SIOCTRL) ................................................................... 75
6.3.2.6 Super I/O IRQ Configuration Register (SIOIRQ) ..................................................... 75
6.3.2.7 Super I/O General Purpose Register (SIOGP) ........................................................ 76
6.3.2.8 Super I/O Power Mode Register (SIOPWR)............................................................ 76
6.3.2.9 Depth 2 I/O Address (D2ADR) ................................................................................ 76
6.3.2.10 Depth 2 I/O Data (D2DAT) ...................................................................................... 77
6.3.3 Standard Logical Device Configuration Registers ............................................................... 77
6.3.3.1 Logical Device Activate Register (LDA)................................................................... 77
6.3.3.2
I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 77
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