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Timing Constraints and Optimization User Guide Version O-2018.06....pdf
Preface
About This User Guide
Audience
Related Publications
Release Notes
Conventions
Customer Support
Accessing SolvNet
Contacting the Synopsys Technical Support Center
Introduction to Synthesis Timing
Static Timing Analysis
Timing Paths
Clocks
Input and Output Delays
Delay Calculation
Flip-Flop and Latch Timing Checks
Timing Analysis in the Design Flow
Synopsys Design Constraint Commands
Library Timing Data
Design Compiler
Ideal Clocking
Wire Load Models and Topographical Technology
Design Partitioning
Path Groups
Register Retiming Optimization
IC Compiler
Design Planning
Placement
Clock Tree Synthesis
Routing
Timing Analysis After Routing
Synthesis Design Rules
Clocks
Creating Clocks
Clock Network Effects
Clock Latency
Propagated Latency
Ideal Network Latency
Source Latency
Clock Uncertainty
Ideal Clock Transition Times
Reporting Clock Information
Multiple Clocks
Synchronous Clocks
Asynchronous Clocks
Exclusive Clocks
Clock Sense
Pulse Clocks
Minimum Pulse Width Checks
Clock-Gating Signal Timing Checks
Generated Clocks
Divide-by-2 Generated Clock
Generated Clock Based on Edges
Divide-by Clock Based on Falling Edges
Shifting the Edges of a Generated Clock
Combinational-Only Source Latency Calculation
Generated Clock Based on a Non-Unate Master Clock
Estimated I/O Latency
Calculating I/O Latency for Input Paths
Calculating I/O Latency for Output Paths
Propagated Clocks
Timing Paths
Path Groups
User Grouping of Paths
Weight or Cost Function
Critical Range
Reporting Path Groups
Path Specification Methods
Through Arguments
Rise/Fall From/To Clock
Default Path Delay Constraints
Path Delay for Flip-Flops Using a Single Clock
Path Delay for Flip-Flops Using Different Clocks
Setup Analysis
Hold Analysis
Single-Cycle Path Analysis Examples
Timing Exceptions
False Path Exceptions
Maximum and Minimum Path Delay Exceptions
Multicycle Path Exceptions
Path Timing Margin Exceptions
Specifying Exceptions Efficiently
Exception Order of Precedence
Exception Type Priority
Path Specification Priority
Reporting Exceptions
Removing Exceptions
Preset and Clear Timing
Data-to-Data Checks
Specifying Data-to-Data Checks
Generating Timing Reports for Data Checks
Data Checks and Clock Domains
Library-Based Data Checks
Operating Conditions
Operating Condition Definitions
Setting Operating Conditions
Operating Condition Modes
Minimum and Maximum Delay Calculations
Min-Max Cell and Net Delay Values
Setup and Hold Checks
Path Delay Tracing for Setup and Hold Checks
Setup Timing Check for Worst-Case Conditions
Hold Timing Check for Best-Case Conditions
Simultaneous Best-Case/Worst-Case Conditions
Path Tracing in On-Chip Variation Mode
Using Two Libraries for Min-Max Analysis
Setting On-Chip Variation Derating Factors
Advanced On-Chip Variation Analysis
How AOCV Analysis Works
Cell Adjustment Factor
AOCV Flow
AOCV Data Formats
Library-Based AOCV Data
File-Based AOCV Data
Advanced On-Chip Variation Reporting
Fast Path-Based AOCV
Parametric On-Chip Variation Analysis
How POCV Analysis Works
Parametric On-Chip Variation Flow
POCV Data Formats
Library-Based POCV Data
File-Based POCV Data
Saving Scenario-Specific POCV Data
Enabling Parametric On-Chip Variation Analysis
Reading File-Based Parametric On-Chip Variation Data
POCV Guard Band (IC Compiler Only)
Scaling the POCV Coefficients (IC Compiler Only)
Reporting POCV Information
Reporting the POCV Analysis Results
Voltage and Temperature Scaling Between Libraries
Clock Reconvergence Pessimism Removal
On-Chip Variation Example
Reconvergent Logic Example
Setting Clock Reconvergence Pessimism Removal
Transparent Latch Edge Considerations
Reporting CRPR Calculations
Timing Constraints
Input Delays
Excluding Clocks
Reference Pin
Output Delays
Drive Characteristics at Input Ports
Setting the Port Driving Cell
Setting the Port Drive Resistance
Setting a Fixed Port Transition Time
Removing Drive Information From Ports
Port Load Capacitance
Ideal Networks
Propagation of the Ideal Network Property
Creating Ideal Networks
Removing Ideal Networks
Reporting Ideal Networks
Retrieving Ideal Objects
Setting Ideal Latency and Ideal Transition Time
Case Analysis
Reporting Case Analysis
Removing Case Analysis
Constant Propagation Log File
Usage Example
Mode Analysis
Mode Groups
Setting Modes Using Case Analysis
Setting Modes Directly on Cells
Reporting Modes
Wire Load Models
Net Capacitance, Resistance, and Area Calculation
Choosing a Wire Load Model
Wire Load Model Modes
Setting a Wire Load Model
Local Link Library Usage
Setting a Wire Load Selection Group
Wire Load Models for Hierarchical Cells
Selecting the Wire Load Model Automatically
Defining the Minimum Block Size
Reporting Wire Load Models
Timing Loops
Breaking Feedback Loops Manually
Back-Annotation
Back-Annotating Delays and Timing Checks
Delay Calculations
Back-Annotating Timing Information From an SDF File
Instance Names
Cell and Pin Names
DESIGN Field Names
Supported SDF Constructs
Back-Annotating Timing From a Subdesign Timing File
Back-Annotating Load Delay
Back-Annotating for Worst Timing Delay
Back-Annotating Timing Checks
Back-Annotating for Conditional Arc Cell Delay
Back-Annotation Order of Precedence
Examples
Writing an SDF File
Annotating Delays and Timing Checks From the Command Line
Defining Net and Cell Delays
Defining Timing Check Values Between Pins
Reporting Annotated Values and Checks
Reporting Load and Resistance Values
Reporting Annotated Delay Values
Removing Back-Annotated Values
Removing Annotated Delay Values
Removing Annotated Timing Checks Between Specific Pins
Removing Annotated Resistance or Capacitance Values
Removing Back-Annotated Values Command Summary
Setting Net Load
Setting Net Resistance
Setting Pi Model Capacitance and Resistance
Back-Annotating Detailed Parasitics
RTL Load Annotation With Wire Load Modeling
Default Resistance Values
RTL Load Buffering
Extraction of RTL Loads
Timing Reports
Reporting Commands
check_timing Command
report_constraint Command
report_timing Command
report_timing Report Contents
report_timing Command Options
Scope of the Design Reported
Path Details Reported
Delay Type (Min/Max) Reported
Number of Paths Reported
Other Options
report_delay_calculation Command
get_timing_paths Command
report_clock_timing Command
Latency and Transition Time Reporting
Skew Reporting
Interclock Skew Reporting
Clock Timing Reporting Options
Summary Report
List Report
Verbose (Path) Report
Graphical User Interface
Using the GUI for Timing Analysis
Timing Menu Commands
IC Compiler Layout Window Timing Menu Commands
Path Slack Histogram
Path Inspector
Path Schematic
Path Element Tables
Path Delay Profiles
Timing Analysis Driver
Timing in Latch-Based Designs
Time Borrowing in Latch-Based Designs
A Simple D Latch
About Time Borrowing
Time Borrowed and Time Given
Balancing Relative Slacks
Determining Relative Slack
Optimizing Near-Critical Paths
Reducing Delay Costs
Automatic Slack Distribution During Optimization
Normalized Slack Analysis
Enabling Normalized Slack Analysis
Reporting Normalized Slack
Using Normalized Slack to Adjust the Clock Period
Setting Limits for Normalized Slack Analysis
Constraining a Latch-Based Design
Creating Non-Overlapping Clocks
What Are Two-Phase Designs?
What Are Non-Overlapping Clocks?
Path Timing Report With Borrowing
Latch-Based Time-Borrowing Example
Linear Block Encoder and Decoder
Noisy Channel
Linear Block Decoder for Single-Bit Error
Linear Block Encoder and Decoder Implementation
Setting Constraints on the Linear Block Encoder
report_timing Command Output
Advanced Latch Timing Analysis
Enabling Advanced Latch Analysis
Breaking Loops
Specifying Loop-Breaker Latches
Finding Loop-Breaker Latches
Latch Loop Groups
Listing Collections of Latch Loop Groups
Reporting Latch Loop Groups
Specifying the Maximum Number of Latches Analyzed Per Path
Timing Exceptions Applied to Latch Paths
False Path Exceptions
Multicycle Path Exceptions
Maximum and Minimum Delay Exceptions
Clock Groups
Specification of Exceptions on Throughpaths
Reporting Paths Through Latches With report_timing
Calculation of the Worst and Total Negative Slack
Static Timing Delay Calculation
Path-Based Timing Optimization
Reporting Retain Arcs
Reporting Arc Delay Calculations
Debugging Delay Calculations Along a Critical Path
Reporting Details of a Cell Delay Arc
Delay Models
Linear Delay Model
Slope Delay
Intrinsic Delay
Transition Time
Connect Delay
Delay Calculation (Linear) Example
CMOS2 Delay Model
Edge Rate Delay
Intrinsic Delay
Transition Time
Connect Delay
Delay Calculation (CMOS2) Example
Nonlinear Delay Model
Library Cell Timing Arcs
Delay Calculation Example
Environmental Scaling
Waveform Propagation Using CCS Models
Synopsys®
Timing Constraints and Optimization
User Guide
Version O-2018.06, June 2018
Copyright Notice and Proprietary Information
©2018 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to
Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with
Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated
documentation is strictly prohibited.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective owners.
Free and Open-Source Software Licensing Notices
If applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.
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and is not responsible for such websites and their practices, including privacy practices, availability, and content.
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www.synopsys.com
Synopsys® Timing Constraints and Optimization User Guide, Version O-2018.06
ii
Copyright Notice for the Command-Line Editing Feature
© 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software
contributed to Berkeley by Christos Zoulas of Cornell University.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1.Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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disclaimer in the documentation and/or other materials provided with the distribution.
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Copyright Notice for the Line-Editing Library
© 1992 Simmule Turner and Rich Salz. All rights reserved.
This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of
the University of California.
Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and
redistribute it freely, subject to the following restrictions:
1.The authors are not responsible for the consequences of use of this software, no matter how awful, even if they arise
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read sources, credits must appear in the documentation.
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4.This notice may not be removed or altered.
Synopsys® Timing Constraints and Optimization User Guide, Version O-2018.06
iii
Synopsys® Timing Constraints and Optimization User Guide, Version O-2018.06
iv
Contents
About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accessing SolvNet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Synopsys Technical Support Center . . . . . . . . . . . . . . . . . . . . .
1-xvi
1-xvi
1-xvi
1-xvii
1-xviii
1-xix
1-xix
1-xix
1.
Introduction to Synthesis Timing
Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip-Flop and Latch Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Analysis in the Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synopsys Design Constraint Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library Timing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Load Models and Topographical Technology . . . . . . . . . . . . . . . . . . .
Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Retiming Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-7
1-11
1-13
1-14
1-16
1-19
1-19
1-24
1-26
1-26
1-27
1-29
1-30
1-33
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Synopsys® Timing Constraints and Optimization User Guide
O-2018.06
Version O-2018.06
IC Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Analysis After Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesis Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Clocks
Creating Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Network Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagated Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Network Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Uncertainty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Clock Transition Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Clock Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exclusive Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum Pulse Width Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock-Gating Signal Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-by-2 Generated Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generated Clock Based on Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-by Clock Based on Falling Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shifting the Edges of a Generated Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combinational-Only Source Latency Calculation . . . . . . . . . . . . . . . . . . . . . . .
Generated Clock Based on a Non-Unate Master Clock . . . . . . . . . . . . . . . . . .
Estimated I/O Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
1-34
1-35
1-35
1-37
1-38
1-39
1-41
2-2
2-3
2-5
2-5
2-6
2-7
2-8
2-11
2-11
2-12
2-14
2-16
2-16
2-18
2-22
2-24
2-25
2-29
2-30
2-30
2-31
2-33
2-34
2-35
2-37
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Calculating I/O Latency for Input Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculating I/O Latency for Output Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Timing Paths
Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Grouping of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Weight or Cost Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Critical Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Specification Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Through Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rise/Fall From/To Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Path Delay Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Delay for Flip-Flops Using a Single Clock . . . . . . . . . . . . . . . . . . . . . . . . .
Path Delay for Flip-Flops Using Different Clocks. . . . . . . . . . . . . . . . . . . . . . . .
Setup Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hold Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Cycle Path Analysis Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
False Path Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum and Minimum Path Delay Exceptions . . . . . . . . . . . . . . . . . . . . . . . .
Multicycle Path Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Timing Margin Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Exceptions Efficiently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exception Order of Precedence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exception Type Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Specification Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Removing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preset and Clear Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data-to-Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Data-to-Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating Timing Reports for Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Checks and Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1: Contents
Contents
2-39
2-40
2-40
3-2
3-2
3-2
3-3
3-3
3-4
3-5
3-6
3-9
3-9
3-11
3-12
3-12
3-13
3-15
3-16
3-17
3-18
3-23
3-24
3-26
3-26
3-27
3-28
3-29
3-29
3-30
3-31
3-33
3-34
vii
1-vii
Synopsys® Timing Constraints and Optimization User Guide
Synopsys® Timing Constraints and Optimization User Guide
O-2018.06
Version O-2018.06
Library-Based Data Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-34
4. Operating Conditions
Operating Condition Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Condition Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum and Maximum Delay Calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Min-Max Cell and Net Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup and Hold Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Delay Tracing for Setup and Hold Checks . . . . . . . . . . . . . . . . . . . . .
Setup Timing Check for Worst-Case Conditions . . . . . . . . . . . . . . . . . . . .
Hold Timing Check for Best-Case Conditions. . . . . . . . . . . . . . . . . . . . . . .
Simultaneous Best-Case/Worst-Case Conditions . . . . . . . . . . . . . . . . . . .
Path Tracing in On-Chip Variation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Two Libraries for Min-Max Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting On-Chip Variation Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced On-Chip Variation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How AOCV Analysis Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Adjustment Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AOCV Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AOCV Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library-Based AOCV Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
File-Based AOCV Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced On-Chip Variation Reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Path-Based AOCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parametric On-Chip Variation Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How POCV Analysis Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parametric On-Chip Variation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POCV Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library-Based POCV Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
File-Based POCV Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving Scenario-Specific POCV Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling Parametric On-Chip Variation Analysis. . . . . . . . . . . . . . . . . . . . . . . .
Reading File-Based Parametric On-Chip Variation Data. . . . . . . . . . . . . . . . . .
POCV Guard Band (IC Compiler Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
4-2
4-4
4-5
4-6
4-7
4-8
4-8
4-9
4-10
4-11
4-11
4-12
4-12
4-15
4-15
4-17
4-17
4-17
4-18
4-19
4-21
4-22
4-22
4-23
4-24
4-25
4-26
4-27
4-29
4-29
4-30
4-31
viii
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