genus_user.pdf

发布时间：2022-05-30 发布人：admin 分类：说明书资料大小：1.57M 资料格式：pdf 举报版权申诉

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Contents

Preface

About This Manual

Additional References

Reporting Problems or Errors in Manuals

Customer Support

Cadence Online Support

Other Support Offerings

Supported User Interfaces

Messages

Man Pages

Command-Line Help

Getting the Syntax for a Command

Getting Attribute Help

Searching For Commands When You Are Unsure of the Name

Documentation Conventions

Text Command Syntax

Introduction

Overview

Installing the Genus Software

Licensing

Getting Started with Genus

The CDN_SYNTH_ROOT Variable

Using the Initialization File

Invoking Genus

Customizing the Log File and Command File Names

Setting Information Level and Messages

Working in the Genus Shell

Navigation

Objects and Attributes

Output Redirection

Scripting

Using SDC Commands

Getting Help

Getting Help on a Command or an Attribute

Getting Help on an Attribute

Genus Messages: Errors, Warnings, and Information

Tips and Shortcuts

Accessing UNIX Environment Variables from Genus

Working with Tcl in Genus

Using Command Abbreviations

Using Tab Completion

Using Wildcards

Using the Command Line Editor

Genus Design Information Hierarchy

Overview

Setting the Current Design

Specifying Hierarchy Names

Describing the Design Information Hierarchy

Working in the Top-Level (root) Directory

Working in the designs Directory

Working in the Library Directory

Working in the hdl_libraries Directory

Working in the obj_types Directory

Manipulating Objects in the Design Information Hierarchy

Ungrouping Modules During and After Elaboration

Finding Information in the Design Information Hierarchy

Using the vcd Command to Navigate the Design Information Hierarchy

Using the vls Command to List Directory Objects and Attributes

Using the get_db Command to Search for Information

Navigating a Sample Design

Saving the Design Information Hierarchy

Using the Libraries

Overview

Tasks

Specifying Explicit Search Paths

Specifying Implicit Search Paths

Specifying Settings that Influence Handling of Library Cells

Setting the Target Technology Library

Preventing the Use of Specific Library Cells

Forcing the Use of Specific Library Cells

Working with Liberty Format Technology Libraries

Using Voltage Scaling

Library Scaling in Multi-Mode Multi-Corner (MMMC) Flow

Troubleshooting

Cells Identified as Unusable

Cells Identified as Timing Models

Loading Files

Overview

Tasks

Updating Scripts through Patching

Running Scripts

Reading HDL Files

Loading HDL Files

Specifying the HDL Language Mode

Specifying HDL Search Paths

Reading Verilog Files

Defining Verilog Macros

Reading VHDL Files

Specifying the VHDL Environment

Verifying VHDL Code Compliance with the LRM

Specifying Illegal Characters in VHDL

Showing the VHDL Logical Libraries

Using Arithmetic Packages from Other Vendors

Modifying the Case of VHDL Names

Reading Designs with Mixed Verilog and VHDL Files

Reading in Verilog Modules and VHDL Entities with Same Names

Using Case Sensitivity in Verilog/VHDL Mixed-Language Designs

Reading and Elaborating a Structural Netlist Design

Reading a Partially Structural Design

Keeping Track of Loaded HDL Files

Importing the Floorplan

Elaborating the Design

Overview

Tasks

Performing Elaboration

Specifying Top-Level Parameters or Generic Values

Specifying HDL Library Search Paths

Elaborating a Specified Module or Entity

Naming Individual Bits of Array and Record Ports and Registers

Naming Individual Bits of Multi-Bit Wires

Naming Parameterized Modules

Keeping Track of the RTL Source Code

Grouping an Extra Level of Design Hierarchy

Applying Constraints

Overview

Tasks

Importing and Exporting SDC

Applying Timing Constraints

Importing Physical Information

Applying Design Rule Constraints

Creating Ideal Objects

Defining Optimization Settings

Overview

Preserving Instances and Modules

Grouping and Ungrouping Objects

Grouping

Ungrouping

Partitioning

Setting Boundary Optimization

Mapping to Complex Sequential Cells

Deleting Unused Sequential Instances

Controlling Merging of Combinational Hierarchical Instances

Optimizing Total Negative Slack

Making DRC the Highest Priority

Creating Hard Regions

Deleting Buffers and Inverters Driven by Hard Regions

Preventing Boundary Optimization through Hard Regions

Reducing Runtime Using Super-Threading

Overview

Licensing and CPU Usage

Using Super-Threading on Local Host

Using Super-Threading on Remote Shell

Using Super-Threading on Platform Load Sharing Facility (LSF)

Using Super-Threading on Sun Grid Engine (SGE)

Performing Synthesis

Overview

RTL Optimization

Global Focus Mapping

Global Incremental Optimization

Incremental Optimization (IOPT)

Tasks

Synthesizing your Design

Synthesizing Submodules

Synthesizing Unresolved References

Re-synthesizing with a New Library (Technology Translation)

Setting Effort Levels

Quality of Silicon Prediction

Generic Gates in a Generic Netlist

Generic Flop

Generic Latch

Generic Mux

Generic Dont-Care

Writing the Generic Netlist

Reading the Netlist

Analyzing the Log File

Retiming the Design

Overview

Retiming for Timing

Retiming for Area

Tasks

Retiming Using the Automatic Top-Down Retiming Flow

Manual Retiming (Block-Level Retiming)

Incorporating Design for Test (DFT) and Low Power Features

Localizing Retiming Optimizations to Particular modules

Controlling Retiming Optimization

Retiming Registers with Asynchronous Set and Reset Signals

Identifying Retimed Logic

Retiming Multiple Clock Designs

Performing Functional Verification

Overview

Tasks

Writing Out dofiles for Formal Verification

Generating Reports

Overview

Tasks

Generating Timing Reports

Generating Area Reports

Tracking and Saving QoR Metrics

Summarizing Messages

Redirecting Reports

Customizing the report_* Commands

Using the Genus Database

Overview

Tasks

Saving the Netlist and Setup

Restoring the Netlist and Setup

Splitting the Database

Interfacing to Place and Route

Overview

Preparing the Netlist for Place-and-Route or Third-Party Tools

Changing Names

Naming Flops

Removing Assign Statements

Inserting Tie Cells

Handling Bit Blasted Port Styles

Handling Bit-Blasted Constants

Generating Design and Session Information

Saving and Restoring a Session in Genus

Writing Out the Design Netlist

Writing SDC Constraints

Writing an SDF File

Modifying the Netlist

Overview

Connecting Pins, Ports, and hports

Disconnecting Pins, Ports, and hports

Creating New Instances

Overriding Preserved Modules

Creating Unique Parameter Names

Naming Generated Components

Changing the Instance Library Cell

IP Protection

Overview

Decryption and Encryption using xmprotect

Supported Encryption Flows

Variation due to encryption pragma

Variation due to type of encryption key

Levels of Protection

Round-trip Protection Flow

Details and Examples of Protection Features

Encrypting Designs within Genus

Encrypting Designs outside Genus

Loading Encrypted Designs

Writing Encrypted Designs

Attributes — "protected" and "encrypted"

Simple Synthesis Template

Index

Genus User Guide Product Version 19.1 August 2019

© 2015-2018 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. All other trademarks are the property of their respective holders. Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used only in accordance with a written agreement between Cadence and its customer. 2. The publication may not be modified in any way. 3. Any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement. 4. The information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

Genus User Guide Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Additional References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reporting Problems or Errors in Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Cadence Online Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Other Support Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Supported User Interfaces Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Command-Line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 . . . . . . . . . . . . . . . . 21 Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Getting the Syntax for a Command Getting Attribute Help Searching For Commands When You Are Unsure of the Name Text Command Syntax 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Overview Installing the Genus Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Getting Started with Genus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 The CDN_SYNTH_ROOT Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Using the Initialization File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Invoking Genus Customizing the Log File and Command File Names . . . . . . . . . . . . . . . . . . . . . . . . 30 Setting Information Level and Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Navigation Objects and Attributes Working in the Genus Shell August 2019 Product Version 19.1 © 2015-2019 Cadence Design Systems, Inc. All Rights Reserved. 3

Genus User Guide Getting Help Output Redirection Scripting Using SDC Commands Getting Help on a Command or an Attribute Getting Help on an Attribute Genus Messages: Errors, Warnings, and Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Accessing UNIX Environment Variables from Genus . . . . . . . . . . . . . . . . . . . . . . . . 40 Working with Tcl in Genus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Using Command Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Using Tab Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Using Wildcards Using the Command Line Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Tips and Shortcuts Setting the Current Design Specifying Hierarchy Names 2 Genus Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Describing the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Working in the Top-Level (root) Directory Working in the designs Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Working in the Library Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Working in the hdl_libraries Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Working in the obj_types Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 . . . . . . . . . . . . . . . . . . . . . . . 82 . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Finding Information in the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . 85 . . . . . . . . . . 85 . . . . . . . . . . . . . . . . 86 . . . . . . . . . . . . . . . . . . . . . . . 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Using the vcd Command to Navigate the Design Information Hierarchy Using the vls Command to List Directory Objects and Attributes Using the get_db Command to Search for Information Navigating a Sample Design Manipulating Objects in the Design Information Hierarchy Ungrouping Modules During and After Elaboration Saving the Design Information Hierarchy August 2019 Product Version 19.1 © 2015-2019 Cadence Design Systems, Inc. All Rights Reserved. 4

Genus User Guide 3 Using the Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Specifying Explicit Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Specifying Implicit Search Paths . . . . . . . . . . . . . . . . . . 103 Specifying Settings that Influence Handling of Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Setting the Target Technology Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Preventing the Use of Specific Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Forcing the Use of Specific Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . 106 Working with Liberty Format Technology Libraries Using Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Library Scaling in Multi-Mode Multi-Corner (MMMC) Flow . . . . . . . . . . . . . . . . . . . . 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Cells Identified as Unusable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Cells Identified as Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Troubleshooting 4 Loading Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Tasks Updating Scripts through Patching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Running Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Reading HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Loading HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Specifying the HDL Language Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Specifying HDL Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Reading Verilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Specifying the VHDL Environment Verifying VHDL Code Compliance with the LRM Specifying Illegal Characters in VHDL Showing the VHDL Logical Libraries Defining Verilog Macros Reading VHDL Files August 2019 Product Version 19.1 © 2015-2019 Cadence Design Systems, Inc. All Rights Reserved. 5

Genus User Guide Reading Designs with Mixed Verilog and VHDL Files Reading in Verilog Modules and VHDL Entities with Same Names Using Case Sensitivity in Verilog/VHDL Mixed-Language Designs Using Arithmetic Packages from Other Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Modifying the Case of VHDL Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 . . . . . . . . . . . . . . . . . . . . . . . . . . 143 . . . . . . . . . . . . . 143 . . . . . . . . . . . . . 143 Reading and Elaborating a Structural Netlist Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Reading a Partially Structural Design Keeping Track of Loaded HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Importing the Floorplan 5 Elaborating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Tasks Performing Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Specifying Top-Level Parameters or Generic Values . . . . . . . . . . . . . . . . . . . . . . . 152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Specifying HDL Library Search Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Elaborating a Specified Module or Entity Naming Individual Bits of Array and Record Ports and Registers . . . . . . . . . . . . . . 154 Naming Individual Bits of Multi-Bit Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Naming Parameterized Modules Keeping Track of the RTL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Grouping an Extra Level of Design Hierarchy 6 Applying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Tasks Importing and Exporting SDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Applying Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Importing Physical Information Applying Design Rule Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Creating Ideal Objects August 2019 Product Version 19.1 © 2015-2019 Cadence Design Systems, Inc. All Rights Reserved. 6

Genus User Guide 7 Defining Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Preserving Instances and Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Grouping and Ungrouping Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Ungrouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 . . . . . . . . . . . . . . . . . . . . 196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Deleting Buffers and Inverters Driven by Hard Regions . . . . . . . . . . . . . . . . . . . . . . 199 Preventing Boundary Optimization through Hard Regions . . . . . . . . . . . . . . . . . . . . 200 Partitioning Setting Boundary Optimization Mapping to Complex Sequential Cells Deleting Unused Sequential Instances Controlling Merging of Combinational Hierarchical Instances Optimizing Total Negative Slack Making DRC the Highest Priority Creating Hard Regions 8 Reducing Runtime Using Super-Threading . . . . . . . . . . . . . . . . . . 201 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Licensing and CPU Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Using Super-Threading on Local Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Using Super-Threading on Remote Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Using Super-Threading on Platform Load Sharing Facility (LSF) . . . . . . . . . . . . . . . . . 205 Using Super-Threading on Sun Grid Engine (SGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 9 Performing Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 RTL Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Global Focus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Global Incremental Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Incremental Optimization (IOPT) August 2019 Product Version 19.1 © 2015-2019 Cadence Design Systems, Inc. All Rights Reserved. 7

Genus User Guide Tasks Synthesizing your Design Synthesizing Submodules Synthesizing Unresolved References Re-synthesizing with a New Library (Technology Translation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 . . . . . . . . . . . . . . . . 217 Setting Effort Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Quality of Silicon Prediction Generic Gates in a Generic Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Generic Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Generic Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Generic Mux Generic Dont-Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Writing the Generic Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Reading the Netlist Analyzing the Log File Tasks Retiming for Timing Retiming for Area 10 Retiming the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Retiming Using the Automatic Top-Down Retiming Flow . . . . . . . . . . . . . . . . . . . . . 246 Manual Retiming (Block-Level Retiming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Incorporating Design for Test (DFT) and Low Power Features . . . . . . . . . . . . . . . . 251 Localizing Retiming Optimizations to Particular modules . . . . . . . . . . . . . . . . . . . . . 254 Controlling Retiming Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Retiming Registers with Asynchronous Set and Reset Signals . . . . . . . . . . . . . . . . 256 Identifying Retimed Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Retiming Multiple Clock Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 11 Performing Functional Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Overview Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 August 2019 Product Version 19.1 © 2015-2019 Cadence Design Systems, Inc. All Rights Reserved. 8

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