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QorIQ Data Path Acceleration Architecture (DPAA) Reference Manua....pdf
Contents
Figures
Tables
Terminology, Conventions, and Resources
Terms, Acronyms, and Abbreviations
Table i. Terms, Acronyms, and Abbreviations
Notational Conventions
Table ii. Notational Conventions
Suggested Reading
Table iii. Related Documentation Types
Chapter 1 Data Path Acceleration Architecture (DPAA) Overview
1.1 Purpose of this manual
1.2 General DPAA Functionality
1.2.1 Packet Distribution and Queue/Congestion Management
Table 1-1. DPAA Offload Functions
1.2.2 Content Processing Acceleration
Table 1-2. DPAA Content-Processing Accelerators
1.3 DPAA Programming Model
Figure 1-1. Queuing Messages to Channels
1.4 DPAA Terms and Definitions
Table 1-3. DPAA Terms and Definitions
1.5 Major DPAA Components
Figure 1-2. Example of QorIQ Data Path Acceleration Architecture (DPAA)
1.5.1 Queue Manager (QMan)
1.5.2 Buffer Manager (BMan)
1.5.3 Frame Manager (FMan)
1.5.3.1 FMan Network Interfaces
1.5.3.2 FMan Parse Function
Table 1-4. Parser Header Types
1.5.3.3 FMan Distribution and Policing
Table 1-5. Post-Parsing Treatment Options
1.5.3.3.1 FMan Policer
1.5.4 Security Engine (SEC) 4.x
Table 1-6. SEC 4.x Crypto Hardware Accelerators (CHAs)
1.5.5 Pattern Matching Engine (PME) 2.x
1.5.5.1 PME Regular Expressions (Regex)
1.5.5.2 PME Match Detection
Figure 1-3. PME 2.x Block Diagram
1.5.6 RapidIO Message Manager (RMan)
1.5.7 RAID Engine (RE) 5/6
1.6 Data Formats Used in the DPAA
1.6.1 Frame Descriptor (FD)
1.6.1.1 FD Format
Figure 1-4. Frame Descriptor (FD)
Table 1-7. FD Field Description
1.6.1.2 Frame Descriptor (FD) Considerations
1.6.2 Multi-Buffer Frames
1.6.2.1 Scatter/Gather Entry Format
Figure 1-5. Scatter/Gather Table Entry Format
Table 1-8. Scatter/Gather Table Entry Field Descriptions
1.6.2.2 Multi-Buffer Frame Considerations
Figure 1-6. Simplified Representation of a Long, Multi-Buffer, Simple Frame
1.6.2.3 Situations Where Multi-Buffer-Frame Processing Stops
1.6.3 Single-Buffer Frames
1.6.4 Compound Frames
1.6.4.1 When to Use Compound Frames
1.6.4.2 Compound Frame Considerations
Figure 1-7. Simplified Representation of a Compound Frame
1.6.5 Simple Frames
Table 1-9. Simple Frame Types
1.6.6 Frame Format Codes
Table 1-10. Frame Format Codes
1.6.7 Frame Formats Supported by Accelerators
Table 1-11. Frame Format Support Matrix
1.6.8 Special Values and Exceptions
1.6.9 Releasing Buffers to the BMan
1.7 Accessing Memory Using Logical IO Device Numbers (LIODNs)
1.7.1 Role of the PAMU in the DPAA
1.7.2 Using Multiple LIODNs
1.7.2.1 Benefit of Using Multiple LIODNs
1.7.2.2 LIODN Requirements
1.8 Packet Walk-Through Example
1.9 Differences between DPAA Modules per chip
Table 1-12. DPAA Module Support
Chapter 2 Memory Map
2.1 Memory Map Overview
2.1.1 Considerations When Accessing Reserved Registers and Bits
2.1.2 DPAA Address Map
Table 2-1. DPAA-Block Base Address Map
Chapter 3 Datapath Three Speed Ethernet Controller (dTSEC)
3.1 dTSEC Overview
Figure 3-1. dTSEC Block Diagram
3.2 dTSEC Features Summary
3.3 dTSEC Implementation
3.4 dTSEC Modes of Operation
3.4.1 Full- and Half-Duplex Operation
3.4.2 10- and 100-Mbps RMII Interface Operation
3.4.3 MAC Address Recognition Options
3.5 dTSEC External Signals Description
Table 3-1. dTSEC Network Interface Options
Table 3-2. dTSEC Network Interface Signal Summary
Table 3-3. dTSEC Client 1588 Signal Summary
3.5.1 dTSEC Detailed Signal Descriptions
Table 3-4. P4080, P5020, P3041, P2040 dTSEC Signals-Detailed Signal Descriptions (continued)
Table 3-5. P1023 dTSEC Signals-Detailed Signal Descriptions (continued)
3.6 dTSEC Memory Map/Register Definition
3.6.1 dTSEC Top-Level Module Memory Map
Table 3-6. dTSEC Ethernet MAC Memory Map Summary
Table 3-7. dTSEC Ethernet Management Interface Memory Map Summary
3.6.2 dTSEC Detailed Memory Map
Table 3-8. dTSEC Ethernet Module Memory Map (continued)
Table 3-9. dTSEC Ethernet Management Interface Memory Map (continued)
3.6.3 dTSEC Memory-Mapped Register Descriptions
3.6.3.1 General Control and Status Registers
3.6.3.1.1 Controller ID Register (dTSEC_ID)
Figure 3-2. Controller ID Register (dTSEC_ID)
Table 3-10. dTSEC_ID Field Descriptions
3.6.3.1.2 Controller ID Register 2 (TSEC_ID2)
Figure 3-3. Controller ID Register 2 (TSEC_ID2)
Table 3-11. dTSEC_ID2 Field Descriptions
3.6.3.1.3 Interrupt Event Register (IEVENT)
Figure 3-4. Interrupt Event Register (IEVENT)
Table 3-12. IEVENT Field Descriptions (continued)
3.6.3.1.4 Interrupt Mask Register (IMASK)
Figure 3-5. Interrupt Mask Register (IMASK)
Table 3-13. IMASK Field Descriptions
3.6.3.1.5 Ethernet Control Register (ECNTRL)
Figure 3-6. Ethernet Control Register (ECNTRL)
Table 3-14. ECNTRL Field Descriptions (continued)
Table 3-7. P4080 dTSEC Interface Configurations
Table 3-8. P1023, P5020, P3041, P2040 dTSEC Interface Configurations
3.6.3.1.6 Pause Time Value Register (PTV)
Figure 3-9. Pause Time Value Register (PTV)
Table 3-15. PTV Field Descriptions
3.6.3.1.7 TBI Physical Address Register (TBIPA)
Figure 3-10. TBI Physical Address Register (TBIPA)
Table 3-16. TBIPA Field Descriptions
3.6.3.1.8 Timer Control Register (TMR_CTRL)
Figure 3-11. Timer Control Register (TMR_CTRL)
Table 3-17. TMR_CTRL Register Field Descriptions (continued)
3.6.3.1.9 Timer PTP Packet Event Register (TMR_PEVENT)
Figure 3-12. Timer PTP Packet Event Register (TMR_PEVENT)
Table 3-18. TMR_PEVENT Register Field Descriptions
3.6.3.1.10 Timer Event Mask Register (TMR_PEMASK)
Figure 3-13. Timer Event Mask Register (TMR_PEMASK)
Table 3-19. TMR_PEMASK Register Field Descriptions
3.6.3.2 Transmit/Receive and Interface Control and Status Registers
3.6.3.2.1 Transmit Control Register (TCTRL)
Figure 3-14. Transmit Control Register (TCTRL)
Table 3-20. TCTRL Field Descriptions (continued)
3.6.3.2.2 Receive Control Register (RCTRL)
Figure 3-15. Receive Control Register (RCTRL)
Table 3-21. RCTRL Field Descriptions (continued)
3.6.3.3 Hash Function Registers
3.6.3.3.1 Individual/Group Address Registers 0-7 (IGADDRn)
Figure 3-16. Individual/Group Address Registers 0-7 (IGADDRn)
Table 3-22. IGADDRn Field Description
3.6.3.3.2 Group Address Registers 0-7 (GADDRn)
Figure 3-17. Group Address Registers 0-7 (GADDRn)
Table 3-23. GADDRn Field Description
3.6.3.4 MAC Registers
3.6.3.4.1 MAC Configuration 1 Register (MACCFG1)
Figure 3-18. MACCFG1 Register Definition
Table 3-24. MACCFG1 Field Descriptions (continued)
3.6.3.4.2 MAC Configuration 2 Register (MACCFG2)
Figure 3-19. MACCFG2 Register Definition
Table 3-25. MACCFG2 Field Descriptions (continued)
3.6.3.4.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)
Figure 3-20. IPGIFG Register Definition
Table 3-26. IPGIFG Field Descriptions
3.6.3.4.4 Half-Duplex Register (HAFDUP)
Figure 3-21. Half-Duplex Register Definition
Table 3-27. HAFDUP Field Descriptions
3.6.3.4.5 Maximum Frame Length Register (MAXFRM)
Figure 3-22. Maximum Frame Length Register Definition
Table 3-28. MAXFRM Descriptions (continued)
3.6.3.4.6 MII Management Configuration Register (MIIMCFG)
Figure 3-23. MII Management Configuration Register Definition
Table 3-29. MIIMCFG Field Descriptions (continued)
3.6.3.4.7 MII Management Command Register (MIIMCOM)
Figure 3-24. MIIMCOM Register Definition
Table 3-30. MIIMCOM Descriptions
3.6.3.4.8 MII Management Address Register (MIIMADD)
Figure 3-25. MIIMADD Register Definition
Table 3-31. MIIMADD Field Descriptions
3.6.3.4.9 MII Management Control Register (MIIMCON)
Figure 3-26. MII Mgmt Control Register Definition
Table 3-32. MIIMCON Field Descriptions
3.6.3.4.10 MII Management Status Register (MIIMSTAT)
Figure 3-27. MIIMSTAT Register Definition
Table 3-33. MIIMSTAT Field Descriptions
3.6.3.4.11 MII Management Indicator Register (MIIMIND)
Figure 3-28. MII Mgmt Indicator Register Definition
Table 3-34. MIIMIND Field Descriptions
3.6.3.4.12 Interface Status Register (IFSTAT)
Figure 3-29. Interface Status Register Definition
Table 3-35. IFSTAT Field Descriptions
3.6.3.4.13 MAC Station Addresses
Figure 3-30. MAC Station Address Part 1 Register Definition
Table 3-36. MACSTNADDR1 Field Descriptions
Figure 3-31. MAC Station Address Part 2 Register Definition
Table 3-37. MACSTNADDR2 Field Descriptions
3.6.3.4.14 MAC Exact Match Address 1-15 Part 1 Registers (MAC01ADDR1-MAC15ADDR1)
Figure 3-32. MAC Exact Match Address n Part 1 Register Definition
Table 3-38. MACnADDR1 Field Descriptions
3.6.3.4.15 MAC Exact Match Address 1-15 Part 2 Registers (MAC01ADDR2-MAC15ADDR2)
Figure 3-33. MAC Exact Match Address x Part 2 Register Definition
Table 3-39. MAC01ADDR2-MAC15ADDR2 Field Descriptions
3.6.3.5 MIB Registers: Transmit and Receive Counters
3.6.3.5.1 Transmit and Receive 64-Byte Frame Counter (TR64)
Figure 3-34. Transmit and Receive 64-Byte Frame Register Definition
Table 3-40. TR64 Field Descriptions
3.6.3.5.2 Transmit and Receive 65- to 127-Byte Frame Counter (TR127)
Figure 3-35. Transmit and Receive 65- to 127-Byte Frame Register Definition
Table 3-41. TR127 Field Descriptions
3.6.3.5.3 Transmit and Receive 128- to 255-Byte Frame Counter (TR255)
Figure 3-36. Transmit and Received 128- to 255-Byte Frame Register Definition
Table 3-42. TR255 Field Descriptions
3.6.3.5.4 Transmit and Receive 256- to 511-Byte Frame Counter (TR511)
Figure 3-37. Transmit and Received 256- to 511-Byte Frame Register Definition
Table 3-43. TR511 Field Descriptions
3.6.3.5.5 Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K)
Figure 3-38. Transmit and Received 512- to 1023-Byte Frame Register Definition
Table 3-44. TR1K Field Descriptions
3.6.3.5.6 Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)
Figure 3-39. Transmit and Received 1024- to 1518-Byte Frame Register Definition
Table 3-45. TRMAX Field Descriptions
3.6.3.5.7 Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter (TRMGV)
Figure 3-40. Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition
Table 3-46. TRMGV Field Descriptions
3.6.3.5.8 Receive Byte Counter (RBYT)
Figure 3-41. Receive Byte Counter Register Definition
Table 3-47. RBYT Field Descriptions
3.6.3.5.9 Receive Packet Counter (RPKT)
Figure 3-42. Receive Packet Counter Register Definition
Table 3-48. RPKT Field Descriptions
3.6.3.5.10 Receive FCS Error Counter (RFCS)
Figure 3-43. Receive FCS Error Counter Register Definition
Table 3-49. RFCS Field Descriptions
3.6.3.5.11 Receive Multicast Packet Counter (RMCA)
Figure 3-44. Receive Multicast Packet Counter Register Definition
Table 3-50. RMCA Field Descriptions
3.6.3.5.12 Receive Broadcast Packet Counter (RBCA)
Figure 3-45. Receive Broadcast Packet Counter Register Definition
Table 3-51. RBCA Field Descriptions
3.6.3.5.13 Receive Control Frame Packet Counter (RXCF)
Figure 3-46. Receive Control Frame Packet Counter Register Definition
Table 3-52. RXCF Field Descriptions
3.6.3.5.14 Receive Pause Frame Packet Counter (RXPF)
Figure 3-47. Receive Pause Frame Packet Counter Register Definition
Table 3-53. RXPF Field Descriptions
3.6.3.5.15 Receive Unknown Opcode Packet Counter (RXUO)
Figure 3-48. Receive Unknown OPCode Packet Counter Register Definition
Table 3-54. RXUO Field Descriptions
3.6.3.5.16 Receive Alignment Error Counter (RALN)
Figure 3-49. Receive Alignment Error Counter Register Definition
Table 3-55. RALN Field Descriptions
3.6.3.5.17 Receive Frame Length Error Counter (RFLR)
Figure 3-50. Receive Frame Length Error Counter Register Definition
Table 3-56. RFLR Field Descriptions
3.6.3.5.18 Receive Code Error Counter (RCDE)
Figure 3-51. Receive Code Error Counter Register Definition
Table 3-57. RCDE Field Descriptions
3.6.3.5.19 Receive Carrier Sense Error Counter (RCSE)
Figure 3-52. Receive Carrier Sense Error Counter Register Definition
Table 3-58. RCSE Field Descriptions
3.6.3.5.20 Receive Undersize Packet Counter (RUND)
Figure 3-53. Receive Undersize Packet Counter Register Definition
Table 3-59. RUND Field Descriptions
3.6.3.5.21 Receive Oversize Packet Counter (ROVR)
Figure 3-54. Receive Oversize Packet Counter Register Definition
Table 3-60. ROVR Field Descriptions
3.6.3.5.22 Receive Fragments Counter (RFRG)
Figure 3-55. Receive Fragments Counter Register Definition
Table 3-61. RFRG Field Descriptions
3.6.3.5.23 Receive Jabber Counter (RJBR)
Figure 3-56. Receive Jabber Counter Register Definition
Table 3-62. RJBR Field Descriptions
3.6.3.5.24 Receive Dropped Packet Counter (RDRP)
Figure 3-57. Receive Dropped Packet Counter Register Definition
Table 3-63. RDRP Field Descriptions
3.6.3.5.25 Transmit Byte Counter (TBYT)
Figure 3-58. Transmit Byte Counter Register Definition
Table 3-64. TBYT Field Descriptions
3.6.3.5.26 Transmit Packet Counter (TPKT)
Figure 3-59. Transmit Packet Counter Register Definition
Table 3-65. TPKT Field Descriptions
3.6.3.5.27 Transmit Multicast Packet Counter (TMCA)
Figure 3-60. Transmit Multicast Packet Counter Register Definition
Table 3-66. TMCA Field Descriptions
3.6.3.5.28 Transmit Broadcast Packet Counter (TBCA)
Figure 3-61. Transmit Broadcast Packet Counter Register Definition
Table 3-67. TBCA Field Descriptions
3.6.3.5.29 Transmit Pause Control Frame Counter (TXPF)
Figure 3-62. Transmit Pause Control Frame Counter Register Definition
Table 3-68. TXPF Field Descriptions
3.6.3.5.30 Transmit Deferral Packet Counter (TDFR)
Figure 3-63. Transmit Deferral Packet Counter Register Definition
Table 3-69. TDFR Field Descriptions
3.6.3.5.31 Transmit Excessive Deferral Packet Counter (TEDF)
Figure 3-64. Transmit Excessive Deferral Packet Counter Register Definition
Table 3-70. TEDF Field Descriptions
3.6.3.5.32 Transmit Single Collision Packet Counter (TSCL)
Figure 3-65. Transmit Single Collision Packet Counter Register Definition
Table 3-71. TSCL Field Descriptions
3.6.3.5.33 Transmit Multiple Collision Packet Counter (TMCL)
Figure 3-66. Transmit Multiple Collision Packet Counter Register Definition
Table 3-72. TMCL Field Descriptions
3.6.3.5.34 Transmit Late Collision Packet Counter (TLCL)
Figure 3-67. Transmit Late Collision Packet Counter Register Definition
Table 3-73. TLCL Field Descriptions
3.6.3.5.35 Transmit Excessive Collision Packet Counter (TXCL)
Figure 3-68. Transmit Excessive Collision Packet Counter Register Definition
Table 3-74. TXCL Field Descriptions
3.6.3.5.36 Transmit Total Collision Counter (TNCL)
Figure 3-69. Transmit Total Collision Counter Register Definition
Table 3-75. TNCL Field Descriptions
3.6.3.5.37 Transmit Drop Frame Counter (TDRP)
Figure 3-70. Transmit Drop Frame Counter Register Definition
Table 3-76. TDRP Field Descriptions
3.6.3.5.38 Transmit Jabber Frame Counter (TJBR)
Figure 3-71. Transmit Jabber Frame Counter Register Definition
Table 3-77. TJBR Field Descriptions
3.6.3.5.39 Transmit FCS Error Counter (TFCS)
Figure 3-72. Transmit FCS Error Counter Register Definition
Table 3-78. TFCS Field Descriptions
3.6.3.5.40 Transmit Control Frame Counter (TXCF)
Figure 3-73. Transmit Control Frame Counter Register Definition
Table 3-79. TXCF Field Descriptions
3.6.3.5.41 Transmit Oversize Frame Counter (TOVR)
Figure 3-74. Transmit Oversized Frame Counter Register Definition
Table 3-80. TOVR Field Descriptions
3.6.3.5.42 Transmit Undersize Frame Counter (TUND)
Figure 3-75. Transmit Undersize Frame Counter Register Definition
Table 3-81. TUND Field Descriptions
3.6.3.5.43 Transmit Fragment Counter (TFRG)
Figure 3-76. Transmit Fragment Counter Register Definition
Table 3-82. TFRG Field Descriptions
3.6.3.5.44 Carry Register One (CAR1)
Figure 3-77. Carry Register One (CAR1) Register Definition
Table 3-83. CAR1 Field Descriptions (continued)
3.6.3.5.45 Carry Register Two (CAR2)
Figure 3-78. Carry Register Two (CAR2) Register Definition
Table 3-84. CAR2 Field Descriptions (continued)
3.6.3.5.46 Carry Mask Register One (CAM1)
Figure 3-79. Carry Mask Register One (CAM1) Register Definition
Table 3-85. CAM1 Field Descriptions
3.6.3.5.47 Carry Mask Register Two (CAM2)
Figure 3-80. Carry Mask Register Two (CAM2) Register Definition
Table 3-86. CAM2 Field Descriptions (continued)
3.6.4 Ten-Bit Interface (TBI)
3.6.4.1 TBI Transmit Process
3.6.4.1.1 Packet Encapsulation
3.6.4.1.2 8B10B Encoding
3.6.4.1.3 Preamble Shortening
3.6.4.2 TBI Receive Process
3.6.4.2.1 Synchronization
3.6.4.2.2 Auto-Negotiation for 1000BASE-X
3.6.4.3 TBI MII Set Register Descriptions
Table 3-87. TBI MII Register Set (continued)
3.6.4.3.1 Control Register (CR)
Figure 3-81. Control Register Definition
Table 3-88. CR Field Descriptions (continued)
3.6.4.3.2 Status Register (SR)
Figure 3-82. Status Register Definition
Table 3-89. SR Descriptions
3.6.4.3.3 AN Advertisement Register (ANA)
Figure 3-83. AN Advertisement Register Definition
Table 3-90. ANA Field Descriptions (continued)
Table 3-91. PAUSE Priority Resolution (continued)
3.6.4.3.4 AN Link Partner Base Page Ability Register (ANLPBPA)
Figure 3-84. AN Link Partner Base Page Ability Register Definition
Table 3-92. ANLPBPA Field Descriptions (continued)
3.6.4.3.5 AN Expansion Register (ANEX)
Figure 3-85. AN Expansion Register Definition
Table 3-93. ANEX Field Descriptions
3.6.4.3.6 AN Next Page Transmit Register (ANNPT)
Figure 3-86. AN Next Page Transmit Register Definition
Table 3-94. ANNPT Field Descriptions
3.6.4.3.7 AN Link Partner Ability Next Page Register (ANLPANP)
Figure 3-87. AN Link Partner Ability Next Page Register Definition
Table 3-95. ANLPANP Field Descriptions
3.6.4.3.8 Extended Status Register (EXST)
Figure 3-88. Extended Status Register Definition
Table 3-96. EXST Field Descriptions
3.6.4.3.9 Jitter Diagnostics Register (JD)
Figure 3-89. Jitter Diagnostics Register Definition
Table 3-97. JD Field Descriptions
3.6.4.3.10 TBI Control Register (TBICON)
Figure 3-90. TBI Control Register Definition
Table 3-98. TBICON Field Descriptions
3.7 dTSEC Functional Description
3.7.1 Connecting the dTSEC to Physical Interfaces on Ethernet
3.7.1.1 Reduced Media-Independent Interface (RMII)
Figure 3-91. dTSEC-RMII Connection
3.7.1.2 Reduced Gigabit Media-Independent Interface (RGMII)
Figure 3-92. P4080, P5020, P3041, P2040 dTSEC-RGMII Connection
Figure 3-93. P1023 dTSEC-RGMII Connection
3.7.1.3 Serial Gigabit Media-Independent Interface (SGMII)
Figure 3-94. dTSEC-SGMII Connection
3.7.1.4 Ethernet Physical Interfaces Signal Summary
Table 3-99. P1023 RMII Signalling (continued)
Table 3-100. P4080, P5020, P3041, P2040 RGMII Signalling (continued)
Table 3-101. P1023 RGMII Signalling
Table 3-102. SGMII Signalling
Table 3-103. Shared Signals
3.7.2 MAC Functionality
3.7.2.1 Configuring the MAC
3.7.2.2 Controlling CSMA/CD
3.7.2.3 Handling Packet Collisions
3.7.2.4 Controlling Packet Flow
3.7.2.5 Controlling PHY Links
3.7.3 Gigabit Ethernet Controller Channel Operation
3.7.3.1 Initialization Sequence
3.7.3.1.1 Hardware Controlled Initialization
3.7.3.1.2 User Initialization
Table 3-104. Steps for Minimum Register Initialization
3.7.3.2 Soft Reset and Reconfiguring Procedure
3.7.3.3 Gigabit Ethernet Frame Transmission
3.7.3.4 Gigabit Ethernet Frame Reception
3.7.3.5 Ethernet Preamble Customization
3.7.3.5.1 User-Defined Preamble Transmission
Figure 3-95. Definition of Custom Preamble Sequence.
Table 3-105. Custom Preamble Field Descriptions
3.7.3.5.2 User-Visible Preamble Reception
Figure 3-96. Definition of Received Preamble Sequence
Table 3-106. Received Preamble Field Descriptions
3.7.3.6 RMON Support
3.7.3.7 Frame Recognition
3.7.3.7.1 Destination Address Recognition and Frame Filtering
Figure 3-97. Ethernet Address Recognition Flowchart
3.7.3.7.2 Hash Table Algorithm
Figure 3-98. Sample C Code for Computing dTSEC Hash Table Indices
3.7.3.8 Magic Packet Mode
3.7.3.9 Flow Control
Table 3-107. Flow Control Frame Structure (continued)
3.7.3.10 Interrupt Handling
Table 3-99. General Interrupts
Table 3-100. Diagnostic Interrupts
Table 3-101. Error Interrupts
Table 3-102. Timer Interrupts
3.7.3.11 Inter-Frame Gap Time
3.7.3.12 Internal and External Loop Back
3.7.3.13 Error-Handling Procedure
Table 3-108. Transmission Errors
Table 3-109. Reception Errors
Table 3-110. Timer Error
3.8 dTSEC Initialization/Application Information
3.8.1 Interface Mode Configuration
3.8.1.1 RGMII Interface Mode
Table 3-111. P4080, P5020, P3041, P2040 RGMII Interface Mode Signal Configuration (continued)
Table 3-112. P1023 RGMII Interface Mode Signal Configuration (continued)
Table 3-113. Shared RGMII Signals
Table 3-114. RGMII Mode Register Initialization Steps (continued)
3.8.1.2 RMII Interface Mode
Table 3-115. P1023 RMII Interface Mode Signal Configuration
Table 3-116. P1023 Shared RMII Signals
Table 3-117. P1023 RMII Mode Register Initialization Steps (continued)
3.8.1.3 SGMII Interface Support
Table 3-118. SGMII Interface Signal Configuration (4-Wire)
Table 3-119. SGMII Mode Register Initialization Steps (continued)
3.8.2 Hardware Assist for IEEE Std 1588-Compliant Time-Stamping
3.8.2.1 IEEE 1588 dTSEC Time-Stamping Features Summary
3.8.2.2 Time-Stamp Inline Insertion on Receive Packets
3.8.2.2.1 Required Time-Stamp Point
Figure 3-103. Ethernet Sampling Points for 1588
3.8.2.3 Time-Stamps For Transmit Packets
3.8.2.4 Time-Stamp Latency
Table 3-120. Time-Stamp Latency
3.8.2.5 Timer Soft Reset Procedure
Chapter 4 10-Gigabit Ethernet Media Access Controller (10GEC)
4.1 10GEC Overview
Figure 4-1. 10 Gigabit Ethernet Block Diagram
4.2 10GEC Features Summary
4.3 10GEC External Signals Descriptions
Table 4-1. 10-gigabit Ethernet Network Interface Signals
4.3.1 10GEC Detailed Signal Descriptions
Table 4-2. 10-gigabit Ethernet Signals-Detailed Signal Descriptions
4.4 10GEC Memory Map/Register Definition
4.4.1 10GEC Top-Level Memory Map
Table 4-3. 10-gigabit Ethernet MAC Memory Map Summary
Table 4-4. 10-gigabit Ethernet Management Interface Memory Map Summary
4.4.2 10GEC Detailed Memory Map
Table 4-5. Module Memory Map
4.4.3 10GEC Memory-Mapped Register Descriptions
4.4.3.1 10GEC General Control and Status Registers
4.4.3.1.1 10-gigabit Ethernet MAC Controller ID (EC10G_ID)
Figure 4-2. 10-gigabit Ethernet MAC Controller ID (EC10G_ID)
Table 4-6. EC10G_ID Field Descriptions
4.4.3.1.2 Command and Configuration Register (COMMAND_CONFIG)
Figure 4-3. Command and Configuration Register (COMMAND_CONFIG)
Table 4-7. COMMAND_CONFIG Field Descriptions
4.4.3.1.3 First MAC Lower Address Register (MAC_ADDR_0)
Figure 4-4. First MAC Lower Address Register (MAC_ADDR_0)
Table 4-8. MAC_ADDR_0 Field Descriptions
4.4.3.1.4 First MAC Upper Address Register (MAC_ADDR_1)
Figure 4-5. First MAC Upper Address Register (MAC_ADDR_1
Table 4-9. MAC_ADDR_1 Field Descriptions
4.4.3.1.5 Maximum Frame Length Register (MAXFRM)
Figure 4-6. Maximum Frame Length Register (MAXFRM)
Table 4-10. MAXFRM Field Descriptions
4.4.3.1.6 Pause Quanta Register (PAUSE_QUANT)
Figure 4-7. Pause Quanta Register (PAUSE_QUANT)
Table 4-11. PAUSE_QUANT Field Descriptions
4.4.3.1.7 Hashtable Control Register (HASHTABLE_CTRL)
Figure 4-8. HASHTABLE_CTRL Register Definition
Table 4-12. HASHTABLE_CTRL Field Descriptions
4.4.3.1.8 MAC Status Register (STATUS)
Figure 4-9. MAC Status Register (STATUS
Table 4-13. STATUS Field Descriptions
4.4.3.1.9 Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH)
Figure 4-10. Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH)
Table 4-14. TX_IPG_LENGTH Field Descriptions
4.4.3.1.10 Second MAC Lower Address Register (MAC_ADDR_2)
Figure 4-11. Second MAC Lower Address Register (MAC_ADDR_2)
Table 4-15. MAC_ADDR_2 Field Descriptions
4.4.3.1.11 Second MAC Upper Address Register (MAC_ADDR_3)
Figure 4-12. Second MAC Upper Address Register (MAC_ADDR_3)
Table 4-16. MAC_ADDR_3 Field Descriptions
4.4.3.1.12 Interrupt Mask Register (IMASK)
Figure 4-13. Interrupt Mask Register (IMASK)
Table 4-17. IMASK Field Descriptions
4.4.3.1.13 Interrupt Event Register (IEVENT)
Figure 4-14. Interrupt Event Register (IEVENT)
Table 4-18. IEVENT Field Descriptions
4.4.3.2 10GEC Statistics Counter Registers
4.4.3.2.1 Transmit Frame Counter Register (TFRMn)
Figure 4-15. Transmit Frame Counter Register (TFRMn)
Table 4-19. TFRMn Field Description
4.4.3.2.2 Receive Frame Counter Register (RFRMn)
Figure 4-16. Receive Frame Counter Register (RFRMn)
Table 4-20. RFRMn Field Description
4.4.3.2.3 Receive Frame Check Sequence Error Counter Register (RFCSn)
Figure 4-17. Receive Frame Check Sequence Error Counter Register (RFCSn)
Table 4-21. RFCSn Field Description
4.4.3.2.4 Receive Alignment Error Counter Register (RALNn)
Figure 4-18. Receive Alignment Error Counter Register (RALNn)
Table 4-22. RALNn Field Description
4.4.3.2.5 Transmit Valid Pause Frame Counter Register (TXPFn)
Figure 4-19. Transmit Valid Pause Frame Counter Register (TXPFn)
Table 4-23. TXPFn Field Description
4.4.3.2.6 Receive Valid Pause Frame Counter Register (RXPFn)
Figure 4-20. Receive Valid Pause Frame Counter Register (RXPFn)
Table 4-24. RXPFn Field Description
4.4.3.2.7 Receive Frame Too Long Error Counter Register (RLONGn)
Figure 4-21. Receive Frame Too Long Error Counter Register (RLONGn)
Table 4-25. RLONGn Field Description
4.4.3.2.8 Receive Frame Length Error Counter Register (RFLRn)
Figure 4-22. Receive Frame Length Error Counter Register (RFLRn)
Table 4-26. RFLRn Field Description
4.4.3.2.9 Transmit VLAN Frame Counter Register (TVLANn)
Figure 4-23. Transmit VLAN Frame Counter Register (TVLANn)
Table 4-27. TVLANn Field Description
4.4.3.2.10 Receive VLAN Frame Counter Register (RVLANn)
Figure 4-24. Receive VLAN Frame Counter Register (RVLANn)
Table 4-28. RVLANn Field Description
4.4.3.2.11 Transmit Octets Counter Register (TOCTn)
Figure 4-25. Transmit Octets Counter Register (TOCTn)
Table 4-29. TOCTn Field Description
4.4.3.2.12 Receive Octets Counter Register (ROCTn)
Figure 4-26. Receive Octets Counter Register (ROCTn)
Table 4-30. ROCTn Field Description
4.4.3.2.13 Receive Unicast Frame Counter Register (RUCAn)
Figure 4-27. Receive Unicast Frame Counter Register (RUCAn)
Table 4-31. RUCAn Field Description
4.4.3.2.14 Receive Multicast Frame Counter Register (RMCAn)
Figure 4-28. Receive Multicast Frame Counter Register (RMCAn)
Table 4-32. RMCAn Field Description
4.4.3.2.15 Receive Broadcast Frame Counter Register (RBCAn)
Figure 4-29. Receive Broadcast Frame Counter Register (RBCAn)
Table 4-33. RBCAn Field Description
4.4.3.2.16 Transmit Frame Error Counter Register (TERRn)
Figure 4-30. Transmit Frame Error Counter Register (TERRn)
Table 4-34. TERRn Field Description
4.4.3.2.17 Transmit Unicast Frame Counter Register (TUCAn)
Figure 4-31. Transmit Unicast Frame Counter Register (TUCAn)
Table 4-35. TUCAn Field Description
4.4.3.2.18 Transmit Multicast Frame Counter Register (TMCAn)
Figure 4-32. Transmit Multicast Frame Counter Register (TMCAn)
Table 4-36. TMCAn Field Description
4.4.3.2.19 Transmit Broadcast Frame Counter Register (TBCAn)
Figure 4-33. Transmit Broadcast Frame Counter Register (TBCAn)
Table 4-37. TBCAn Field Description
4.4.3.2.20 Receive Dropped Packets Counter Register (RDRPn)
Figure 4-34. Receive Dropped Packets Counter Register (RDRPn)
Table 4-38. RDRPn Field Description
4.4.3.2.21 Receive Ethernet Octets Counter (REOCTn)
Figure 4-35. Receive Ethernet Octets Counter (REOCTn)
Table 4-39. REOCTn Field Description
4.4.3.2.22 Receive Packets Counter Register (RPKTn)
Figure 4-36. Receive Packets Counter Register (RPKTn)
Table 4-40. RPKTn Field Description
4.4.3.2.23 Undersized Packet Counter Register (TRUNDn)
Figure 4-37. Undersized Packet Counter Register (TRUNDn)
Table 4-41. TRUNDn Field Description
4.4.3.2.24 Receive 64-Octet Packet Counter Register (R64n)
Figure 4-38. Receive 64-Octet Packet Counter Register (R64n)
Table 4-42. R64n Field Description
4.4.3.2.25 Receive 65- to 127-Octet Packet Counter Register (R127n)
Figure 4-39. Receive 65- to 127-Octet Packet Counter Register (R127n)
Table 4-43. R127n Field Description
4.4.3.2.26 Receive 128- to 255-Octet Packet Counter Register (R255n)
Figure 4-40. Receive 128- to 255-Octet Packet Counter Register (R255n)
Table 4-44. R255n Field Description
4.4.3.2.27 Receive 256- to 511-Octet Packet Counter Register (R511n)
Figure 4-41. Receive 256- to 511-Octet Packet Counter Register (R511n)
Table 4-45. R511n Field Description
4.4.3.2.28 Receive 512- to 1023-Octet Packet Counter Register (R1023n)
Figure 4-42. Receive 512- to 1023-Octet Packet Counter Register (R1023n)
Table 4-46. R1023n Field Description
4.4.3.2.29 Receive 1024- to 1518-Octet Packet Counter Register (R1518n)
Figure 4-43. Receive 1024- to 1518-Octet Packet Counter Register (R1518n)
Table 4-47. R1518n Field Description
4.4.3.2.30 Receive 1519- to Max-Octet Packet Counter Register (R1519Xn)
Figure 4-44. Receive 1519- to Max-Octet Packet Counter Register (R1519Xn)
Table 4-48. R1519Xn Field Description
4.4.3.2.31 Oversized Packet Counter Register (TROVRn)
Figure 4-45. Oversized Packet Counter Register (TROVRn)
Table 4-49. TROVRn Field Description
4.4.3.2.32 Jabber Packet Counter Register (TRJBRn)
Figure 4-46. Jabber Packet Counter Register (TRJBRn)
Table 4-50. TRJBRn Field Description
4.4.3.2.33 Fragment Packet Counter Register (TRFRGn)
Figure 4-47. Fragment Packet Counter Register (TRFRGn)
Table 4-51. TRFRGn Field Description
4.4.3.2.34 Receive Frame Error Counter Register (RERRn)
Figure 4-48. Receive Frame Error Counter Register (RERRn)
Table 4-52. RERRn Field Description
4.4.3.3 MDIO Ethernet Management Interface Registers
4.4.3.3.1 MDIO Configuration and Status Register (MDIO_CFG_STAT)
Figure 4-49. MDIO_CFG_STAT Register Definition
Table 4-53. MDIO_CFG_STAT Field Descriptions
4.4.3.3.2 MDIO Control Register (MDIO_CTL)
Figure 4-50. MDIO_CTL Register Definition
Table 4-54. MDIO_CLT Field Descriptions
4.4.3.3.3 MDIO Data Register (MDIO_DATA)
Figure 4-51. MDIO_DATA Register Definition
Table 4-55. MDIO_DATA Field Descriptions
4.4.3.3.4 MDIO Register Address Register (MDIO_ADDR)
Figure 4-52. MDIO_ADDR Register Definition
Table 4-56. MDIO_ADDR Field Descriptions
4.5 10GEC Functional Description
4.5.1 MAC Address Insertion
4.5.2 CRC-32 Calculation
4.5.3 IEEE 1588 Timestamping Latency
Table 4-57. Time-Stamp Latency
Chapter 5 IEEE 1588 Timer Module
5.1 1588 Timer Features Summary
5.2 1588 Timer Modes of Operation
5.3 1588 Timer External Signals Description
Table 5-1. 1588 Timer External Interface Signal Summary
5.3.1 1588 Timer Detailed Signal Descriptions
Table 5-2. 1588 Timer-Detailed Signal Descriptions
5.4 1588 Timer Memory Map/Register Definition
5.4.1 1588 Timer Top-Level Module Memory Map
Table 5-3. Module Memory Map Summary
5.4.2 1588 Timer Detailed Memory Map
Table 5-4. Module Memory Map
5.4.3 1588 Timer Memory-Mapped Register Descriptions
5.4.3.1 General Control and Status Registers
5.4.3.1.1 Module ID Register (TMR_ID)
Figure 5-1. Module ID Register (TMR_ID)
Table 5-5. TMR_ID Field Descriptions
5.4.3.1.2 Controller ID Register (TMR_ID2)
Figure 5-2. Controller ID Register (TMR_ID2)
Table 5-3. dTSEC_ID2 Field Descriptions
5.4.3.2 Hardware Assist for IEEE 1588 Compliant Timestamping
5.4.3.2.1 Timer Control Register (TMR_CTRL)
Figure 5-4. Timer Control Register (TMR_CTRL)
Table 5-6. TMR_CTRL Register Field Descriptions
5.4.3.2.2 Timer Event Register (TMR_TEVENT)
Figure 5-5. Timer Event Register (TMR_TEVENT)
Table 5-7. TMR_TEVENT Register Field Descriptions
5.4.3.2.3 Timer Event Mask Register (TMR_TEMASK)
Figure 5-6. Timer Event Mask Register (TMR_TEMASK)
Table 5-8. TMR_TEMASK Field Descriptions
5.4.3.2.4 Timer Counter Register (TMR_CNT_H/L)
Figure 5-7. Timer Counter Register (TMR_CNT_H/L)
Table 5-9. TMR_CNT_H/L Register Field Descriptions
5.4.3.2.5 Timer Drift Compensation Addend Register (TMR_ADD)
Figure 5-8. TMR_CNT_H Register Definition
Table 5-10. TMR_ADD Register Field Descriptions
5.4.3.2.6 Timer Accumulator Register (TMR_ACC)
Figure 5-9. Timer Accumulator Register (TMR_ACC)
Table 5-11. TMR_ACC Register Field Descriptions
5.4.3.2.7 Timer Prescale Register (TMR_PRSC)
Figure 5-10. Timer Prescale Register (TMR_PRSC)
Table 5-12. TMR_PRSC Field Descriptions
5.4.3.2.8 Timer Offset Registers (TMROFF_H/L)
Figure 5-11. Timer Offset Registers (TMROFF_H/L)
Table 5-13. TMROFF_H/L Field Descriptions
5.4.3.2.9 Alarm Time Comparator Register 1-2 (TMR_ALARMn_H/L)
Figure 5-12. Alarm Time Comparator Register 1-2 (TMR_ALARMn_H/L)
Table 5-14. TMR_ALARMn_H/L Field Descriptions
5.4.3.2.10 Timer Fixed Interval Period Registers (TMR_FIPERn)
Figure 5-13. Timer Fixed Interval Period Registers (TMR_FIPERn)
Table 5-15. TMR_FIPERn Field Descriptions
5.4.3.2.11 External Trigger Stamp Registers 1-2 (TMR_ETTSn_H/L)
Figure 5-14. External Trigger Stamp Registers 1-2 (TMR_ETTSn_H/L)
Table 5-16. TMR_ETTSn_H Field Descriptions
5.5 1588 Timer Initialization/Application Information
5.5.1 Initialization Sequence
5.5.1.1 Hardware Controlled Initialization
5.5.1.2 User Initialization
5.5.2 Soft Reset and Reconfiguring Procedure
5.5.3 Interrupt Handling
Table 5-17. 1588 IP Interrupts
5.5.4 Hardware Assist for IEEE Std. 1588 Compliant Timestamping
Figure 5-15. Current Time Control
5.5.4.1 Time-Stamping of Packets
5.5.4.2 Precision Time Protocol (PTP) Packets
Table 5-18. PTP Payload Special Fields
Figure 5-16. PTP Packet Format
5.5.4.3 Time-Stamps For External Trigger
Chapter 6 Queue Manager (QMan)
6.1 QMan Introduction
6.1.1 QMan Overview
Figure 6-1. QMan Overview Block Diagram
6.1.2 QMan Features
6.2 QMan Memory Map and Register Definition
6.2.1 QMan Software Portals (QCSP) Memory Map
Table 6-1. QMan Software Portals (QCSP) Memory Map
6.2.2 QMan Configuration and Control Register Memory Map
Table 6-2. QMan Configuration and Control Register Memory Map
6.2.3 QMan Software Portals (QCSP) Register Descriptions
6.2.3.1 QCSP Enqueue Command Ring Registers (QCSPi_EQCR0-7)
Figure 6-2. QCSP Enqueue Command Ring Registers (QCSPi_EQCR0-7)
Table 6-3. QCSPi_EQCR0-7 Field Descriptions
6.2.3.2 QCSP Dequeue Response Ring Registers (QCSPi_DQRR0-15)
Figure 6-3. QCSP Dequeue Response Ring Registers (QCSPi_DQRR0-15) (Entries 0 to 7)
Figure 6-4. QCSP Dequeue Response Ring Registers (QCSPi_DQRR0-15) (Entries 8 to 15)
Table 6-4. QCSPi_DQRR0-15 Field Descriptions
6.2.3.3 QCSP Message Ring Registers (QCSPi_MR0-7)
Figure 6-5. QCSP Message Ring Registers (QCSPi_MR0-7)
Table 6-5. QCSPi_MR0-7 Field Descriptions
6.2.3.4 QCSP Management Command Registers (QCSPi_CR)
Figure 6-6. QSCP Management Command Registers (QCSPi_CR)
Table 6-6. QCSPi_CR Field Descriptions
6.2.3.5 QCSP Management Response Registers (QCSPi_RR0-1) Format
Figure 6-7. QCSP Management Response Register 0 (QCSPi_RR0)
Figure 6-8. QCSP Management Response Register 1 (QCSPi_RR1)
Table 6-7. QCSPi_RR0-1 Field Descriptions
6.2.3.6 QCSP Enqueue Command Ring (EQCR) Producer Index Registers
6.2.3.6.1 QCSP EQCR Producer Index Cache-Enabled Registers (QCSPi_EQCR_PI_CENA)
Figure 6-9. QCSP EQCR Producer Index Registers (QCSPi_EQCR_PI_CENA)
Table 6-8. QCSPi_EQCR_PI_CENA Field Descriptions
6.2.3.6.2 QCSP EQCR Producer Index Cache-Inhibited Registers (QCSPi_EQCR_PI_CINH)
Figure 6-10. QCSP EQCR Producer Index Register (QCSPi_EQCR_PI_CINH)
Table 6-9. QCSPi_EQCR_PI_CINH Field Descriptions
6.2.3.7 QCSP EQCR Consumer Index Registers
6.2.3.7.1 QCSP EQCR Consumer Index Cache-Enabled Registers (QCSPi_EQCR_CI_CENA)
Figure 6-11. QCSP EQCR Consumer Index Register (QCSPi_EQCR_CI_CENA)
Table 6-10. QCSPi_EQCR_CI_CENA Field Descriptions
6.2.3.7.2 QCSP EQCR Consumer Index Cache-Inhibited Registers (QCSPi_EQCR_CI_CINH)
Figure 6-12. QCSP EQCR Consumer Index Register (QCSPi_EQCR_CI_CINH)
Table 6-11. QCSPi_EQCR_CI_CINH Field Descriptions
6.2.3.8 QCSP Dequeue Response Ring (DQRR) Producer Index Registers
6.2.3.8.1 QCSP DQRR Producer Index Cache-Enabled Registers (QCSPi_DQRR_PI_CENA)
Figure 6-13. QCSP DQRR Producer Index Register (DQRRi_PI_CENA)
Table 6-12. QCSPi_DQRR_PI_CENA Field Descriptions
6.2.3.8.2 QCSP DQRR Producer Index Cache-Inhibited Registers (QCSPi_DQRR_PI_CINH)
Figure 6-14. QCSP DQRR Producer Index Cache-Inhibited Registers (QCSPi_DQRR_PI_CINH)
Table 6-13. QCSPi_DQRR_PI_CINH Field Descriptions
6.2.3.9 QCSP DQRR Consumer Index Registers (QCSPi_DQRR_CI_CENA)
6.2.3.9.1 QCSP DQRR Consumer Index Cache-Enabled Registers (QCSPi_DQRR_CI_CENA)
Figure 6-15. QCSP DQRR Consumer Index Cache-Enabled Registers (QCSPi_DQRR_CI_CENA)
Table 6-14. QCSPi_DQRR_CI_CENA Field Descriptions
6.2.3.9.2 QCSP DQRR Consumer Index Cache-Inhibited Registers (QCSPi_DQRR_CI_CINH)
Figure 6-16. QCSP DQRR Consumer Index Cache-Inhibited Registers (QCSPi_DQRR_CI_CINH)
Table 6-15. QCSPi_DQRR_CI_CINH Field Descriptions
6.2.3.10 QCSP DQRR Discrete Consumption Acknowledgment and Park (QCSPi_DQRR_DCAP)
Figure 6-17. DQRR Discrete Consumption Acknowledgment Register (QCSPi_DQRR_DCAP)
Table 6-16. QCSPi_DQRR_DCAP Field Descriptions
6.2.3.11 QCSP DQRR Static Dequeue Command Register (SDQCR)
Figure 6-18. QCSP DQRR Static Dequeue Command Register (QCSPi_DQRR_SDQCR)
Table 6-17. QCSPi_DQRR_SDQCR Field Descriptions
6.2.3.12 QCSP DQRR Volatile Dequeue Command Register (QCSPi_DQRR_VDQCR)
Figure 6-19. QCSO DQRR Volatile Dequeue Command Register (QCSPi_DQRR_VDQCR)
Table 6-18. QCSPi_DQRR_VDQCR Field Descriptions
6.2.3.13 QCSP DQRR Pull Dequeue Command Register (QSCPi_DQRR_PDQCR)
Figure 6-20. QCSP DQRR Pull Dequeue Command Register (QSCPi_DQRR_PDQCR)
Table 6-19. QCSPi_DQRR_PDQCR Field Descriptions
6.2.3.14 QCSP MR Producer Index Registers
6.2.3.14.1 QCSP MR Producer Index Cache-Enabled Registers (QCSPi_MR_PI_CENA)
Figure 6-21. QCSP MR Producer Index Cache-Enabled Registers (QCSPi_MR_PI_CENA)
Table 6-20. QCSPi_MR_PI_CENA Field Descriptions
6.2.3.14.2 QCSP MR Producer Index Cache-Inhibited Registers (QCSPi_MR_PI_CINH)
Figure 6-22. QCSP MR Producer Index Cache-Inhibited Registers (QCSPi_MR_PI_CINH)
Table 6-21. QCSPi_MR_PI_CINH Field Descriptions
6.2.3.15 QCSP MR Consumer Index Registers
6.2.3.15.1 QCSP MR Consumer Index Cache-Enabled Registers (QCSPi_MR_CI_CENA)
Figure 6-23. QCSP MR Consumer Index Cache-Enabled Registers (QCSPi_MR_CI_CENA)
Table 6-22. QCSPi_MR_CI_CENA Field Descriptions
6.2.3.15.2 QCSP MR Consumer Index Cache-Inhibited Registers (QCSPi_MR_CI_CINH)
Figure 6-24. QCSP MR Consumer Index Cache-Inhibited Registers (QCSPi_MR_CI_CINH)
Table 6-23. QCSPi_MR_CI_CINH Field Descriptions
6.2.3.16 QCSP Read-Only Ring Indices Cache-Enabled Registers (QCSPi_RORI_CENA)
Figure 6-25. QCSP Read-Only Ring Indices Cache-Enabled Registers (QCSPi_RORI_CENA)
Table 6-24. QCSPi_RORI_CENA Field Descriptions
6.2.3.17 QMan Software Portal Configuration Register (QCSPi_CFG)
Figure 6-26. QCSP Configuration Register (QCSPi _CFG)
Table 6-25. QCSPi_CFG Field Descriptions
6.2.3.18 QCSP EQCR Interrupt Threshold Register (QCSPi_EQCR_ITR)
Figure 6-27. QCSP EQCR Interrupt Threshold Register (QCSPi_EQCR_ITR)
Table 6-26. QCSPi_EQCR_ITR Field Descriptions
6.2.3.19 QCSP DQRR Interrupt Threshold Register (QCSPi_DQRR_ITR)
Figure 6-28. QCSP DQRR Interrupt Threshold Register (QCSPi_DQRR_ITR)
Table 6-27. QCSPi_DQRR_ITR Field Descriptions
6.2.3.20 QCSP MR Interrupt Threshold Register (QCSPi_MR_ITR)
Figure 6-29. QCSP MR Interrupt Threshold Register (QCSPi_MR_ITR)
Table 6-28. QCSPi_MR_ITR Field Descriptions
6.2.3.21 QCSP Interrupt Status Register (QCSPi_ISR)
Figure 6-30. QCSP Interrupt Status Register (QCSPi_ISR)
Table 6-29. QCSPi_ISR Field Descriptions
6.2.3.22 QCSP Interrupt Enable Registers (QCSPi_IER)
Figure 6-31. QCSP Interrupt Enable Register (QCSPi_IER)
Table 6-30. QCSPi_IER Field Descriptions
6.2.3.23 QCSP Interrupt Status Disable Registers (QCSPi_ISDR)
Figure 6-32. QCSP Interrupt Enable Registers (QCSPi_IER)
Table 6-31. QCSPi_ISDR Field Descriptions
6.2.3.24 QCSP Interrupt Inhibit Registers (QCSPi_IIR)
Figure 6-33. QCSP Interrupt Inhibit Register (QCSPi_IIR)
Table 6-32. QCSPi_IIR Field Descriptions
6.2.3.25 QCSP Interrupt Time-Out Period Registers (QCSPi_ITPR)
Figure 6-34. QCSP Interrupt Time Out Period Registers (QCSPi_ITPR)
Table 6-33. QCSPi_ITPR Field Descriptions
6.2.4 QMan Configuration and Control Register Descriptions
6.2.4.1 QCSP LIO Configuration Registers (QCSPi_LIO_CFG)
Figure 6-35. QCSP LIO Configuration (QCSPi_LIO_CFG)
Table 6-34. QCSPi_LIO_CFG Field Descriptions
6.2.4.2 QCSP IO Configuration Registers (QCSPi_IO_CFG)
Figure 6-36. QCSP IO Configuration Registers (QCSPi_IO_CFG)
Table 6-35. QCSPi_IO_CFG Field Descriptions
6.2.4.3 QCSP Dynamic Debug Configuration Registers (QCSPi_DD_CFG)
Figure 6-37. QCSP Dynamic Debug Configuration Registers (QCSPi_DD_CFG)
Table 6-36. QCSPi_DD_CFG Field Descriptions
6.2.4.4 QMan Dynamic Debug Configuration Register (QMAN_DD_CFG)
Figure 6-38. QMan Dynamic Debug Configuration Register (QMAN_DD_CFG)
Table 6-37. QMAN_DD_CFG Field Descriptions
6.2.4.5 QCSP Dynamic Debug Internal Halt Request Status Register (QCSP_DD_IHRSR)
Figure 6-39. QCSP Dynamic Debug Internal Halt Request Status Register (QCSP_DD_IHRSR)
Table 6-38. QCSP_DD_IHRSR Field Descriptions
6.2.4.6 DCP Dynamic Debug Internal Halt Request Status Register (DCP_DD_IHRSR)
Figure 6-40. DCP Dynamic Debug Internal Halt Request Status Register (DCP_DD_IHRSR)
Table 6-39. DCP_DD_IHRSR Field Descriptions
6.2.4.7 QCSP Dynamic Debug Internal Halt Request Force Register (QCSP_DD_IHRFR)
Figure 6-41. QCSP Dynamic Debug Internal Halt Request Force Register (QCSP_DD_IHRFR)
Table 6-40. QCSP_DD_IHRFR Field Descriptions
6.2.4.8 DCP Dynamic Debug Internal Halt Request Force Register (DCP_DD_IHRFR)
Figure 6-42. DCP Dynamic Debug Internal Halt Request Force Register (DCP_DD_IHRFR)
Table 6-41. DCP_DD_IHRFR Field Descriptions
6.2.4.9 QCSP Dynamic Debug Halt Acknowledge Status Register (QCSP_DD_HASR)
Figure 6-43. QCSP Dynamic Debug Halt Acknowledge Status Register (QCSP_DD_HASR)
Table 6-42. QCSP_DD_HASR Field Descriptions
6.2.4.10 DCP Dynamic Debug Halt Acknowledge Status Register (DCP_DD_HASR)
Figure 6-44. DCP Dynamic Debug Halt Acknowledge Status Register (DCP_DD_HASR)
Table 6-43. DCP_DD_HASR Field Descriptions
6.2.4.11 DCP Configuration Registers (DCPi_CFG)
Figure 6-45. DCP Configuration Registers (DCPi_CFG)
Table 6-44. DCPi_CFG Field Descriptions
6.2.4.12 DCP Dynamic Debug Configuration Registers (DCPi_DD_CFG)
Figure 6-46. DCP Dynamic Debug Configuration Registers (DCPi_DD_CFG)
Table 6-45. DCPi_DD_CFG Field Descriptions
6.2.4.13 DCP Dequeue Latency Monitor Configuration Registers (DCPi_DLM_CFG)
Figure 6-47. DCP Dequeue Latency Monitor Configuration (DCPi_DLM_CFG)
Table 6-46. DCPi_DLM_CFG Field Descriptions
6.2.4.14 DCP Dequeue Latency Monitor Average Registers (DCPi_DLM_AVG)
Figure 6-48. DCP Dequeue Latency Monitor Average Registers (DCPi_DLM_AVG)
Table 6-47. DCPi_DLM_AVG Field Descriptions
6.2.4.15 PFDR Free Pool Count Register (PFDR_FPC)
Figure 6-49. PFDR Free Pool Count Register (PFDR_FPC)
Table 6-48. PFDR_FPC Field Descriptions
6.2.4.16 PFDR Free Pool Head Pointer Register (PFDR_FP_HEAD)
Figure 6-50. PFDR Free Pool Head Pointer Register (PFDR_FP_HEAD)
Table 6-49. PFDR_FP_HEAD Field Descriptions
6.2.4.17 PFDR Free Pool Tail Pointer Register (PFDR_FP_TAIL)
Figure 6-51. PFDR Free Pool Tail Pointer Register (PFDR_FP_TAIL)
Table 6-50. PFDR_FP_TAIL Field Descriptions
6.2.4.18 PFDR Free Pool Low Watermark Interrupt Threshold (PFDR_FP_LWIT)
Figure 6-52. PFDR Free Pool Low Watermark Interrupt Threshold (PFDR_FP_LWIT)
Table 6-51. Register PFDR_FP_LWIT Field Descriptions
6.2.4.19 PFDR Configuration (PFDR_CFG)
Figure 6-53. PFDR Configuration (PFDR_CFG)
Table 6-52. Register PFDR_CFG Field Descriptions
6.2.4.20 SFDR Configuration Register (SFDR_CFG)
Figure 6-54. SFDR Configuration Register (SFDR_CFG)
Table 6-53. SFDR_CFG Field Descriptions
6.2.4.21 SFDR In Use Register (SFDR_IN_USE)
Figure 6-55. SFDR In Use Register (SFDR_IN_USE)
Table 6-54. SFDR_IN_USE Field Descriptions
6.2.4.22 Work Queue Class Scheduler Configuration Registers (WQ_CS_CFGi)
Figure 6-56. Work Queue Class Scheduler Configuration (WQ_CS_CFGi)
Table 6-55. WQ_CS_CFGi Field Descriptions
6.2.4.23 WQ Default Enqueue WQID Register (WQ_DEF_ENQ_WQID)
Figure 6-57. WQ Default Enqueue WQID Register (WQ_DEF_ENQ_WQID)
Table 6-56. WQ_DEF_ENQ_WQID Field Descriptions
6.2.4.24 WQ Channel Dynamic Debug Configuration Registers
6.2.4.24.1 WQ Channel Software Portal Dynamic Debug Configuration Registers (WQ_SC_DD_CFG_i)
Figure 6-58. WQ Channel Software Portal Dynamic Debug Configuration Registers (WQ_SC_DD_CFG_i)
Table 6-57. WQ_SC_DD_CFG_i Field Descriptions
6.2.4.24.2 WQ Channel Pool Dynamic Debug Configuration Registers (WQ_PC_DD_CFG_i)
Figure 6-59. WQ Channel Pool Dynamic Debug Configuration Registers (WQ_PC_DD_CFG_i)
Table 6-58. WQ_PC_DD_CFG_i Field Descriptions
6.2.4.24.3 WQ Channel DCP Dynamic Debug Configuration Registers (WQ_DCx_DD_CFG_i)
Figure 6-60. WQ Channel DCP Dynamic Debug Configuration Registers (WQ_DCx_DD_CFG_i)
Table 6-59. WQ_DCx_DD_CFG_i Field Descriptions
6.2.4.25 CM Configuration Register (CM_CFG)
Figure 6-61. CM Configuration Register (CM_CFG)
Table 6-60. CM_CFG Field Descriptions
6.2.4.26 QMan Error Capture Status Register (QMAN_ECSR)
Figure 6-62. QMan Error Capture Status Register (QMAN_ECSR)
Table 6-61. QMAN_ECSR Field Descriptions
6.2.4.27 QMan Error Capture Information Register (QMAN_ECIR)
Figure 6-63. QMan Error Capture Information Register (QMAN_ECIR)
Table 6-62. QMAN_ECIR Field Descriptions
6.2.4.28 QMan ECC Error Address Register (QMAN_EADR)
Figure 6-64. QMan Error Address Register (QMAN_EADR)
Table 6-63. QMAN_EADR Field Descriptions
6.2.4.29 QMan ECC Error Data Registers (QMAN_EDATAi)
Figure 6-65. QMan Error Data Registers (QMAN_EDATAi)
Table 6-64. QMAN_EDATAi Field Descriptions
6.2.4.30 QMan Single-Bit ECC Error Threshold Register (QMAN_SBET)
Figure 6-66. QMan Single Bit Error Threshold Register (QMAN_SBET)
Table 6-65. QMAN_SBET Field Descriptions
6.2.4.31 QMan Single Bit ECC Error Count Registers (QMAN_SBECi)
Figure 6-67. QMan Single Bit Error Count Registers (QMAN_SBECi)
Table 6-66. QMAN_SBECi Field Descriptions
6.2.4.32 QMan Management Command/Result Register (QMAN_MCR)
Figure 6-68. QMan Management Command/Result Register (QMAN_MCR)
Table 6-67. QMAN_MCR Field Descriptions
6.2.4.33 QMan Management Command Parameter 0 Register (QMAN_MCP0)
Figure 6-69. QMan Management Command Parameter 0 Register (QMAN_MCP0)
Table 6-68. QMAN_MCP0 Field Descriptions
6.2.4.34 QMan Management Command Parameter 1 Register (QMAN_MCP1)
Figure 6-70. QMan Management Command Parameter 1 Register (QMAN_MCP1)
Table 6-69. QMAN_MCP1 Field Descriptions
6.2.4.35 QMan Management Command Result Registers (QMAN_MRi)
Figure 6-71. QMan Management Command Result Registers (QMAN_MRi)
Table 6-70. QMAN_MRi Field Descriptions
6.2.4.36 QMan Miscellaneous Configuration Register (QMAN_MISC_CFG)
Figure 6-72. QMan Miscellaneous Configuration Register (QMAN_MISC_CFG)
Table 6-71. QMAN_MISC_CFG Field Descriptions
6.2.4.37 QMan Idle Status Register (QMAN_IDLE_STAT)
Figure 6-73. QMan Idle Status Register (QMAN_IDLE_STAT)
Table 6-72. QMAN_IDLE_STAT Field Descriptions
6.2.4.38 QMan IP Block Revision 1 Register (QMAN_IP_REV_1)
Figure 6-74. QMan IP Block Revision 1Register (QMAN_IP_REV_1)
Table 6-73. QMAN_IP_REV_1 Field Descriptions
6.2.4.39 QMan IP Block Revision 2 Register (QMAN_IP_REV_2)
Figure 6-75. QMan IP Block Revision 2 Register (QMAN_IP_REV_2)
Table 6-74. QMAN_IP_REV_2 Field Descriptions
6.2.4.40 Data Structure Base Address Registers
6.2.4.40.1 Data Structure Extended Base Address Registers (FQD_BARE)
Figure 6-76. Data Structure Extended Base Address Registers (FQD_BARE)
Table 6-75. FQD_BARE Field Descriptions
6.2.4.40.2 Data Structure Extended Base Address Registers (PFDR_BARE)
Figure 6-77. Data Structure Extended Base Address Registers (PFDR_BARE)
Table 6-76. PFDR_BARE Field Descriptions
6.2.4.40.3 Data Structure Base Address Registers (FQD_BAR)
Figure 6-78. Data Structure Base Address Registers (FQD_BAR)
Table 6-77. FQD_BAR Field Descriptions
6.2.4.40.4 Data Structure Base Address Registers (PFDR_BAR)
Figure 6-79. Data Structure Base Address Registers (PFDR_BAR)
Table 6-78. PFDR_BAR Field Descriptions
6.2.4.41 Data Structure Attributes Registers
6.2.4.41.1 Data Structure Attributes Register (FQD_AR)
Figure 6-80. Data Structure Attribute Register (FQD_AR)
Table 6-79. FQD_AR Field Descriptions
6.2.4.41.2 Data Structure Attributes Register (PFDR_AR)
Figure 6-81. Data Structure Attribute Register (PFDR_AR)
Table 6-80. PFDR_AR Field Descriptions
6.2.4.42 QMan Software Portal (QCSP) Base Address Registers
6.2.4.42.1 QCSP Extended Base Address Register (QCSP_BARE)
Figure 6-82. QCSP Extended Base Address Register (QCSP_BARE)
Table 6-81. QCSP_BARE Field Descriptions
6.2.4.42.2 QCSP Base Address Register (QCSP_BAR)
Figure 6-83. QCSP Base Address Register (QCSP_BAR)
Table 6-82. QCSP_BAR Field Descriptions
6.2.4.43 Initiator Scheduling Configuration (CI_SCHED_CFG)
Figure 6-84. Initiator Scheduling Configuration Register (CI_SCHED_CFG)
Table 6-83. CI_SCHED_CFG Field Descriptions
6.2.4.44 QMan Source ID Register (QMAN_SRCIDR)
Figure 6-85. QMan Source ID Register (QMAN_SRCIDR)
Table 6-84. QMAN_SRCIDR Field Descriptions
6.2.4.45 QMan Logical I/O Device Number Register (QMAN_LIODNR)
Figure 6-86. QMan Logical I/O Device Number Register (QMAN_LIODNR)
Table 6-85. QMAN_LIODNR Field Descriptions
6.2.4.46 Initiator Read Latency Monitor Configuration Register (CI_RLM_CFG)
Figure 6-87. Initiator Read Latency Monitor Configuration Register (CI_RLM_CFG)
Table 6-86. CI_RLM_CFG Field Descriptions
6.2.4.47 Initiator Read Latency Monitor Average (CI_RLM_AVG)
Figure 6-88. Initiator Read Latency Monitor Average Register (CI_RLM_AVG)
Table 6-87. CI_RLM_AVG Field Descriptions
6.2.4.48 QMan Error Interrupt Status Register (QMAN_ERR_ISR)
Figure 6-89. QMan Error Interrupt Status Register (QMAN_ERR_ISR)
Table 6-88. QMAN_ERR_ISR Field Descriptions
6.2.4.49 QMan Error Interrupt Enable Register (QMAN_ERR_IER)
Figure 6-90. QMan Error Interrupt Enable Register (QMAN_ERR_IER)
Table 6-89. QMAN_ERR_IER Field Descriptions
6.2.4.50 QMan Error Interrupt Status Disable Register (QMAN_ERR_ISDR)
Figure 6-91. QMan Error Interrupt Status Disable Register (QMAN_ERR_ISDR)
Table 6-90. QMAN_ERR_ISDR Field Descriptions
6.2.4.51 QMan Error Interrupt Inhibit Register (QMAN_ERR_IIR)
Figure 6-92. QMan Error Interrupt Inhibit Register (QMAN_ERR_IIR)
Table 6-91. QMAN_ERR_IIR Field Descriptions
6.2.4.52 QMan Error Halt Enable Register (QMAN_ERR_HER)
Figure 6-93. QMan Error Halt Enable Register (QMAN_ERR_HER)
Table 6-92. QMAN_ERR_HER Field Descriptions
6.3 Functional Description
Figure 6-94. QMan Detailed Block Diagram
6.3.1 Frames
6.3.1.1 Frames and the QMan
6.3.1.2 Frame Descriptors (FDs)
6.3.1.2.1 Definition of Frame Descriptors (FDs)
6.3.1.2.2 Structure of Frame Descriptors (FDs)
Figure 6-95. Frame Descriptor Format (FD)
Table 6-93. Frame Descriptor (FD)
6.3.1.3 Frame Queues (FQs)
6.3.1.3.1 Definition of Frame Queues (FQs)
6.3.1.3.2 Frame Queues (FQs) and the QMan
6.3.1.3.3 Structure of Frame Queues (FQs)
Figure 6-96. Example-Frame Queue Structure Walk-Through
Figure 6-97. Example-Frame Queue Structure Walk-Through (continued)
Figure 6-98. Example-Frame Queue Structure Walk-Through (continued)
6.3.1.4 Frame Queue Descriptors (FQDs)
6.3.1.4.1 Definition of a Frame Queue Descriptor (FQD)
6.3.1.4.2 Frame Queue Descriptors (FQDs) and the QMan
6.3.1.4.3 Structure of a Frame Queue Descriptor (FQD)
Figure 6-99. Frame Queue Descriptor (FQD) Format
Table 6-94. Frame Queue Descriptor (FQD) Format Description
6.3.1.5 Frame Queue State
Figure 6-100. Frame Queue State Diagram (P4080)
Figure 6-101. Frame Queue State Diagram (P1023, P2041, P3041 and P5020)
6.3.2 Work Queues (WQs) and Channels
6.3.2.1 Definition of a Work Queue (WQ)
6.3.2.2 Definition of a Channel
6.3.2.3 Types of Channels
6.3.2.4 Work Queue Channel Assignments
Table 6-95. Work Queue (WQ) Channel Assignments in the QMan
6.3.3 Enqueue Operations
6.3.4 Dequeue Operations
6.3.4.1 Dequeue Availability
6.3.4.2 Dequeue Commands
6.3.4.3 Dequeuing in the Held Active State
6.3.5 Traffic Class (TC) Flow Control
6.3.6 Frame Queue (FQ) Flow Control
6.3.6.1 FQ Flow Control and FQ States
6.3.6.2 FQ Flow Control Exceptions
6.3.7 Dequeue Scheduling
6.3.7.1 WQ Channel Scheduling
6.3.7.2 WQ Class Scheduling
Table 6-96. WQ Class Scheduler
6.3.7.3 Intra-WQ Class Scheduling
6.3.8 Software Portals
6.3.8.1 Enqueue Command Ring (EQCR)
6.3.8.1.1 EQCR Errors
6.3.8.1.2 EQCR Production Notification
6.3.8.1.3 EQCR Consumption Notification
6.3.8.1.4 EQCR Interrupts
6.3.8.1.5 Speculative Reads of the EQCR Cache-Enabled Entries when Using Implicit Production Notification
6.3.8.2 Dequeue Response Ring (DQRR)
6.3.8.2.1 DQRR Production Notification
6.3.8.2.2 DQRR Consumption Notification
6.3.8.2.3 DQRR Dequeue Commands
6.3.8.2.4 DQRR Dequeue Command Portal Selection
6.3.8.2.5 DQRR Dequeue Dispatcher
Table 6-97. Dequeue Dispatcher Service Priorities
Figure 6-102. Software Portal Dequeue Dispatcher and WQ Class Schedulers
6.3.8.2.6 Dequeue Dispatcher Operation-Dequeuing from One or More Channels
6.3.8.2.7 Dequeue Dispatcher Operation-Dequeuing from a Specific WQ
Figure 6-103. Dequeue Dispatcher Operation Flow Diagram-Dequeuing from One or More Channels
Figure 6-104. Dequeue Dispatcher Operation Flow Diagram-Dequeuing from a Specified WQ
6.3.8.2.8 Active and Suspended Frame Queues
6.3.8.2.9 Dequeue Command Behavior when No Frames are Available for Dequeue
6.3.8.2.10 Dequeue Command Behavior with Parked and Retired Frame Queues
6.3.8.2.11 DQRR Interrupts
6.3.8.3 Message Ring (MR)
6.3.8.3.1 MR Production Notification
6.3.8.3.2 MR Consumption Notification
6.3.8.4 Management Command Register (CR)
6.3.8.5 Management Response Registers (RR0/RR1)
6.3.8.6 DQRR Entry Stashing
6.3.8.7 EQCR_CI Stashing
6.3.8.8 Dequeued Frame Data, Annotation, and Context Stashing
6.3.8.8.1 FQD Context_A Field used for dequeued Frame Data, Annotation, and Context Stashing control
Figure 6-105. FQD Context_A for dequeued Frame Data, Annotation, and Context Stashing control
Table 6-98. FQD Context_A field for dequeued Frame Data, Annotation, and Context Stashing control
6.3.8.8.2 Dropping of Dequeued Frame Data, Annotation, and FQ Context Stashes
6.3.8.9 Stash Transaction Flow Control and Scheduling
6.3.8.10 Software Portals Virtualization
6.3.9 Software Portal Commands and Responses
6.3.9.1 Enqueue Command
Figure 6-106. Enqueue Command Format
Table 6-99. Enqueue Command Format
6.3.9.2 Frame Dequeue Response
Figure 6-107. Frame Dequeue Response Format
Table 6-100. Frame Dequeue Response Format
6.3.9.3 ERN Message Response
Figure 6-108. ERN Message Response Format
Table 6-101. ERN Message Response Format
6.3.9.4 FQ State Change Notification Message Response
Figure 6-109. FQ State Change Notification Message Response Format
Table 6-102. FQ State Change Notification Message Response Format
6.3.9.5 Frame Queue Management Commands
6.3.9.5.1 Initialize Frame Queues (FQ)
Figure 6-110. Initialize FQ Command Format
Table 6-103. Initialize FQ Command Format
Figure 6-111. Initialize FQ Response Format
Table 6-104. Initialize FQ Response Format
6.3.9.5.2 Query FQ Programmable Fields
Figure 6-112. Query FQ Programmable Fields Command Format
Table 6-105. Query FQ Programmable Fields Command Format
Figure 6-113. Query FQ Programmable Fields Response Format
Table 6-106. Query FQ Programmable Fields Response Format
6.3.9.5.3 Query FQ Non-Programmable Fields
Figure 6-114. Query FQ Non-Programmable Fields Command Format
Table 6-107. Query FQ Non-Programmable Fields Command Format
Figure 6-115. Query FQ Non-Programmable Fields Response Format
Table 6-108. Query FQ Non-Programmable Fields Response Format
6.3.9.5.4 Alter FQ State Commands
Figure 6-116. Alter FQ State Command Format
Table 6-109. Alter FQ State Command Format
Figure 6-117. Alter FQ State Response Format
Table 6-110. Alter FQ State Response Format
6.3.9.5.5 Query WQ Length
Figure 6-118. Query WQ Length Command Format
Table 6-111. Query WQ Length Command Format
Figure 6-119. Query WQ Length Response Format
Table 6-112. Query WQ Length Response Format
6.3.9.6 Congestion Group Management Commands
6.3.9.6.1 Initialize/Modify a CGR
Figure 6-120. Initialize/Modify CGR Command Format
Table 6-113. Initialize/Modify CGR Command Format
Figure 6-121. Initialize/Modify CGR Response Format
Table 6-114. Initialize/Modify CGR Response Format
6.3.9.6.2 CGR Test Write
Figure 6-122. CGR Test Write Command Format
Table 6-115. CGR Test Write Command Format
Figure 6-123. CGR Test Write Response Format
Table 6-116. CGR Test Write Response Format
6.3.9.6.3 Query CGR
Figure 6-124. Query CGR Command Format
Table 6-117. Query CGR Command Format
Figure 6-125. Query CGR Response Format
Table 6-118. Query CGR Response Format
6.3.9.6.4 Query Congestion State
Figure 6-126. Query Congestion State Command Format
Table 6-119. Query Congestion State Command Format
Figure 6-127. Query Congestion State Response Format
Table 6-120. Query Congestion State Response Format
6.3.10 Direct Connect Portals (DCPs)
6.3.11 Algorithmic Sequencers
6.3.11.1 Portal Service Selection
6.3.11.2 Multi-Way Resource Arbiter (MRA)
6.3.11.3 Work Queue Semaphore and Context Manager
6.3.12 Frame Queue Descriptor Cache
6.3.12.1 FQD cache operation summary
6.3.13 Order Restoration
6.3.13.1 Position of Order Definition Points within QMan
6.3.13.2 Position of Order Restoration Points within QMan
6.3.13.3 Special Cases for Order Restoration
Figure 6-128. Order Restoration: Elapsed Time View of Packet Processing
Figure 6-129. Order Restoration: Elapsed Time View of Packet Processing (continued)
6.3.13.4 Order Definition Point Implementation
6.3.13.5 Order Restoration Point Implementation
6.3.13.5.1 Order Restoration Point (ORP) Descriptor
6.3.13.5.2 Using Sequence Numbers
6.3.13.5.3 ORP Behavior in Extreme Conditions
Figure 6-130. Order Restoration Sequence Number Windows
6.3.14 Congestion Management and Avoidance
6.3.14.1 Random Early Discard (RED)
6.3.14.2 Weighted Random Early Discard (WRED)
Figure 6-131. WRED Curve
6.3.14.3 Congestion Group Tail Drop
6.3.14.4 FQ Tail Drop
6.3.14.5 Enqueue Rejections
6.3.14.6 Congestion State Change Notifications (CSCN)
6.3.14.7 Congestion Group Record (CGR)
Table 6-121. Congestion Group Record (CGR)
6.3.15 Dynamic Debug (DD)
6.3.15.1 Data Path Frame Marking
6.3.15.2 Debug Trace Points
6.3.15.3 QMan Dynamic Frame Marking
6.3.15.4 Debug Halt
6.3.16 Error Management and Recovery
6.3.17 System Interfaces
6.3.18 System Target interface
6.3.19 System Initiator Interface
6.3.19.1 QMan’s use of LIODN and PAMU
Table 6-122. PAMU IOE to EOE mapping recommended for QMan
6.3.19.2 SrcID and LIODN_OFFSET
6.3.19.3 Initiator Scheduling and Priority
6.3.19.4 CPC Stashing of QMan Private Data Structures
6.4 Initialize the QMan
Chapter 7 Buffer Manager (BMan)
7.1 BMan Overview
7.1.1 BMan Features Overview
Figure 7-1. Buffer Manager (BMan) Block Diagram
7.1.2 BMan Features Summary
7.2 BMan Memory Map and Register Definition
7.2.1 BMan Software Portal Memory Map
Table 7-1. BMan Software Portal Memory Map (continued)
7.2.2 BMan Configuration and Control Register Memory Map
Table 7-2. BMan Configuration, Control, and Status Register Memory Map (continued)
7.2.3 BMan Software Portal (BCSP) Register Descriptions
7.2.3.1 BCSP Command Registers (BCSPn_CR)
Figure 7-2. BCSP Command Registers (BCSPn_CR)
Table 7-3. BCSPn_CR Field Descriptions
7.2.3.2 BCSP Response Registers (BCSPn_RRm)
Figure 7-3. BCSP Response Registers (BCSPn_RRm)
Table 7-4. BCSPn_RRm Field Descriptions
7.2.3.3 BCSP Release Command Ring Registers (BCSPn_RCRm)
Figure 7-4. BCSP Release Command Ring Registers (BCSPn_RCRm)
Table 7-5. BCSPn_RCRm Field Descriptions
7.2.3.4 BCSP Release Command Ring (RCR) Producer Index Registers (BCSPn_RCR_PI_CENA,BCSPn_RCR_PI_CINH)
Figure 7-5. BCSP RCR Producer Index Cache-Enabled and Cache-Inhibited Registers (BCSPn_RCR_PI_CENA, BCSPn_RCR_PI_CINH)
Table 7-6. BCSPn_RCR_PI_CENA, BCSPn_RCR_PI_CINH Field Descriptions
7.2.3.5 BSCP RCR Consumer Index Registers (BCSPn_RCR_CI_CENA, BCSPn_RCR_CI_CINH)
Figure 7-6. BCSP RCR Consumer Index Cache-Enabled and Cache-Inhibited Registers (BCSPn_RCR_CI_CENA, BCSPn_RCR_CI_CINH)
Table 7-7. BCSPn_RCR_CI_CENA, BCSPn_RCR_CI_CENA Field Descriptions
7.2.3.6 BCSP RCR Interrupt Threshold Register (BCSPi_RCR_ITR)
Figure 7-7. BCSP RCR Interrupt Threshold Register (BCSPn_RCR_ITR)
Table 7-8. BCSPn_RCR_ITR Field Descriptions
7.2.3.7 BCSP Configuration Registers (BCSPn_CFG)
Figure 7-8. BMan Software Portal Configuration Registers (BCSPn_CFG)
Table 7-9. BCSPn_CFG Field Descriptions
7.2.3.8 BCSP Depletion State Change Interrupt Enable Registers (BCSPn_SCNm/0)
Figure 7-9. BCSP SCN0 Depletion State Change Interrupt Enable Registers (BCSPn_SCN0)
Figure 7-10. BCSP SCN1 Depletion State Change Interrupt Enable Registers (BCSPn_SCN1)
Table 7-10. BCSPn_SCNm/0 Field Descriptions
7.2.3.9 BCSP Functional Interrupt Management Registers (BCSPn_ISR, BCSPn_IER, BCSPn_ISDR, BCSPn_IFR, BCSPn_IIR)
Figure 7-11. BCSP Interrupt Status Registers (BCSPn_ISR)
Figure 7-12. BCSP Interrupt Enable and Interrupt Status Disable Registers (BCSPn_IER, BCSPn_ISDR)
Figure 7-13. BCSP Interrupt Force Register (BCSPn_IFR)
Table 7-11. BCSPn_ISR, BCSPn_IER, BCSPn_IFR, BCSPn_ISDR Field Descriptions
Figure 7-14. BCSP Interrupt Inhibit Registers (BCSPn_IIR)
Table 7-12. BCSPn_IIR Field Descriptions
7.2.4 BMan Configuration and Control Register Descriptions
7.2.4.1 Block Revision Registers (BMAN_IP_REV_1, BMAN_IP_REV_2)
Figure 7-15. BMan IP Block Revision 1Register (BMAN_IP_REV_1)
Table 7-13. Register BMAN_IP_REV_1 Field Descriptions
Figure 7-16. BMan IP Block Revision 2 Register (BMAN_IP_REV_2)
Table 7-14. Register BMAN_IP_REV_2 Field Descriptions (continued)
7.2.4.2 Memory Configuration Registers (FBPR_BAR, FBPR_BARE, FBPR_AR, BMAN_LIODNR, BMAN_SRCID)
Figure 7-17. Data Structure Extended Base Address Registers (FBPR_BARE)
Table 7-15. Register FBPR_BARE Field Descriptions
Figure 7-18. Data Structure Base Address Registers (FBPR_BAR)
Table 7-16. Register FBPR_BAR Field Descriptions
Figure 7-19. Data Structure Attribute Registers (FBPR_AR)
Table 7-17. Register FBPR_AR Field Descriptions
Figure 7-20. BMan Logical I/O Device Number Register (BMAN_LIODNR)
Table 7-18. BMAN_LIODNR Field Descriptions
Figure 7-21. BMan Source ID Register (BMAN_SRCIDR)
Table 7-19. BMAN_SRCIDR Field Descriptions
7.2.4.3 Hardware and Software Portal Depletion Threshold Registers (BMAN_POOLn_SWDET, BMAN_POOLn_SWDXT)
Figure 7-22. Buffer Manager (BMan) threshold depletion state changes
Figure 7-23. BMan Software Portal Depletion Threshold Register (BMAN_POOLn_SWDET, BMAN_POOLn_SWDXT, BMAN_POOLn_HWDET, BMAN_POOLn_HWDXT)
Table 7-20. BMAN_POOLn_SWDET, BMAN_POOLn_SWDXT, BMAN_POOLn_HWDET, BMAN_POOLn_HWDXT Field Descriptions
7.2.4.4 FBPR Pool Low Watermark Interrupt Threshold Register (FBPR_FP_LWIT)
Figure 7-24. FBPR Free Pool Low Watermark Interrupt Threshold Register (FBPR_FP_LWIT)
Table 7-21. FBPR_FP_LWIT Field Descriptions
7.2.4.5 Hardware and Software Portal Depletion Count Register (BMAN_POOLn_SDCNT, BMAN_POOLn_HDCNT)
Figure 7-25. BMan Software Portal Depletion Count Registers (BMAN_POOLn_SDCNT, BMAN_POOLn_HDCNT)
Table 7-22. BMAN_POOLn_SDCNT, BMAN_POOLn_HDCNT Field Descriptions
7.2.4.6 Pool Content Registers (BMAN_POOLn_CONTENT, FBPR_FPC)
Figure 7-26. BMan Pool Content Register (BMAN_POOLn_CONTENT, FBPR_FPC)
Table 7-23. BMAN_POOLn_CONTENT Field Descriptions
7.2.4.7 Free List Head Pointer Registers (BMAN_POOLn_HDPTR, FBPR_HDPTR)
Figure 7-27. BMan Pool Content Registers (BMAN_POOLn_HDPTR, FBPR_HDPTR)
Table 7-24. BMAN_POOLn_HDPTR, FBPR_HDPTR Field Descriptions
7.2.4.8 Command Performance Monitor Configuration Registers (CMD_PMn_CFG)
Figure 7-28. BMAN Performance Monitor Configuration Registers (CMD_PMn_CFG)
Table 7-25. CMD_PMn_CFG Field Descriptions
7.2.4.9 Free List Performance Monitor Configuration Register (BMAN_FL_PMn_CFG)
Figure 7-29. BMAN Performance Monitor Configuration Register (BMAN_FL_PM_CFG)
Table 7-26. BMAN_FL_PM_CFG Field Descriptions
7.2.4.10 Error Interrupt Management Registers (BMAN_ERR_ISR, BMAN_ERR_IER, BMAN_ERR_ISDR, BMAN_ERR_IFR, BMAN_ERR_IIR)
Figure 7-30. BMan Error Interrupt Status Register (BMAN_ERR_ISR)
Figure 7-31. BMan Error Interrupt Enable Register (BMAN_ERR_IER)
Figure 7-32. BMan Error Interrupt Force Register (BMAN_ERR_IFR)
Table 7-27. BMAN_ERR_ISR Field Descriptions
Figure 7-33. BMan Error Interrupt Inhibit Register (BMAN_ERR_IIR)
Table 7-28. BMAN_ERR_IIR Field Descriptions
7.2.4.11 Single Bit ECC Error Threshold Register (BMAN_SBET)
Figure 7-34. BMan Single Bit Error Threshold Register (BMAN_SBET)
Table 7-29. BMAN_SBET Field Descriptions (continued)
7.2.4.12 Single Bit ECC Error Count Registers (BMAN_SBEC0-1)
Figure 7-35. BMan Single Bit Error Count Registers (BMAN_SBEC0-1)
Table 7-30. BMAN_SBEC0-1 Field Descriptions
7.2.4.13 Error Capture Registers (BMAN_ECSR, BMAN_ECIR, BMAN_EADR, BMAN_EDATA0-7)
Figure 7-36. BMan Error Capture Status Register (BMAN_ECSR)
Table 7-31. BMAN_ECSR Field Descriptions
Figure 7-37. Free Buffer Proxy Record Free Pool Count Register (BMAN_ECIR)
Table 7-32. BMAN_ECIR Field Descriptions
Figure 7-38. BMan Error Address Register (BMAN_EADR)
Table 7-33. BMAN_EADR Field Descriptions
Figure 7-39. BMan Error Data Registers (BMAN_EDATA0-7)
Table 7-34. BMAN_EDATA0-7 Field Descriptions
7.2.4.14 Error Fetch Capture and Address Registers (BMAN_EFCR, BMAN_EFAR)
Figure 7-40. BMan Error Fetch Capture Register (BMAN_EFCR)
Table 7-35. BMAN_EFCR Field Descriptions
Figure 7-41. BMan Error Fetch Address Register (BMAN_EFAR)
Table 7-36. BMAN_EFAR Field Descriptions
7.2.4.15 Error Capture Information Register (BMAN_ECIR)
Figure 7-42. Free Buffer Proxy Record Free Pool Count Register (BMAN_ECIR)
Table 7-37. BMAN_ECIR Field Descriptions (continued)
7.2.4.16 Corruption Error Capture and Address Registers (BMAN_CECR, BMAN_CEAR)
Figure 7-43. BMan Error Fetch Capture Register (BMAN_CECR)
Table 7-38. BMAN_CECR Field Descriptions
Figure 7-44. BMan Corruption Error Address Register (BMAN_CEAR)
Table 7-39. BMAN_CEAR Field Descriptions
7.2.4.17 Access Error Capture and Address Registers (BMAN_AECR, BMAN_AEAR)
Figure 7-45. BMan Error Fetch Capture Register (BMAN_AECR)
Table 7-40. BMAN_AECR Field Descriptions
Figure 7-46. BMan Error Fetch Address Register (BMAN_AEAR)
Table 7-41. BMAN_AEAR Field Descriptions
7.3 BMan Functional Description
7.3.1 Direct Connect Portals (DCPs)
7.3.2 External Memory Interfaces
7.3.3 Software Portal Components
7.3.3.1 Section 7.2.1, “BMan Software Portal Memory Map,” contains a detailed description of all of the software portal’s resour...
7.3.3.1.1 Writing a Command into the CR
7.3.3.1.2 Benefits of Using Alternating Polarity
7.3.3.1.3 Acquire and Query Commands
Figure 7-47. Acquire Command Format
Table 7-42. Acquire Command Format Field Descriptions
7.3.3.2 Response Register (RR) Functionality
7.3.3.2.1 Determining the Appropriate Response Register
Table 7-43. Internal Storage Register Conditions/Results
7.3.3.2.2 Acquire Response
Figure 7-48. Acquire Response Format
Table 7-44. Acquire Response Format Field Descriptions (continued)
7.3.3.2.3 Query Response
Figure 7-49. Query Response Format
Table 7-45. Query Response Format (continued)
7.3.3.2.4 Determining the Expected Polarity of the Valid Bit
Table 7-46. Determining the Expected Polarity of the Valid Bit
7.3.3.3 Release Command Ring (RCR) Functionality
7.3.3.3.1 Issuing a Command Using the RCR
7.3.3.3.2 Release Commands
Figure 7-50. Release Command Format
Table 7-47. Release Command Format (continued)
7.3.4 Interrupts
7.3.4.1 Interrupt Control Logic
Figure 7-51. Interrupt Control Logic Flow
Figure 7-52. Buffer Manager (BMan) interrupt state changes
7.3.4.2 Error Interrupt Sources
Table 7-48. Additional BMan Error Event Registers (continued)
7.3.4.3 Functional Interrupt Source, per Software Portal
Table 7-49. Additional BMan Error Event Registers
7.3.4.4 Reaction to Multi-Bit ECC Interrupts (MBEI)
7.3.4.5 Effect of FBPR Depletion on Release Commands
7.3.5 Buffer Pool State
7.3.5.1 Buffer Availability State
7.3.5.2 Buffer Depletion State
7.3.5.3 Changing Depletion Thresholds
7.3.6 Free Buffer Proxy Records (FBPRs)
7.3.6.1 FBPR Format: Containing FBPRs
Figure 7-53. Free Buffer Proxy Record (FBPR) Containing FBPR Indices
7.3.6.2 FBPR Format: Containing Buffer Pointers
Figure 7-54. Free Buffer Proxy Record (FBPR) Containing Buffer Pointers
7.3.6.3 FBPR Format
Figure 7-55. Free Buffer Proxy Record (FBPR) Using Buffer Pointers (BPs)
7.3.7 Performance Monitor
7.3.7.1 Command Performance Monitoring
7.3.7.2 Free List Fetch/Flush Performance Monitoring
7.4 BMan Initialization Tips
Chapter 8 Frame Manager (FMan)
8.1 Frame Manager Overview
Table 8-1. Mapping features to Freescale devices
8.1.1 FMan Terms, Acronyms, and Abbreviations
Table 8-2. FMan Terms, Acronyms, and Abbreviations
8.1.2 FMan Features Summary
8.2 Frame Manager High-Level Functional Description
8.2.1 FMan Hardware Ports Types
Table 8-3. Supported FMan Hardware Ports
8.2.2 FMan Network Interfaces
8.2.3 FMan-to-SoC Interfaces
Figure 8-1. FMan Interfaces Block Diagram
8.2.4 FMan Module Architecture
Figure 8-2. FMan Block Diagram
8.2.5 FMan User-Configurable Pipeline Architecture-Introducing the NIA
8.2.5.1 Packet Flow in the FMan Configurable Pipeline Architecture
Figure 8-3. FMan User-Configurable Pipeline Example
8.2.5.2 Role of the NIA in the FMan Configurable Pipeline Architecture
8.2.6 FMan Multitasking-Introducing the Task and TNUM
8.2.7 LIODN
8.2.8 FMan Hardware Ports, QMan sub-portals
8.2.9 FMan Timestamp
8.2.10 FMan Memory Map-High-Level Concept
8.2.11 FMan Internal Memory
Table 8-4. Mapping Different FMan into Freescale Devices
8.2.11.1 FMan Internal Memory for Tx, Rx, and O/H FIFOs
8.2.11.2 FMan Internal Memory for Coarse Classification
8.2.12 FMan Parser
Table 8-5. Parser Header Types
8.2.13 FMan Classification, Distribution
Table 8-6. Classification types
8.2.14 FMan Policer
8.2.15 FMan Functional Flows
8.2.15.1 Receive (Rx) Flows
8.2.15.1.1 Configurable Receive (Rx) Flows
Figure 8-4. Configurable Receive (Rx) Flows
8.2.15.1.2 Receive (Rx) Flow Example with Coarse Classification
Figure 8-5. FMan Receive (Rx) Functional Flow (Example)
Table 8-7. FMan Receive (Rx) Functional Flow (Example)
8.2.15.2 Transmit (Tx) Flow Example
Figure 8-6. FMan Transmit (Tx) Functional Flow (Example)
Table 8-8. FMan Transmit (Tx) Functional Flow (Example)
8.2.15.3 FMan Offline Port Flow Example
Figure 8-7. FMan Offline Port Functional Flow (Example for Offline Parsing)
Table 8-9. FMan Offline Port Functional Flow (Example for Offline Parsing)
8.2.15.4 Independent Mode (IM) Flow
Figure 8-8. Independent Mode Flow (Rx and Tx)
Table 8-10. Independent Rx Flow
Table 8-11. Independent Tx Flow
8.2.15.5 Host Command Flow
Figure 8-9. FMan Host Command Flow
Table 8-12. HOST Command Flow
8.3 Frame Manager Detailed Functional Description
8.3.1 FMan Hardware Ports
Table 8-13. Hardware PortIDs
Table 8-14. FMan Hardware Ports in Freescale Devices
8.3.1.1 FMan PortIDs
8.3.2 FMan Detailed Memory Map
Table 8-15. FMan base address in SoC Memory map
8.3.2.1 Hardware Port Pages in the FMan Memory Map
Table 8-16. FMan Memory Map Regions
Table 8-17. FMan Hardware Port Page Memory Map
8.3.2.2 Examples for the Evaluation of Addresses of FMan Registers
8.3.2.2.1 Calculate the SoC Absolute Address for an FMan Register
Figure 8-10. FMan Hardware Port Pages Address Space
8.3.2.2.2 Calculate the SoC Absolute Address for FMan Hardware Port Page Register
Figure 8-11. FMan Hardware Port Pages Address Space
8.3.3 FMan Frame Internal Context (IC)
Table 8-18. Internal Context (IC)
8.3.3.1 Override IC from FQD or Data Buffer
8.3.3.1.1 Frame Queue Descriptor (FQD) Context A
Figure 8-12. FQD[Context A] for FMan dequeue
Table 8-19. FQD[Context A] for FMan dequeue description
Figure 8-13. Context A-A0 Field Description for Tx Port
Table 8-20. Context A-A0 Field Descriptions for Tx Port
8.3.3.1.2 Frame Queue Descriptor Context B
Figure 8-14. Context B Structure
Table 8-21. Context B - field bit Descriptions
8.3.3.2 Frame Descriptor (FD)
Figure 8-15. Frame Descriptor
Table 8-22. Frame Descriptor Fields
8.3.3.2.1 FD Command/Status Word
Figure 8-16. Rx FD Status
Table 8-23. Rx FD Status Field Description
Figure 8-17. Tx FD Command
Figure 8-18. Tx FD Status (Confirmation)
Table 8-24. Tx FD Command/Status Field Description
Figure 8-19. Offline Port FD Command
Figure 8-20. Offline Port FD Status
Table 8-25. Offline Port FD Command/Status Field Description
Table 8-21. CRE_CHE
Figure 8-22. Host Command FD Command
Figure 8-23. Host Command FD Status
Table 8-26. Host Command FD Command/Status Field Description
8.3.3.3 Internal Context Action Descriptor (ICAD)
8.3.3.3.1 Internal Context Action Descriptor (ICAD) for Rx
Figure 8-24. Internal Context Action Descriptor (ICAD) for Rx
Table 8-27. ICAD for Rx Fields
8.3.3.3.2 Internal Context Action Descriptor (ICAD) for Tx or Offline Port
Figure 8-25. Internal Context Action Descriptor (ICAD) for Tx or Offline
Table 8-28. ICAD for Tx or Offline Fields
8.3.4 Next Invoked Action (NIA)
Figure 8-26. FMan Next Invoked Action (NIA) Structure
Table 8-29. NIA Field Descriptions
Table 8-30. NIA Codes Cross References
8.3.4.1 NIA Register Configuration-Rx Flows
Figure 8-27. Rx Flows
8.3.5 FMan Debug
8.3.5.1 FMan Debug Overview
8.3.5.2 FMan Debug Features Summary
8.3.5.3 FMan Debug Glossary
Table 8-31. FMan Debug Terms
8.3.5.4 FMan Packet Debug
8.3.5.4.1 Flow Debug
8.3.5.4.2 Trace
Figure 8-28. Trace First 4 Bytes
Table 8-32. Trace NIA Field Descriptions
8.3.5.4.3 Debug Traps
8.3.5.5 Debug Programming Model
8.3.5.5.1 Generic Debug Control Register Model
Figure 8-29. Generic Debug Trace Configuration Register Model
Table 8-33. Generic Debug Trace Configuration Model Field Descriptions
8.3.5.5.2 Generic Debug Trap Configuration Register (GDTCR) Model
Figure 8-30. Generic Debug Trap Configuration Register (GDTCR) Model
Table 8-34. GDTCR Field Descriptions
8.3.5.5.3 Generic Debug Value Register (DVR) Model
Figure 8-31. Generic Debug Trap Value Register (DVR) Model
Table 8-35. Generic Debug Trap Value Register (DVR) Model Field Descriptions
8.3.5.5.4 Generic Debug Trap Mask Register Model
8.3.5.6 DMA Trace Write
Figure 8-32. Generic Debug Trap Mask Register Model
Table 8-36. Generic Debug Trap Mask Register Model Field Descriptions
8.3.6 Implementing Statistics Counters
8.3.7 Error Handling
Table 8-37. Types of FMan Errors
8.3.7.1 Local Catastrophic Errors
8.3.7.2 Serious Errors
8.3.7.3 Operational Errors
8.3.8 Configuration Register Access
8.3.9 Graceful Stop
8.3.9.1 Tx Port Graceful Stop
8.3.9.2 Rx Port Graceful Stop
8.3.10 Dynamic Changes
8.4 Frame Manager-Buffer Manager Interface (BMI)
8.4.1 Frame Manager BMI Introduction
8.4.1.1 Acronyms
Table 8-38. Glossary of Acronyms and Abbreviations
8.4.1.2 Terminology
Table 8-39. Terms and Descriptions
8.4.2 Frame Manager BMI Overview
8.4.2.1 Frame Manager BMI Features
8.4.2.2 Frame Manager BMI Modes of Operation
8.4.3 BMI Input NIA
Table 8-40. BMI Input Actions Codes (NIAs)
8.4.4 Frame Manager BMI Memory Map and Register Definition
Figure 8-33. FMan Hardware Port Pages Address Space
Table 8-41. BMI Memory Map
Table 8-42. BMI Detailed Memory Map
8.4.4.1 Storage Profiles
Table 8-43. Hardware port storage profile
8.4.4.2 FMan BMI Common Registers Description
8.4.4.2.1 BMI Initialization Register (FMBM_INIT)
Figure 8-34. BMI Initialization Register (FMBM_INIT)
Table 8-44. FMBM_INIT Field Descriptions
8.4.4.2.2 BMI Configuration 1 Register (FMBM_CFG1)
Figure 8-35. BMI Configuration 1 Register (FMBM_CFG1)
Table 8-45. FMBM_CFG1 Field Descriptions
8.4.4.2.3 BMI Configuration 2 Register (FMBM_CFG2)
Figure 8-36. BMI Configuration 2 Register (FMBM_CFG2)
Table 8-46. FMBM_CFG2 Field Descriptions
8.4.4.2.4 Interrupt Event Register (FMBM_IEVR)
Figure 8-37. Interrupt Event Register (FMBM_IEVR)
Table 8-47. FMBM_IEVR Field Descriptions
8.4.4.2.5 Interrupt Enable Register (FMBM_IER)
Figure 8-38. Interrupt Enable Register (FMBM_IER)
Table 8-48. FMBM_IER Field Descriptions
8.4.4.2.6 Interrupt Force Register (FMBM_IFR)
Figure 8-39. Interrupt Force Register (FMBM_IFR)
Table 8-49. FMBM_IFR Field Descriptions
8.4.4.2.7 BMI Arbitration Registers (FMBM_ARB_1-8)
Figure 8-40. BMI Arbitration Registers (FMBM_ARB_1-8)
Table 8-50. FMBM_ARB Field Descriptions
8.4.4.2.8 Debug Trap Counter Register (FMBM_DTC)
Figure 8-41. Debug Trap Counter Register (FMBM_DTC)
Table 8-51. FMBM_DTC Field Descriptions
8.4.4.2.9 Debug Compare Value Register (FMBM_DCV)
Figure 8-42. Debug Compare Value Register (FMBM_DCV)
Table 8-52. FMBM_DCV Field Descriptions
8.4.4.2.10 Debug Compare Mask (FMBM_DCM)
Figure 8-43. Debug Compare Mask (FMBM_DCM)
Table 8-53. FMBM_DCM Field Descriptions
8.4.4.2.11 Global Debug Enable (FMBM_GDE)
Figure 8-44. Global Debug Enable (FMBM_GDE)
Table 8-54. FMBM_GDE Field Descriptions
8.4.4.2.12 Port Parameters Register (FMBM_PP_1-63)
Figure 8-45. Port Parameters Register (FMBM_PP_1-63)
Table 8-55. FMBM_PP Field Descriptions
8.4.4.2.13 Port FIFO Size Register (FMBM_PFS_1-63)
Figure 8-46. Port FIFO Size Register (FMBM_PFS_1-63)
Table 8-56. FMBM_PFS Field Descriptions
8.4.4.2.14 SPLIODN Register (FMBM_SPLIODN_1-63)
Figure 8-47. Storage Profile and Logical I/O Device Number Register (FMBM_SPLIODN)
Table 8-57. FMBM_SPLIODN Field Descriptions
8.4.4.3 Rx Port Register Descriptions
8.4.4.3.1 Rx Configuration Register (FMBM_RCFG)
Figure 8-48. Rx Configuration Register (FMBM_RCFG)
Table 8-58. FMBM_RCFG Field Descriptions
8.4.4.3.2 Rx Status Register (FMBM_RST)
Figure 8-49. Rx Status Register (FMBM_RST)
Table 8-59. FMBM_RST Reset Values
Table 8-60. FMBM_RST Field Descriptions
8.4.4.3.3 Rx DMA Attributes Register (FMBM_RDA)
Figure 8-50. Rx DMA Attributes Register (FMBM_RDA)
Table 8-61. FMBM_RDA Field Descriptions
8.4.4.3.4 Rx FIFO Parameters Register (FMBM_RFP)
Figure 8-51. Rx FIFO Parameters Register (FMBM_RFP)
Table 8-62. FMBM_RFP Field Descriptions
8.4.4.3.5 Rx Frame End Data Register (FMBM_RFED)
Figure 8-52. Rx Frame End Data Register (FMBM_RFED)
Table 8-63. FMBM_RFED Field Descriptions
8.4.4.3.6 Rx Internal Context Parameters (FMBM_RICP)
Figure 8-53. Rx Internal Context Parameters (FMBM_RICP)
Table 8-64. FMBM_RICP Field Descriptions
8.4.4.3.7 Rx Internal Margins Register (FMBM_RIM)
Figure 8-54. Rx Internal Margins Register (FMBM_RIM)
Table 8-65. FMBM_RIM Field Descriptions
8.4.4.3.8 Rx External Buffer Margins Register (FMBM_REBM)
Figure 8-55. Rx External Buffer Margins Register (FMBM_REBM)
Table 8-66. FMBM_REBM Field Descriptions
8.4.4.3.9 Rx Frame Next Engine Register (FMBM_RFNE)
Figure 8-56. Rx Frame Next Engine Register (FMBM_RFNE)
Table 8-67. FMBM_RFNE Field Descriptions
8.4.4.3.10 Rx Frame Attributes Register (FMBM_RFCA)
Figure 8-57. Rx Frame Attributes Register (FMBM_RFCA)
Table 8-68. FMBM_RFCA Field Descriptions
8.4.4.3.11 Rx Frame Parser Next Engine Register (FMBM_RFPNE)
Figure 8-58. Rx Frame Parser Next Engine Register (FMBM_RFPNE)
Table 8-69. FMBM_RFPNE Field Descriptions
8.4.4.3.12 Rx Parsing Start Offset Register (FMBM_RPSO)
Figure 8-59. Rx Parsing Start Offset Register (FMBM_RPSO)
Table 8-70. FMBM_RPSO Field Descriptions
8.4.4.3.13 Rx Policer Profile Register (FMBM_RPP)
Figure 8-60. Rx Policer Profile Register (FMBM_RPP)
Table 8-71. FMBM_RPP Field Descriptions
8.4.4.3.14 Rx Coarse Classification Base Register (FMBM_RCCB)
Figure 8-61. Rx Coarse Classification Base Register (FMBM_RCCB)
Table 8-72. FMBM_RCCB Field Descriptions
8.4.4.3.15 Rx Excessive Threshold Register (FMBM_RETH)
Figure 8-62. Rx Excessive Threshold Register (FMBM_RETH)
Table 8-73. FMBM_RETH Field Descriptions
8.4.4.3.16 Rx Parse Result Initialization Register (FMBM_RPRI)
Figure 8-63. Rx Parse Result Initialization Register (FMBM_RPRI)
Table 8-74. FMBM_RPRI Reset Values
Table 8-75. FMBM_RPRI Field Descriptions
8.4.4.3.17 Rx Frame Queue ID Register (FMBM_RFQID)
Figure 8-64. Rx Frame Queue ID Register (FMBM_RFQID)
Table 8-76. FMBM_RFQID Field Descriptions
8.4.4.3.18 Rx Error Frame Queue ID Register (FMBM_REFQID)
Figure 8-65. Rx Error Frame Queue ID Register (FMBM_REFQID)
Table 8-77. FMBM_REFQID Field Descriptions
8.4.4.3.19 Rx Frame Status Discard Mask Register (FMBM_RFSDM)
Figure 8-66. Rx Frame Status Discard Mask Register (FMBM_RFSDM)
Table 8-78. FMBM_RFSDM Field Descriptions
8.4.4.3.20 Rx Frame Status Error Mask Register (FMBM_RFSEM)
Figure 8-67. Rx Frame Status Error Mask Register (FMBM_RFSEM)
Table 8-79. FMBM_RFSEM Field Descriptions
8.4.4.3.21 Rx Frame Enqueue Next Engine Register (FMBM_RFENE)
Figure 8-68. Rx Frame Enqueue Next Engine Register (FMBM_RFENE)
Table 8-80. FMBM_RFENE Field Descriptions
8.4.4.3.22 Rx External Buffers Manager Pool Information Register (FMBM_REBMPI)
Figure 8-69. External Buffers Manager Pool Information Register (FMBM_REBMPI)
Table 8-81. FMBM_REBMPI_y Field Descriptions
8.4.4.3.23 Rx Allocate Counter Register (FMBM_RACNT)
Figure 8-70. Allocate Counter Register (FMBM_RACNT)
Table 8-82. FMBM_RACNT Field Descriptions
8.4.4.3.24 Receive Congestion Group Map Register (FMBM_RCGM)
Figure 8-71. Receive Congestion Group Map Register (FMBM_RCGM)
Table 8-83. FMBM_RCGM Field Descriptions
8.4.4.3.25 BMan Pool Depletion Register (FMBM_RMPD)
Figure 8-72. BMan Pool Depletion Register (FMBM_RMPD)
Table 8-84. FMBM_RMPD Field Descriptions
8.4.4.3.26 Statistics Counters Register (FMBM_RSTC)
Figure 8-73. Rx Statistics Counters Register (FMBM_RSTC)
Table 8-85. FMBM_RSTC Field Descriptions
8.4.4.3.27 Rx Frame Counter Register (FMBM_RFRC)
Figure 8-74. Rx Frame Counter Register (FMBM_RFRC)
Table 8-86. FMBM_RFRC Field Descriptions
8.4.4.3.28 Rx Bad Frames Counter Register (FMBM_RBFC)
Figure 8-75. Rx Bad Frames Counter Register (FMBM_RBFC)
Table 8-87. FMBM_RBFC Field Descriptions
8.4.4.3.29 Rx Large Frames Counter Register (FMBM_RLFC)
Figure 8-76. Rx Large Frames Counter Register (FMBM_RLFC)
Table 8-88. FMBM_RLFC Field Descriptions
8.4.4.3.30 Rx Filter Frames Counter Register (FMBM_RFFC)
Figure 8-77. Rx Filter Frames Counter Register (FMBM_RFFC)
Table 8-89. FMBM_RFFC Field Descriptions
8.4.4.3.31 Rx Frames Discard Counter Register (FMBM_RFDC)
Figure 8-78. Rx Frames Discard Counter Register (FMBM_RFDC)
Table 8-90. FMBM_RFDC Field Descriptions
8.4.4.3.32 Rx Frames List DMA Error Counter Register (FMBM_RFLDEC)
Figure 8-79. Rx Frames List DMA Error Counter Register (FMBM_RFLDEC)
Table 8-91. FMBM_RLFDEC Field Descriptions
8.4.4.3.33 Rx Out of Buffers Discard Counter Register (FMBM_RODC)
Figure 8-80. Rx Out of Buffers Discard Counter Register (FMBM_RODC)
Table 8-92. FMBM_RODC Field Descriptions
8.4.4.3.34 Rx Buffers Deallocate Counter Register (FMBM_RBDC)
Figure 8-81. Rx Buffers Deallocate Counter Register (FMBM_RBDC)
Table 8-93. FMBM_RBDC Field Descriptions
8.4.4.3.35 Rx Performance Counters Register (FMBM_RPC)
Figure 8-82. Rx Performance Counters Register (FMBM_RPC)
Table 8-94. FMBM_RPC Field Descriptions
8.4.4.3.36 Rx Performance Count Parameters Register (FMBM_RPCP)
Figure 8-83. Rx Performance Count Parameters Register (FMBM_RPCP)
Table 8-95. FMBM_RPCP Field Descriptions
8.4.4.3.37 Rx Cycle Counter Register (FMBM_RCCN)
Figure 8-84. Rx Cycle Counter Register (FMBM_RCCN)
Table 8-96. FMBM_RCCN Field Descriptions
8.4.4.3.38 Rx Tasks Utilization Counter Register (FMBM_RTUC)
Figure 8-85. Rx Tasks Utilization Counter Register (FMBM_RTUC)
Table 8-97. FMBM_RTUC Field Descriptions
8.4.4.3.39 Rx Receive Queue Utilization Counter Register (FMBM_RRQUC)
Figure 8-86. Rx Receive Queue Utilization Counter Register (FMBM_RRQUC)
Table 8-98. FMBM_RRQUC Field Descriptions
8.4.4.3.40 Rx DMA Utilization Counter Register (FMBM_RDUC)
Figure 8-87. Rx DMA Utilization Counter Register (FMBM_RDUC)
Table 8-99. FMBM_RDUC Field Descriptions
8.4.4.3.41 Rx FIFO Utilization Counter Register (FMBM_RFUC)
Figure 8-88. Rx FIFO Utilization Counter Register (FMBM_RFUC)
Table 8-100. FMBM_RFUC Field Descriptions
8.4.4.3.42 Rx Pause Activation Counter Register (FMBM_RPAC)
Figure 8-89. Rx Pause Activation Counter Register (FMBM_RPAC)
Table 8-101. FMBM_RFUC Field Descriptions
8.4.4.3.43 Rx Debug Configuration Register (FMBM_RDCFG)
Figure 8-90. Rx Debug Configuration Register (FMBM_RDCFG)
Table 8-102. FMBM_RDCFG Field Descriptions
8.4.4.4 Tx Port Register Descriptions
8.4.4.4.1 Tx Configuration Register (FMBM_TCFG)
Figure 8-91. Tx Configuration Register (FMBM_TCFG)
Table 8-103. FMBM_TCFG Field Descriptions
8.4.4.4.2 Tx Status Register (FMBM_TST)
Figure 8-92. Tx Status Register (FMBM_TST)
Table 8-104. FMBM_TST Field Descriptions
8.4.4.4.3 Tx DMA Attributes Register (FMBM_TDA)
Figure 8-93. Tx DMA Attributes Register (FMBM_TDA)
Table 8-105. FMBM_TDA Field Descriptions
8.4.4.4.4 Tx FIFO Parameters Register (FMBM_TFP)
Figure 8-94. Tx FIFO Parameters Register (FMBM_TFP)
Table 8-106. FMBM_TFP Reset Values
Table 8-107. FMBM_TFP Field Descriptions
8.4.4.4.5 Tx Frame End Data Register (FMBM_TFED)
Figure 8-95. Tx Frame End Data Register (FMBM_TFED)
Table 8-108. FMBM_TFED Field Descriptions
8.4.4.4.6 Tx Internal Context Parameters Register (FMBM_TICP)
Figure 8-96. Tx Internal Context Parameters Register (FMBM_TICP)
Table 8-109. FMBM_TICP Field Descriptions
8.4.4.4.7 Tx Frame Dequeue Next Engine Register (FMBM_TFDNE)
Figure 8-97. Tx Frame Dequeue Next Engine Register (FMBM_TFDNE)
Table 8-110. FMBM_TFDNE Field Descriptions
8.4.4.4.8 Tx Frame Attributes Register (FMBM_TFCA)
Figure 8-98. Tx Frame Attributes Register (FMBM_TFCA)
Table 8-111. FMBM_TFCA Field Descriptions
8.4.4.4.9 Tx Confirmation Frame Queue ID Register (FMBM_TCFQID)
Figure 8-99. Tx Confirmation Frame Queue ID Register (FMBM_TCFQID)
Table 8-112. FMBM_TCFQID Field Descriptions
8.4.4.4.10 Tx Error Frame Queue ID Register (FMBM_TEFQID)
Figure 8-100. Tx Error Frame Queue ID Register (FMBM_TEFQID)
Table 8-113. FMBM_TEFQID Field Descriptions
8.4.4.4.11 Tx Frame Enqueue Next Engine Register (FMBM_TFENE)
Figure 8-101. Tx Frame Enqueue Next Engine Register (FMBM_TFENE)
Table 8-114. FMBM_TFENE Field Descriptions
8.4.4.4.12 Tx Rate Limiter Scale Register (FMBM_TRLMTS)
Figure 8-102. Tx Rate Limiter Scale Register (FMBM_TRLMTS)
Table 8-115. FMBM_TRLMTS Field Descriptions
8.4.4.4.13 Tx Rate Limiter Register (FMBM_TRLMT)
Figure 8-103. Tx Rate Limiter Register (FMBM_TRLMT)
Table 8-116. FMBM_TRLMT Field Descriptions
8.4.4.4.14 Tx Statistics Counters Register (FMBM_TSTC)
Figure 8-104. Tx Statistics Counters Register (FMBM_TSTC)
Table 8-117. FMBM_TSTC Field Descriptions
8.4.4.4.15 Tx Frame Counter Register (FMBM_TFRC)
Figure 8-105. Tx Frame Counter Register (FMBM_TFRC)
Table 8-118. FMBM_TFRC Field Descriptions
8.4.4.4.16 Tx Frames Discard Counter Register (FMBM_TFDC)
Figure 8-106. Tx Frames Discard Counter Register (FMBM_TFDC)
Table 8-119. FMBM_TFDC Field Descriptions
8.4.4.4.17 Tx Frames Length Error Discard Counter Register (FMBM_TFLEDC)
Figure 8-107. Tx Frames Length Error Discard Counter Register (FMBM_TFLEDC)
Table 8-120. FMBM_TFLEDC Field Descriptions
8.4.4.4.18 Tx Frames Unsupported Format Discard Counter Register (FMBM_TFUFDC)
Figure 8-108. Tx Frames Unsupported Format Discard Counter Register (FMBM_TFUFDC)
Table 8-121. FMBM_TFUFDC Field Descriptions
8.4.4.4.19 Tx Buffers Deallocate Counter Register (FMBM_TBDC)
Figure 8-109. Tx Buffers Deallocate Counter Register (FMBM_TBDC
Table 8-122. FMBM_TBDC Field Descriptions
8.4.4.4.20 Tx Performance Counters Register (FMBM_TPC)
Figure 8-110. Tx Performance Counters Register (FMBM_TPC)
Table 8-123. FMBM_TPC Field Descriptions
8.4.4.4.21 Tx Performance Count Parameters Register (FMBM_TPCP)
Figure 8-111. Tx Performance Count Parameters Register (FMBM_TPCP)
Table 8-124. FMBM_TPCP Field Descriptions
8.4.4.4.22 Tx Cycle Counter Register (FMBM_TCCN)
Figure 8-112. Tx Cycle Counter Register (FMBM_TCCN)
Table 8-125. FMBM_TCCN Field Descriptions
8.4.4.4.23 Tx Tasks Utilization Counter Register (FMBM_TTUC)
Figure 8-113. Tx Tasks Utilization Counter Register (FMBM_TTUC)
Table 8-126. FMBM_TTUC Field Descriptions
8.4.4.4.24 Tx Transmit Confirm Queue Utilization Counter Register (FMBM_TTCQUC)
Figure 8-114. Tx Transmit Confirm Queue Utilization Counter Register (FMBM_TTCQUC)
Table 8-127. FMBM_TTCQUC Field Descriptions
8.4.4.4.25 Tx DMA Utilization Counter Register (FMBM_TDUC)
Figure 8-115. Tx DMA Utilization Counter Register (FMBM_TDUC)
Table 8-128. FMBM_TDUC Field Descriptions
8.4.4.4.26 Tx FIFO Utilization Counter Register (FMBM_TFUC)
Figure 8-116. Tx FIFO Utilization Counter Register (FMBM_TFUC)
Table 8-129. FMBM_TFUC Field Descriptions
8.4.4.4.27 Tx Debug Configuration Register (FMBM_TDCFG)
Figure 8-117. Tx Debug Configuration Register (FMBM_TDCFG)
Table 8-130. FMBM_TDCFG Field Descriptions
8.4.4.5 Offline Port/Host Command Port Registers Description
8.4.4.5.1 Offline Port/Host Command (O/H) Configuration Register (FMBM_OCFG)
Figure 8-118. Offline Port/Host Command (O/H) Configuration Register (FMBM_OCFG)
Table 8-131. FMBM_OCFG Field Descriptions
8.4.4.5.2 O/H Status Register (FMBM_OST)
Figure 8-119. O/H Status Register (FMBM_OST)
Table 8-132. FMBM_OST Reset Values
Table 8-133. FMBM_OST Field Descriptions
8.4.4.5.3 O/H DMA Attributes Register (FMBM_ODA)
Figure 8-120. O/H DMA Attributes Register (FMBM_ODA)
Table 8-134. FMBM_ODA Field Descriptions
8.4.4.5.4 O/H Internal Context Parameters Register (FMBM_OICP)
Figure 8-121. O/H Internal Context Parameters Register (FMBM_OICP)
Table 8-135. FMBM_OICP Field Descriptions
8.4.4.5.5 O/H Frame Dequeue Next Engine Register (FMBM_OFDNE)
Figure 8-122. O/H Frame Dequeue Next Engine Register (FMBM_OFDNE)
Table 8-136. FMBM_OFDNE Field Descriptions
8.4.4.5.6 O/H Frame Next Engine Register (FMBM_OFNE)
Figure 8-123. O/H Frame Dequeue Next Engine Register (FMBM_OFNE)
Table 8-137. FMBM_OFNE Field Descriptions
8.4.4.5.7 O/H Frame Attributes Register (FMBM_OFCA)
Figure 8-124. O/H Frame Attributes Register (FMBM_OFCA)
Table 8-138. FMBM_OFCA Field Descriptions
8.4.4.5.8 O/H Frame Parser Next Engine Register (FMBM_OFPNE)
Figure 8-125. O/H Frame Dequeue Next Engine Register (FMBM_OFPNE)
Table 8-139. FMBM_OFPNE Field Descriptions
8.4.4.5.9 O/H Parsing Start Offset Register (FMBM_OPSO)
Figure 8-126. O/H Parsing Start Offset Register (FMBM_OPSO)
Table 8-140. FMBM_OPSO Field Descriptions
8.4.4.5.10 O/H Policer Profile Register (FMBM_OPP)
Figure 8-127. O/H Policer Profile Register (FMBM_OPP)
Table 8-141. FMBM_OPP Field Descriptions
8.4.4.5.11 O/H Coarse Classification Base Register (FMBM_OCCB)
Figure 8-128. O/H Coarse Classification Base Register (FMBM_OCCB)
Table 8-142. FMBM_OCCB Field Descriptions
8.4.4.5.12 O/H Internal Margins Register (FMBM_OIM)
Figure 8-129. O/H Internal Margins Register (FMBM_OIM)
Table 8-143. FMBM_OIM Field Descriptions
8.4.4.5.13 O/H FIFO Parameters Register (FMBM_OFP)
Figure 8-130. O/H FIFO Parameters Register (FMBM_OFP)
Table 8-144. FMBM_OFP Field Descriptions
8.4.4.5.14 O/H Parse Result Initialization Register (FMBM_OPRI)
Figure 8-131. O/H Parse Result Initialization Register (FMBM_OPRI)
Table 8-145. FMBM_OPRI Reset Values
Table 8-146. FMBM_OPRI Field Descriptions
8.4.4.5.15 O/H Frame Queue ID Register (FMBM_OFQID)
Figure 8-132. O/H Frame Queue ID Register (FMBM_OFQID)
Table 8-147. FMBM_OFQID Field Descriptions
8.4.4.5.16 O/H Error Frame Queue ID Register (FMBM_OEFQID)
Figure 8-133. O/H Error Frame Queue ID Register (FMBM_OEFQID)
Table 8-148. FMBM_OEFQID Field Descriptions
8.4.4.5.17 O/H Frame Status Discard Mask Register (FMBM_OFSDM)
Figure 8-134. O/H Frame Status Discard Mask Register (FMBM_OFSDM)
Table 8-149. FMBM_OFSDM Field Descriptions
8.4.4.5.18 O/H Frame Status Error Mask Register (FMBM_OFSEM)
Figure 8-135. O/H Frame Status Error Mask Register (FMBM_OFSEM)
Table 8-150. FMBM_OFSEM Field Descriptions
8.4.4.5.19 O/H Frame Enqueue Next Engine Register (FMBM_OFENE)
Figure 8-136. O/H Frame Enqueue Next Engine Register (FMBM_OFENE)
Table 8-151. FMBM_OFENE Field Descriptions
8.4.4.5.20 O/H Rate Limiter Scale Register (FMBM_ORLMTS)
Figure 8-137. O/H Rate Limiter Scale Register (FMBM_ORLMTS)
Table 8-152. FMBM_ORLMTS Field Descriptions
8.4.4.5.21 O/H Rate Limiter Register (FMBM_ORLMT)
Figure 8-138. O/H Rate Limiter Register (FMBM_ORLMT)
Table 8-153. FMBM_ORLMT Field Descriptions
8.4.4.5.22 FMBM_OEBMPI - Observed External Buffers Manager Pool Information
Figure 8-139. - FMBM_OEBMPI_y - External Buffer Manager pool Information
Table 8-154. FMBM_OEBMPI_y Field Descriptions
8.4.4.5.23 FMBM_OCGM - Observed Congestion Group Map
Figure 8-140. FMBM_OCGM - Observed Congestion Group Map
Table 8-155. FMBM_OCGM Field Descriptions
8.4.4.5.24 FMBM_OMPD - Observed BMan Pool Depletion
Figure 8-141. FMBM_OMPD - Observed Bman Pool Depletion
Table 8-156. FMBM_OMPD Field Descriptions
8.4.4.5.25 O/H Statistics Counters Register (FMBM_OSTC)
Figure 8-142. O/H Statistics Counters Register (FMBM_OSTC)
Table 8-157. FMBM_OSTC Field Descriptions
8.4.4.5.26 O/H Frame Counter Register (FMBM_OFRC)
Figure 8-143. O/H Frame Counter Register (FMBM_OFRC)
Table 8-158. FMBM_OFRC Field Descriptions
8.4.4.5.27 O/H Frames Discard Counter Register (FMBM_OFDC)
Figure 8-144. O/H Frames Discard Counter Register (FMBM_OFDC)
Table 8-159. FMBM_OFDC Field Descriptions
8.4.4.5.28 O/H Frames Length Error Discard Counter Register (FMBM_OFLEDC)
Figure 8-145. O/H Frames Length Error Discard Counter Register (FMBM_OFLEDC)
Table 8-160. FMBM_OFLEDC Field Descriptions
8.4.4.5.29 O/H Frames Unsupported Format Discard Counter Register (FMBM_OFUFDC)
Figure 8-146. O/H Frames Unsupported Format Discard Counter Register (FMBM_OFUFDC)
Table 8-161. FMBM_OFUFDC Field Descriptions
8.4.4.5.30 O/H Filter Frames Counter Register (FMBM_OFFC)
Figure 8-147. O/H Filter Frames Counter Register (FMBM_OFFC)
Table 8-162. FMBM_OFFC Field Descriptions
8.4.4.5.31 O/H Frames WRED Discard Counter Register (FMBM_OFWDC)
Figure 8-148. O/H Frames WRED Discard Counter Register (FMBM_OFWDC)
Table 8-163. FMBM_RFWDC Field Descriptions
8.4.4.5.32 O/H Frames List DMA Error Counter Register (FMBM_OFLDEC)
Figure 8-149. O/H Frames List DMA Error Counter Register (FMBM_OFLDEC)
Table 8-164. FMBM_OLFDEC Field Descriptions
8.4.4.5.33 O/H Buffers Deallocate Counter Register (FMBM_OBDC)
Figure 8-150. O/H Buffers Deallocate Counter Register (FMBM_OBDC)
Table 8-165. FMBM_OBDC Field Descriptions
8.4.4.5.34 O/H Performance Counters Register (FMBM_OPC)
Figure 8-151. O/H Performance Counters Register (FMBM_OPC)
Table 8-166. FMBM_OPC Field Descriptions
8.4.4.5.35 O/H Performance Count Parameters Register (FMBM_OPCP)
Figure 8-152. O/H Performance Count Parameters Register (FMBM_OPCP)
Table 8-167. FMBM_OPCP Field Descriptions
8.4.4.5.36 O/H Cycle Counter Register (FMBM_OCCN)
Figure 8-153. O/H Cycle Counter Register (FMBM_OCCN)
Table 8-168. FMBM_OCCN Field Descriptions
8.4.4.5.37 O/H Tasks Utilization Counter Register (FMBM_OTUC)
Figure 8-154. O/H Tasks Utilization Counter Register (FMBM_OTUC)
Table 8-169. FMBM_OTUC Field Descriptions
8.4.4.5.38 O/H DMA Utilization Counter Register (FMBM_ODUC)
Figure 8-155. O/H DMA Utilization Counter Register (FMBM_ODUC)
Table 8-170. FMBM_ODUC Field Descriptions
8.4.4.5.39 O/H FIFO Utilization Counter Register (FMBM_OFUC)
Figure 8-156. O/H FIFO Utilization Counter Register (FMBM_OFUC)
Table 8-171. FMBM_OFUC Field Descriptions
8.4.4.5.40 O/H Debug Configuration Register (FMBM_ODCFG)
Figure 8-157. O/H Debug Configuration Register (FMBM_ODCFG)
Table 8-172. FMBM_ODCFG Field Descriptions
8.4.5 Frame Manager BMI Functional Description
8.4.5.1 Introduction to BMI Functional Description
8.4.5.2 Introduction to BMI Data flows
8.4.5.3 BMI Rx Flow-Normal Mode
8.4.5.3.1 Initialization
8.4.5.3.2 BMI ‘Rx Frame’
8.4.5.3.3 Rx BMI ‘Discard Frame’ or ‘Prepare to Enqueue Frame’
8.4.5.3.4 BMI ‘Release Internal Buffers’
8.4.5.4 BMI Rx Flow-Independent Mode
8.4.5.5 BMI Tx Flow-Normal Mode
8.4.5.5.1 Tx BMI ‘Allocate internal IC’ and QMI dequeue
8.4.5.5.2 BMI ‘Transmit Frame’
8.4.5.6 BMI Tx Flow-Independent Mode
8.4.5.7 BMI Offline Port Flow
8.4.5.7.1 Initialization
8.4.5.7.2 Offline BMI ‘Allocate internal IC’ and QMI dequeue
8.4.5.7.3 BMI Offline ‘frame fetch’
8.4.5.7.4 BMI Offline ‘Discard Frame’ or ‘Prepare to Enqueue Frame’
8.4.5.7.5 BMI Offline ‘Release Internal Buffers’
8.4.5.8 BMI Host Command Flow
8.4.6 BMI Internal Operation Details
8.4.6.1 Buffer Pool Selection for Rx and O/H
Figure 8-158. Maximum Frame Size to Fit in One External Buffer
8.4.6.1.1 Backup Pools
8.4.6.2 Restrictions on a scatter/gather list
8.4.6.3 Internal and External Margins
8.4.6.3.1 Internal Margins
8.4.6.3.2 External Margins
Figure 8-159. External Buffer Start Margin Calculation
Figure 8-160. Internal and External Margins, Single Buffer Frame Format
Figure 8-161. Internal and External Margins, Scatter/Gather Frame Format
8.4.6.4 Conditions that enable Tx checksum generation
8.4.6.5 Conditions that enable Offline checksum validation
8.4.6.6 Rx Normal mode and Offline - Enqueue or discard decision logic
Table 8-173. BMI Rx/O/H Flow - Enqueue or discard decision logic
8.4.6.7 Tx confirmation enqueue and buffer deallocation decision
Figure 8-162. Tx Confirmation Enqueue Decision Flow
8.4.6.8 Offline Port Enqueue Decision Flow
Table 8-174. Offline Port Enqueue Decision Flow
8.4.6.9 Host command enqueue decision flow
Figure 8-163. Host Command Enqueue Decision Flow
8.4.6.10 DMA resource Load balancing
8.4.6.11 FMan DMA Priority Elevation
8.4.6.12 LIODN Offset
8.4.6.13 Congestion or Rejection Handling
8.4.6.14 Pause Frames for Flow Control
8.4.6.15 Tx and O/H Rate Limiter
Figure 8-164. BMI Token Bucket Mechanism
8.4.6.16 Internal FIFO Configuration Requirements
8.4.6.16.1 Internal FIFO for Rx Ports
8.4.6.16.2 Internal FIFO for Tx Ports.
8.4.6.16.3 Internal FIFO for O/H Ports
8.4.6.17 Hardware Assist for IEEE 1588-Compliant Timestamping
8.4.6.18 Error Handling
8.4.6.18.1 Non-Recoverable Errors
8.4.6.18.2 Network Errors
8.4.6.18.3 Buffer Depletion
8.4.6.18.4 When this situation occurs, the frame is discarded and the appropriate discard counter is incremented. Buffer depleti...
8.4.6.18.5 Unsupported Frames
8.4.6.18.6 Timestamp Errors
8.4.6.18.7 DMA Error
8.4.6.19 Graceful Stop
8.4.6.20 Debug Capabilities
8.4.6.20.1 Flow Initialization
8.4.6.20.2 Flow Trap
8.4.6.20.3 Flow Trace
Table 8-175. BMI Trace Information
Table 8-176. BMI Prefix Description
Table 8-177. BMI Port ID Description
8.4.6.20.4 Trap Action
8.4.7 Frame Manager BMI Initialization/Application Information
8.4.7.1 Initialization of Common Registers
8.4.7.2 Rx Port Initialization Steps in Normal Mode
8.4.7.3 Rx Port Initialization Steps in Independent Mode
8.4.7.4 Tx Port Initialization Steps in Normal Mode (Example)
8.4.7.5 Tx Port Initialization Steps in Independent Mode
8.4.7.6 Initialization Steps for Offline Ports
8.4.7.7 Initialization Steps of Host Command Ports
8.4.8 BMI Change Summary from P4080 to P1023
8.5 Frame Manager-Queue Manager Interface (QMI)
8.5.1 QMI Overview
Figure 8-166. QMI Connection Block Diagram
8.5.1.1 QMI Features Summary
8.5.2 QMI Input NIA
8.5.3 QMI Memory Map and Register Definition
8.5.3.1 Register offsets
Figure 8-167. FMan Hardware Port Pages Address Space
Table 8-178. QMI Memory Map
8.5.3.2 QMI Register Descriptions
8.5.3.2.1 QMI General Configuration Register (FMQM_GC)
Figure 8-168. QMI General Configuration Register (FMQM_GC)
Table 8-179. Register FMQM_GC Field Descriptions
8.5.3.2.2 Error Interrupt Event Register (FMQM_EIE)
Figure 8-169. Error Interrupt Event Register (FMQM_EIE)
Table 8-180. Register FMQM_EIE Field Descriptions
8.5.3.2.3 Error Interrupt Enable Register (FMQM_EIEN)
Figure 8-170. Error Interrupt Enable Register (FMQM_EIEN)
Table 8-181. Register FMQM_EIEN Field Descriptions
8.5.3.2.4 Error Interrupt Force Register (FMQM_EIF)
Figure 8-171. Error Interrupt Force Register (FMQM_EIF)
Table 8-182. FMQM_EIF Field Descriptions
8.5.3.2.5 Interrupt Event Register (FMQM_IE)
Figure 8-172. Interrupt Event Register (FMQM_IE)
Table 8-183. Register FMQM_IE Field Descriptions
8.5.3.2.6 Interrupt Enable Register (FMQM_IEN)
Figure 8-173. Interrupt Enable Register (FMQM_IEN)
Table 8-184. Register FMQM_IEN Field Descriptions
8.5.3.2.7 Interrupt Force Register (FMQM_IF)
Figure 8-174. Interrupt Force Register (FMQM_IF)
Table 8-185. Register FMQM_IF Field Descriptions
8.5.3.2.8 Global Status Register (FMQM_GS)
Figure 8-175. QMI Global Status Register (FMQM_GS)
Table 8-186. Register FMQM_GS Field Descriptions
Figure 8-176. Task Status Register (FMQM_TS)
8.5.3.2.9 Enqueue Total Frame Counter Register (FMQM_ETFC)
Figure 8-177. Enqueue Total Frame Counter Register (FMQM_ETFC)
Table 8-187. Register FMQM_ETFC Field Descriptions
8.5.3.2.10 Dequeue Total Frame Counter Register (FMQM_DTFC)
Figure 8-178. Dequeue Total Frame Counter Register (FMQM_DTFC)
Table 8-188. Register FMQM_DTFC Field Descriptions
8.5.3.2.11 Dequeue Counter 0 Register (FMQM_DC0)
Figure 8-179. Dequeue Counter 0 Register (FMQM_DC0)
Table 8-189. Register FMQM_DC0 Field Descriptions
8.5.3.2.12 Dequeue Counter 1 Register (FMQM_DC1)
Figure 8-180. Dequeue Counter 1 Register (FMQM_DC1)
Table 8-190. Register FMQM_DC1 Field Descriptions
8.5.3.2.13 Dequeue Counter 2 Register (FMQM_DC2)
Figure 8-181. Dequeue Counter 2 Register (FMQM_DC2)
Table 8-191. Register FMQM_DC2 Field Descriptions
8.5.3.2.14 Dequeue Counter 3 Register (FMQM_DC3)
Figure 8-182. Dequeue Counter 3 Register (FMQM_DC3)
Table 8-192. Register FMQM_DC3 Field Descriptions
8.5.3.2.15 TNUM Aging Period Control Register (FMQM_TAPC)
Figure 8-183. TNUM Aging Period Control Register (FMQM_TAPC)
Table 8-193. Register FMQM_TAPC Field Descriptions
8.5.3.2.16 Dequeue MAC Command Valid Counter Register (FMQM_DMCVC)
Figure 8-184. Dequeue MAC Command Valid Counter Register (FMQM_DMCVC)
Table 8-194. Register FMQM_DCC Field Descriptions
8.5.3.2.17 Dequeue Invalid FD Command Counter Register (FMQM_DIFDCC)
Figure 8-185. Dequeue Invalid FD Command Counter Register (FMQM_DIFDCC)
Table 8-195. Register FMQM_DIFDCC Field Descriptions
8.5.3.2.18 Dequeue A1 Valid Counter Register (FMQM_DA1VC)
Figure 8-186. Dequeue A1 Valid Counter Register (FMQM_DA1VC)
Table 8-196. Register FMQM_DA1VC Field Descriptions
8.5.3.2.19 Debug Trace Configuration Register (FMQM_DTRC)
Figure 8-187. Debug Trace Configuration Register (FMQM_DTRC)
Table 8-197. Register FMQM_DTRC Field Descriptions
8.5.3.2.20 Enqueue Frame Descriptor Dynamic Debug Register (FMQM_EFDDD)
Figure 8-188. Enqueue Frame Descriptor Dynamic Debug Register (FMQM_EFDDD)
Table 8-198. Register FMQM_EFDDD Field Descriptions
8.5.3.2.21 Debug Trap Configuration n Register (FMQM_DTCn)
Figure 8-189. Debug Trap Configuration n Register (FMQM_DTCn)
Table 8-199. FMQM_DTCn Field Descriptions
8.5.3.2.22 Debug Trap Value n Register (FMQM_DTVn)
Figure 8-190. Debug Trap Value n Register (FMQM_DTVn)
Table 8-200. FMQM_DTVn Field Descriptions
8.5.3.2.23 Debug Trap Mask n Register (FMQM_DTMn)
Figure 8-191. Debug Trap Mask n Register (FMQM_DTMn)
Table 8-201. FMQM_DTMn Field Descriptions
8.5.3.2.24 Debug Trap Counter n Register (FMQM_DTCn)
Figure 8-192. Debug Trap Counter n Register (FMQM_DTCn)
Table 8-202. FMQM_DTCn Field Descriptions
8.5.3.2.25 PortID n Configuration Register (FMQM_PnC)
Figure 8-193. PortID n Configuration Register (FMQM_PnC)
Table 8-203. FMQM_PnC Field Descriptions
8.5.3.2.26 PortID n Status Register (FMQM_PnS)
Figure 8-194. PortID n Status Register (FMQM_PnS)
Table 8-204. FMQM_PnS Field Descriptions
8.5.3.2.27 PortID n Task Status Register (FMQM_PnTS)
Figure 8-195. PortID n Task Status Register (FMQM_PnTS)
Table 8-205. FMQM_PnTS Field Descriptions
8.5.3.2.28 PortID n Enqueue NIA Register (FMQM_PnEN)
Figure 8-196. PortID n Enqueue NIA Register (FMQM_PnEN)
Table 8-206. FMQM_PnEN Field Descriptions
8.5.3.2.29 PortID n Enqueue NIA Register (FMQM_PnEN)
Figure 8-197. PortID n Enqueue NIA Register (FMQM_PnEN)
Table 8-207. FMQM_PnEN Field Descriptions
8.5.3.2.30 PortID n Enqueue Total Frame Counter Register (FMQM_PnETFC)
Figure 8-198. PortID n Enqueue Total Frame Counter Register (FMQM_PnETFC)
Table 8-208. FMQM_PnETFC Field Descriptions
8.5.3.2.31 PortID n Dequeue NIA Register (FMQM_PnDN)
Figure 8-199. PortID n Dequeue NIA Register (FMQM_PnDN)
Table 8-209. FMQM_PnDN Field Descriptions
8.5.3.2.32 PortID n Dequeue NIA Register (FMQM_PnDN)
Figure 8-200. PortID n Dequeue NIA Register (FMQM_PnDN)
Table 8-210. FMQM_PnDN Field Descriptions
8.5.3.2.33 PortID n Dequeue Config Registers (FMQM_PnDC)
Figure 8-201. PortID n Dequeue Config Register (FMQM_PnDC)
Table 8-211. FMQM_PnDC Field Descriptions
8.5.3.2.34 PortID n Dequeue Total Frame Counter Register (FMQM_PnDTFC)
Figure 8-202. PortID n Dequeue Total Frame Counter Register (FMQM_PnDTFC)
Table 8-212. FMQM_PnDTFC Field Descriptions
8.5.3.2.35 PortID n Dequeue FQID Not Override Counter Register (FMQM_PnDFNOC)
Figure 8-203. PortID n Dequeue FQID Not Override Counter Register (FMQM_PnDFNOC)
Table 8-213. FMQM_PnDFNOC Field Descriptions
8.5.3.2.36 PortID n Dequeue Confirm Counter Register (FMQM_PnDCC)
Figure 8-204. PortID n Dequeue Confirm Counter Register (FMQM_PnDCC)
Table 8-214. FMQM_PnDCC Field Descriptions
8.5.4 QMI Functional Description
8.5.4.1 Enqueue Operation
8.5.4.2 Dequeue Operation
8.5.4.3 FMan Hardware Ports, QMan sub-portals - details
Figure 8-205. FMan hardware ports and QMan sub-portals
8.5.4.4 QMI parameters which affect performance
8.5.4.4.1 TNUM Aging Mechanism
8.5.4.5 FMan Software Reset Operation
8.5.4.6 QMI Graceful Stop Operation
8.5.4.7 QMI Debug Functionality
8.5.4.7.1 Packet Processing Flow Debug
Table 8-215. QMI Trace Size
Table 8-216. FMan QMI Trace Debug Format
Table 8-217. Trapped Data
8.5.4.7.2 QMI Performance Monitoring
8.5.5 QMI Initialization Sequence
Table 8-218. QMI PortID Counters
8.5.5.1 Initializing the Common QMI Registers
8.5.5.2 Initializing a Specific PortID
8.5.5.2.1 Initializing an Rx Port
8.5.5.2.2 Initializing an Tx/Host Command/Offline Parsing Port
8.5.5.2.3 QMI Graceful Stop Operation for Dequeue
8.6 Frame Manager-Frame Processing Manager
8.6.1 FPM Overview
8.6.1.1 Frames and the FPM
8.6.2 FPM Features
8.6.3 Frame Manager-FPM Memory Map and Register Definition
Table 8-219. FPM Memory Map
8.6.3.1 FPM PortID Control Register (FMFP_PRC)
Figure 8-206. FPM PortID Control Register (FMFP_PRC)
Table 8-220. FMFP_PRC Field Description
8.6.3.2 FPM Maximum Dispatches Register (FMFP_MXD)
Figure 8-207. FPM Maximum Dispatches Register (FMFP_MXD)
Table 8-221. FMFP_MXD Field Descriptions
8.6.3.3 FPM Dispatch Thresholds1 Register (FMFP_DIST1)
Figure 8-208. FPM Dispatch Thresholds 1 Register (FMFP_DIST1)
Table 8-222. FMFP_DIST1 Field Descriptions
8.6.3.4 FPM Dispatch Thresholds2 Register (FMFP_DIST2)
Figure 8-209. FPM Dispatch Thresholds 2 Register (FMFP_DIST2)
Table 8-223. FMFP_DIST2 Field Descriptions
8.6.3.5 FMan Error Pending Interrupt Register (FM_EPI)
Figure 8-210. FMan Error Pending Interrupt Register (FM_EPI)
Table 8-224. FM_EPI Field Descriptions
8.6.3.6 FMan Rams Interrupt Enable Register (FM_RIE)
Figure 8-211. FMan RAMs Interrupt Enable Register (FM_RIE)
Table 8-225. FM_RIE Field Descriptions
8.6.3.7 FPM FMan Controller Event 0-3 Registers (FMFP_FCEV)
Figure 8-212. FPM FMan Controller Event 0-3 Registers (FMFP_FCEVn)
Table 8-226. FMFP_FCEVn Field Descriptions
8.6.3.8 FPM FMan Controller Event Enable0-3 Registers (FMFP_CEE)
Figure 8-213. FPM FMan Controller Event Enable 0-3 Registers (FMFP_CEEn)
Table 8-227. ReFMFP_CEEn Field Descriptions
8.6.3.9 FPM TimeStamp Control1 Register (FMFP_TSC1)
Figure 8-214. FPM TimeStamp Control 1 Register (FMFP_TSC1)
Table 8-228. FMFP_TSC1 Descriptions
8.6.3.10 FPM TimeStamp Control2 Register (FMFP_TSC2)
Figure 8-215. FPM TimeStamp Control 2 Register (FMFP_TSC2)
Table 8-229. FMFP_TSC2 Field Descriptions
8.6.3.11 FPM Time Stamp Register (FMFP_TSP)
Figure 8-216. FPM Time Stamp Register (FMFP_TSP)
Table 8-230. FMFP_TSP Field Descriptions
8.6.3.12 FPM Time Stamp Fraction Register (FMFP_TSF)
Figure 8-217. FPM TimeStamp Fraction Register (FMFP_TSF)
Table 8-231. FMFP_TSF Field Descriptions
8.6.3.13 FMan Rams Control and Event Register (FM_RCR)
Figure 8-218. FMan RAMs Control and Event Register (FM_RCR)
Table 8-232. FM_RCR Field Descriptions
8.6.3.14 FPM External Requests Control Register (FMFP_EXTC)
Figure 8-219. FPM External Requests Control Register (FMFP_EXTC)
Table 8-233. FMFP_EXTC Field Descriptions
8.6.3.15 FPM Data Ram Data0-3 Register (FMFP_DRDn)
Figure 8-220. FPM Data RAM Data 0-3 Registers (FMFP_DRDn)
Table 8-234. FMFP_DRDn Field Descriptions
8.6.3.16 FPM Data RAM Access Register (FMFP_DRA)
Figure 8-221. FPM Data RAM Access Register (FMFP_DRA)
Table 8-235. FMFP_DRA Field Descriptions
8.6.3.17 FMan IP Block Revision 1 Register (FM_IP_REV_1)
Figure 8-222. FMan IP Block Revision 1 Register (FM_IP_REV_1)
Table 8-236. Register FM_IP_REV_1 Bits Description
8.6.3.18 FMan IP Block Revision 2 Register (FM_IP_REV_2)
Figure 8-223. FMan IP Block Revision 2 Register (FM_IP_REV_2)
Table 8-237. FM_IP_REV_2 Field Descriptions
8.6.3.19 FMan Reset Command Register (FM_RSTC)
Figure 8-224. FMan Reset Command Register (FM_RSTC)
Table 8-238. FM_RSTC Field Descriptions
8.6.3.20 FMan Controller Debug Control Register (FMFP_CLDC)
Figure 8-225. FPM Controller Debug Control Register (FMFP_CLDC)
Table 8-239. FMFP_CLDC Field Descriptions
Table 8-240. FMan FPM Debug Trace Format
8.6.3.21 FMan Normal Pending Interrupt Register (FM_NPI)
Figure 8-226. FMan Normal Pending Interrupt Register (FM_NPI)
Table 8-241. FM_NPI Field Descriptions
8.6.3.22 FPM Event and Enable Register (FMFP_EE)
Figure 8-227. FPM Event and Enable Register (FMFP_EE)
Table 8-242. FMFP_EE Field Descriptions
8.6.3.23 FPM CPU Event 0-3 Registers (FMFP_CEVn)
Figure 8-228. FPM CPU Event 0-3 Registers (FMFP_CEVn)
Table 8-243. FMFP_CEVn Field Descriptions
8.6.3.24 FPM PortID Status 0-49 Registers (FMFP_PSn)
Figure 8-229. FPM PortID Status 0-49 Registers (FMFP_PSn)
Table 8-244. FMFP_PSn Field Descriptions
8.6.3.25 FMan Controller Flow AB Control Register (FMFP_CLFABC)
Figure 8-230. FMan Controller Flow AB Control Register (FMFP_CLFABC)
Table 8-245. FMFP_CLFABC Field Descriptions
8.6.3.26 FMan Controller Flow C Control Register (FMFP_CLFCC)
Figure 8-231. FMan Controller Flow C Control Register (FMFP_CLFCC)
Table 8-246. FMFP_CLFCC Field Descriptions
8.6.3.27 FMan Controller Flow A Value Register (FMFP_CLFAVAL)
Figure 8-232. FMan Controller Flow A Value Register (FMFP_CLFAVAL)
Table 8-247. FMFP_CLFAVAL Field Descriptions
8.6.3.28 FMan Controller Flow B Value Register (FMFP_CLFBVAL)
Figure 8-233. FMan Controller Flow B Value Register (FMFP_CLFBVAL)
Table 8-248. FMFP_CLFBVAL Field Descriptions
8.6.3.29 FMan Controller Flow C Value Register (FMFP_CLFCVAL)
Figure 8-234. FMan Controller Flow C Value Register (FMFP_CLFCVAL)
Table 8-249. FMFP_CLFCVAL Field Descriptions
8.6.3.30 FMan Controller Flow A Mask Register (FMFP_CLFAMSK)
Figure 8-235. FMan Controller Flow A Mask Register (FMFP_CLFAMSK)
Table 8-250. FMFP_CLFAMSK Field Descriptions
8.6.3.31 FMan Controller Flow B Mask Register (FMFP_CLFBMSK)
Figure 8-236. FMan Controller Flow B Mask Register (FMFP_CLFBMSK)
Table 8-251. FMFP_CLFBMSK Field Descriptions
8.6.3.32 FMan Controller Flow C Mask Register (FMFP_CLFCMSK)
Figure 8-237. FMan Controller Flow C Mask Register (FMFP_CLFCMSK)
Table 8-252. FMFP_CLFCMSK Field Descriptions
8.6.3.33 FMan Controller Flow A Match Count Register (FMFP_CLFAMC)
Figure 8-238. FMan Controller Flow A Match Count Register (FMFP_CLFAMC)
Table 8-253. FMFP_CLFAMC Field Descriptions
8.6.3.34 FMan Controller Flow B Match Count Register (FMFP_CLFBMC)
Figure 8-239. FMan Controller Flow B Match Count Register (FMFP_CLFBMC)
Table 8-254. FMFP_CLFBMC Field Descriptions
8.6.3.35 FMan Controller Flow C Match Count Register (FMFP_CLFCMC)
Figure 8-240. FMan Controller Flow C Match Count Register (FMFP_CLFCMC)
Table 8-255. FMFP_CLFCMC Field Descriptions
8.6.3.36 FPM TNUM Status 0-127 Registers (FMFP_TSn)
Figure 8-241. FPM TNUM Status 0-127 Registers (FMFP_TSn)
Table 8-256. FMFP_TSn Field Descriptions
8.6.4 Functional Description
8.6.4.1 Order Definition and Restoration
8.6.4.2 Timestamp and Prescale (TSP)
Figure 8-242. Timestamp & Prescale Logic
8.6.4.2.1 TSP Example
8.6.5 Initialization Information
8.7 Frame Manager-DMA
8.7.1 FMan DMA Overview
Figure 8-243. DMA in the FMan Block Diagram
8.7.2 FMan DMA Feature Summary
8.7.3 Introduction about the FMan DMA
8.7.4 FMan DMA Memory Map/Register Definition
Table 8-257. FMan DMA Memory Map
8.7.4.1 FMan DMA Status Register (FMDM_SR)
Figure 8-244. FMan DMA Status Register (FMDM_SR)
Table 8-258. Register FMDM_SR Bits Description
8.7.4.2 FMan DMA Mode Register (FMDM_MR)
Figure 8-245. FMan DMA Mode Register (FMDM_MR)
Figure 8-246. Man DMA Mode Register (FMDM_MR)
Table 8-259. Register FMDM_MR Bits Description
8.7.4.3 FMan DMA Threshold Register (FMDM_TR)
Figure 8-247. DMA Read Data Path
Figure 8-248. DMA Write Data Path
Figure 8-249. DMA Command Queue
Figure 8-250. FMan DMA Threshold Register (FMDM_TR)
Table 8-260. Register FMDM_TR Bits Description
8.7.4.4 FMan DMA Hysteresis Registers (FMDM_HY)
Figure 8-251. FMan DMA Hysteresis Register (FMDM_HY)
Table 8-261. Register FMDM_HY Bits Description
8.7.4.5 FMan DMA SOS Emergency Threshold Register (FMDM_SETR)
Figure 8-252. FMan DMA SOS Emergency Threshold Register (FMDM_SETR)
Table 8-262. Register FMDM_SETR Bits Description
8.7.4.6 FMan DMA Transfer Address High Register (FMDM_TAH)
Figure 8-253. FMan DMA Transfer Address High Register (FMDM_TAH)
Table 8-263. Register FMDM_TAH Bits Description
8.7.4.7 FMan DMA Transfer Address Low Register (FMDM_TAL)
Figure 8-254. FMan DMA Transfer Address Low Register (FMDM_TAL)
Table 8-264. Register FMDM_TAL Bits Description
8.7.4.8 FMan DMA Transfer Communication ID Register (FMDM_TCID)
Figure 8-255. FMan DMA Transfer Communication ID Register (FMDM_TCID)
Table 8-265. Register FMDM_TCID Bits Description
8.7.4.9 FMan DMA buffer Watchdog Counter Value (FMDM_WCR)
Figure 8-256. FMan DMA buffer Watchdog Counter Value (FMDM_WCR)
Table 8-266. Register FMDM_WCR Bits Description
8.7.4.10 FMan DMA buffer Base in FMan Memory Value Register (FMDM_EBCR)
Figure 8-257. FMan DMA buffer Base in FMan Memory Value Register (FMDM_EBCR)
Table 8-267. Register FMDM_EBCR Bits Description
8.7.4.11 FMan DMA Debug Counter (FMDM_DCR)
Figure 8-258. FMan DMA Debug Counter (FMDM_DCR)
Table 8-268. Register FMDM_DCR Bits Description
8.7.4.12 FMan DMA Emergency Smoother Register (FMDM_EMSR)
Figure 8-259. FMan DMA Emergency Smoother Register (FMDM_EMSR)
Table 8-269. Register FMDM_EMSR Bits Description
8.7.4.13 FMan DMA PortID-LIODN Registers (FMDM_PLRn)
Figure 8-260. Hardware Port (PortID)-LIODNn Registers (FMDM_PLR)
Table 8-270. Register FMDM_PLR (0.. 31) Bits Description
8.7.5 FMan DMA Functional Description
8.7.5.1 Bus Error
8.7.5.2 ECC Error
8.7.5.3 Halt
8.7.5.4 Reset
8.7.6 FMan DMA Initialization
8.7.7 FMan DMA Debug Functionality
8.8 Frame Manager-Parser
8.8.1 Parser Overview
8.8.2 Parser Features Summary
8.8.3 Parser Memory Map/Register Definition
Table 8-271. Parser Overall Memory Map
Table 8-272. Parser Individual Register Memory Map
Table 8-273. Parse Internal Memory Map
8.8.3.1 Parser Register Descriptions
8.8.3.1.1 Port x Parse Memory Direct Access Registers
Table 8-274. Port x Header Examination Configuration
Figure 8-261. Port x Configuration Access Control Register (FMPR_PxCAC)
Table 8-275. FMPR_PxCAC Field Descriptions
Figure 8-262. Port x Configured TPID Register (FMPR_PxCTPID)
Table 8-276. FMPR_PxCTPID Field Descriptions
8.8.3.1.2 Parse Memory Read/Write Direct Access Registers-Global Configuration
Figure 8-263. Soft Examination Parameter Array Wx Register (FMPR_SXPAWx)
Table 8-277. FMPR_SXPAWx Field Descriptions
Figure 8-264. Rx Parsing Cycle Limit Register (FMPR_RPCLIM)
Table 8-278. FMPR_RPCLIM Field Descriptions
Figure 8-265. Rx Parse Internal Memory Access Control Register (FMPR_RPIMAC)
Table 8-279. FMPR_RPIMAC Field Descriptions
Figure 8-266. Parse Memory ECC Error Capture Register (FMPR_PMEEC)
Table 8-280. FMPR_PMEEC Field Descriptions
8.8.3.1.3 Interrupt Registers
Figure 8-267. Parser Event Register (FMPR_PEVR)
Table 8-281. FMPR_PEVR Field Descriptions
Figure 8-268. Parser Event Enable Register (FMPR_PEVER)
Table 8-282. FMPR_PEVER Field Descriptions
Figure 8-269. Parser Error Register (FMPR_PERR)
Table 8-283. FMPR_PERR Field Descriptions
Figure 8-270. Parser Error Enable Register (FMPR_PERER)
Table 8-284. FMPR_PERER Field Descriptions
8.8.3.1.4 Parse Statistic Registers
Figure 8-271. Per Port Parser Statistic Control Register (FMPR_PPSC)
Table 8-285. FMPR_PPSC Fields Description
Figure 8-272. Parse Dispatch Statistic Register (FMPR_PDS)
Table 8-286. Register FMPR_PDS Bits Description
Figure 8-273. L2 Result Returned Statistic Register (FMPR_L2RRS)
Table 8-287. FMPR_L2RRS Field Descriptions
Figure 8-274. L3 Result Returned Statistic Register (FMPR_L3RRS)
Table 8-288. FMPR_L3RRS Field Descriptions
Figure 8-275. L4 Result Returned Statistic Register (FMPR_L4RRS)
Table 8-289. FMPR_L4RRS Field Descriptions
Figure 8-276. Shim Result Returned Statistic Register (FMPR_SRRS)
Table 8-290. FMPR_SRRS Field Descriptions
Figure 8-277. L2 Result Returned with Error Statistic Register (FMPR_L2RRES)
Table 8-291. FMPR_L2RRES Field Descriptions
Figure 8-278. L3 Result Returned with Error Statistic Register (FMPR_L3RRES)
Table 8-292. FMPR_L3RRES Field Descriptions
Figure 8-279. L4 Result Returned with Error Statistic Register (FMPR_L4RRES)
Table 8-293. FMPR_L4RRES Field Descriptions
Figure 8-280. Shim Result Returned with Error Statistic Register (FMPR_SRRES)
Table 8-294. FMPR_SRRES Field Descriptions
Figure 8-281. Soft Parser Cycle Statistic Register (FMPR_SPCS)
Table 8-295. FMPR_SPCS Field Descriptions
Figure 8-282. Soft Parser Stall Cycle Statistic Register (FMPR_SPSCS)
Table 8-296. FMPR_SPSCS Field Descriptions
Figure 8-283. HXS Cycle Statistic Register (FMPR_HXSCS)
Table 8-297. FMPR_HXSCS Descriptions
Figure 8-284. FMan Memory Read Cycle Statistic Register (FMPR_MRCS)
Table 8-298. FMPR_MRCS Field Descriptions
Figure 8-285. FMan Memory Write Cycle Statistic Register (FMPR_MWCS)
Table 8-299. FMPR_MWCS Field Descriptions
Figure 8-286. FMan Memory Read Stall Cycle Statistic Register Format
Table 8-300. FMPR_MRSCS Field Descriptions
Figure 8-287. FMan Memory Write Stalled Cycle Statistic Register (FMPR_MWSCS)
Table 8-301. FMPR_MWSCS Field Descriptions
Figure 8-288. FPM Command Stall Cycle Statistic Register (FMPR_FCSCS)
Table 8-302. FMPR_FCSCS Field Descriptions
Figure 8-289. Parser Debug Flow x Trap Event Statistic Registers (FMPR_PDxTES)
Table 8-303. FMPR_PDxTES Field Descriptions
8.8.3.1.5 Parser Debug Registers
Figure 8-290. Parser Debug Control Register (FMPR_PDC)
Table 8-304. FMPR_PDC Field Descriptions
Figure 8-291. Parser Debug Flow x Trap y Configuration Registers (FMPR_PDxTyC)
Table 8-305. FMPR_PDxTyC Field Descriptions
Figure 8-292. Parser Debug Flow x Trap y Value Registers (FMPR_PDxTyV)
Table 8-306. FMPR_PDxTyV Field Descriptions
Figure 8-293. Parser Debug Flow x Trap y Mask Registers (FMPR_PDxTyM)
Table 8-307. FMPR_PDxTyM Field Descriptions
8.8.4 Parser Functional Description
8.8.4.1 Benefits of Using Hard Header Examination Sequences (HXSs)
8.8.4.2 Benefits of Using Soft Examination Sequences
8.8.4.3 Parse Array Functionality Overview
8.8.4.4 Parser Inputs/Outputs
8.8.4.4.1 Possible Parser NIA Action Codes
Table 8-308. Possible NIA Action Codes
8.8.4.4.2 Parser Inputs/Outputs from/to FMan Memory
Table 8-309. Parser Inputs/Outputs from/to FMan Memory
8.8.4.4.3 Purpose of the Status Region of the Frame Descriptor (FD[STATUS])
Table 8-310. FD[STATUS] Bits
8.8.4.4.4 Hard Parser Next Instruction Address (HPNIA)
Table 8-311. HPNIA Next Processing Modules
Figure 8-294. HPNIA Flow
8.8.4.4.5 FMan Controller Activation for Parsing
8.8.4.5 Parse Tree and Hard Header Examination Sequences (HXSs)
Figure 8-295. Hard Parse Tree
8.8.4.5.1 What is a Parse Shell?
Figure 8-296. Shell
8.8.4.5.2 Soft Sequence Attachment
Figure 8-297. Soft Extension
Table 8-312. Hard HXS-Soft Sequence Attachment
Table 8-313. Ethernet HXS Configuration
Table 8-314. PPPoE+PPP HXS Configuration
Table 8-315. VLAN HXS Configuration
Table 8-316. MPLS HXS Configuration
Table 8-317. IPv4 HXS Configuration
Table 8-318. IPv6 HXS Configuration
Table 8-319. TCP HXS Configuration
Table 8-320. UDP HXS Configuration
8.8.4.5.3 Line-up Enable Confirmation Mask
Table 8-321. Line-up Enable Confirmation Mask
8.8.4.5.4 Line-Up Confirmation Vector
Figure 8-298. Line-Up Confirmation Example
8.8.4.6 P4080Parse Array
Table 8-322. Parse Array
Table 8-323. Parse Array Field Descriptions
8.8.4.7 Hard Header Examination Sequences (HXSs)
8.8.4.7.1 L2 HXS - Ethernet
Figure 8-299. Ethernet Frame Formats
Table 8-324. Ethernet-EtherType to Next HXS Mapping
8.8.4.7.2 L2 HXS-VLAN
Figure 8-300. VLAN Tag
Table 8-325. VLAN-EtherType to Next HXS Mapping
8.8.4.7.3 L2 HXS-LLC + SNAP
Table 8-326. 802.3/SNAP-EtherType to Next HXS Mapping
8.8.4.7.4 L2 HXS-PPPoE+PPP
Table 8-327. Ethernet with PPPoE Frame Format
Table 8-328. PPPoE+PPP-Protocol to Next HXS Mapping
8.8.4.7.5 L2 HXS-MPLS
Table 8-329. MPLS Label to Next HXS Mapping
Figure 8-301. MPLS (RFC3032)
8.8.4.7.6 L2 HXS-L2 Results
Table 8-330. L2R Decoded
Table 8-331. L2R Result Codes
8.8.4.7.7 L3 HXS
8.8.4.7.8 L3 HXS-IPv4
Table 8-332. IPv4-Protocol to Next HXS Mapping
8.8.4.7.9 L3 HXS-IPv6
Table 8-333. IPv6 Extension Header Parsing
Table 8-334. IPv6-Next Header to Next HXS Mapping
8.8.4.7.10 L3 HXS - GRE version 0
Figure 8-302. GRE (RFC2890)
Table 8-335. GRE-Protocol Type to Next HXS Mapping
8.8.4.7.11 L3 HXS-Minimal Encapsulation
Figure 8-303. Minimal Encapsulation for IP
Table 8-336. Min. Encap.-Protocol to Next HXS Mapping
8.8.4.7.12 L3 HXS-Other L3 Shell
8.8.4.7.13 L3 HXS-L3 Results
Table 8-337. L3R Decoded
Table 8-338. First L3R Info Results Decoded
Table 8-339. Last L3R Info Results Decoded
Table 8-340. L3R Error Result Codes
8.8.4.7.14 L4 HXS-TCP
Figure 8-304. TCP (RFC793)
8.8.4.7.15 L4 HXS-UDP
Figure 8-305. UDP (RFC768)
8.8.4.7.16 L4 HXS-IPSec
Figure 8-306. AH (RFC2402)
Figure 8-307. ESP (RFC2406)
8.8.4.7.17 L4 HXS-SCTP
Figure 8-308. SCTP (RFC2960)
8.8.4.7.18 L4 HXS-DCCP
Figure 8-309. DCCP (RFC4340)
8.8.4.7.19 L4 HXS-Other L4 Shell
8.8.4.7.20 L4 HXS-L4 Results
Table 8-341. L4R Decoded
Table 8-342. L4R Result Codes
8.8.4.7.21 Shim Result
Table 8-343. ShimR Decoded
8.8.4.8 256 Limit Event Handling
8.8.4.9 Soft HXS Parse Array updates
Table 8-344. Parse Array Required Field Population
8.8.4.10 Parse Result
Table 8-345. Parse Result
Table 8-346. Parse Result Field Description
8.8.4.11 Soft Parser
8.8.4.12 Parsing Exception handling
8.8.4.12.1 Invalid Soft Parser Instruction
8.8.4.12.2 Parse Cycle Limit
8.8.4.12.3 Parse Error Status
8.8.4.12.4 Soft Parser Parsing Events
8.8.4.12.5 Frame Received on a Disabled Port or Unsupported Port
8.8.4.12.6 Frame Received with 256 Limit or Error(s) in Parse Result/FD[STATUS]
8.8.4.13 Parser Debug Functionality
8.8.4.13.1 Parser Trace
Table 8-347. FMan Parser Debug Trace Format
8.8.4.13.2 Debug Traps
8.8.5 Parser Initialization Information
8.8.5.1 Start-Up or Restart
8.9 Frame Manager-Key Generator
8.9.1 KeyGen Overview
8.9.1.1 KeyGen Features Summary
8.9.2 KeyGen Memory Map/Register Definition
8.9.2.1 KeyGen Indirect Memory Space
8.9.2.2 KeyGen Memory Map
Table 8-348. KeyGen Memory Map
8.9.3 KeyGen Detailed Register Definitions
8.9.3.1 KeyGen General Configuration Register (FMKG_GCR)
Figure 8-310. KeyGen General Configuration Register (FMKG_GCR)
Table 8-349. FMKG_GCR Field Descriptions
8.9.3.2 KeyGen Error Event Register (FMKG_EER)
Figure 8-311. KeyGen Error Event Register (FMKG_EER)
Table 8-350. FMKG_EER Field Descriptions
8.9.3.3 KeyGen Error Event Enable Register (FMKG_EEER)
Figure 8-312. KeyGen Error Event Enable Register (FMKG_EEER)
Table 8-351. FMKG_EEER Field Descriptions
8.9.3.4 KeyGen Scheme Error Event Register (FMKG_SEER)
Figure 8-313. KeyGen Scheme Error Event Register (FMKG_SEER)
Table 8-352. FMKG_SEER Field Descriptions
8.9.3.5 KeyGen Global Status Register (FMKG_GSR)
Figure 8-314. KeyGen Global Status Register (FMKG_GSR)
Table 8-353. FMKG_GSR Field Descriptions
8.9.3.6 KeyGen Total Packet Counter Register (FMKG_TPC)
Figure 8-315. KeyGen Total Packet Counter Register (FMKG_TPC)
Table 8-354. FMKG_TPC Field Descriptions
8.9.3.7 KeyGen Soft Error Capture Register (FMKG_SERC)
Figure 8-316. KeyGen Soft Error Capture Register (FMKG_SERC)
Table 8-355. FMKG_SERC Field Descriptions
8.9.3.8 KeyGen Frame Data Offset Register (FMKG_FDOR)
Figure 8-317. KeyGen Frame Data Offset Register (FMKG_FDOR)
Table 8-356. FMKG_FDOR Field Descriptions
8.9.3.9 KeyGen Global Default Value Register (FMKG_GDVR)
Figure 8-318. KeyGen Global Default Value Register (FMKG_GDVR)
Table 8-357. FMKG_GDVR Field Descriptions
8.9.3.10 KeyGen Force Error Event Register (FMKG_FEER)
Figure 8-319. KeyGen Force Error Event Register (FMKG_FEER)
Table 8-358. FMKG_FEER Field Descriptions
8.9.3.11 KeyGen Action Register (FMKG_AR)
Figure 8-320. KeyGen Action Register (FMKG_AR)
Table 8-359. FMKG_AR Field Descriptions
8.9.3.12 KeyGen Scheme Entry Memory Map
8.9.3.12.1 KeyGen Scheme Entry MODE Register (AWR1_RFMODE_FMKG_SE_MODE)
Figure 8-321. KeyGen Scheme Entry MODE Register (AWR1_RFMODE_FMKG_SE_MODE)
Table 8-360. AWR1_RFMODE_FMKG_SE_MODE Field Descriptions
8.9.3.12.2 KeyGen Scheme Entry Extract Known Fields Command Register (AWR2_RFMODE_FMKG_SE_EKFC)
Figure 8-322. KeyGen Scheme Entry Extract Known Fields Command Register (AWR2_RFMODE_FMKG_SE_EKFC)
Table 8-361. AWR2_RFMODE_FMKG_SE_EKFC Field Descriptions
8.9.3.12.3 KeyGen Scheme Entry Extract Known Default Value Register (AWR3_RFMODE_FMKG_SE_EKDV)
Figure 8-323. KeyGen Scheme Entry Extract Known Default Value Register (AWR3_RFMODE_FMKG_SE_EKDV)
Table 8-362. AWR3_RFMODE_FMKG_SE_EKDV Field Descriptions
8.9.3.12.4 KeyGen Scheme Bit Mask Command High Register (AWR4_RFMODE_FMKG_SE_BMCH)
Figure 8-324. KeyGen Scheme Bit Mask Command High Register (AWR4_RFMODE_FMKG_SE_BMCH)
Table 8-363. AWR4_RFMODE_FMKG_SE_BMCH Field Descriptions
8.9.3.12.5 KeyGen Scheme Bit Mask Command Low Register (AWR5_RFMODE_FMKG_SE_BMCL)
Figure 8-325. KeyGen Scheme Bit Mask Command Low Register (AWR5_RFMODE_FMKG_SE_BMCL)
Table 8-364. AWR5_RFMODE_FMKG_SE_BMCL Field Descriptions
Figure 8-326. Bit Mask Command Example
8.9.3.12.6 KeyGen Scheme Entry Frame Queue Base Register (AWR6_RFMODE_FMKG_SE_FQB)
Figure 8-327. KeyGen Scheme Entry Frame Queue Base Register (AWR6_RFMODE_FMKG_SE_FQB)
Table 8-365. AWR6_RFMODE_FMKG_SE_FQB Field Descriptions
8.9.3.12.7 KeyGen Scheme Entry Hash Configuration Register (AWR7_RFMODE_FMKG_SE_HC)
Figure 8-328. KeyGen Scheme Entry Hash Configuration Register (AWR7_RFMODE_FMKG_SE_HC)
Table 8-366. AWR7_RFMODE_FMKG_SE_HC Field Descriptions
8.9.3.12.8 KeyGen Scheme Entry Policer Profile Command Register (AWR8_RFMODE_FMKG_SE_PPC)
Figure 8-329. KeyGen Scheme Entry Policer Profile Command Register (AWR8_RFMODE_FMKG_SE_PPC)
Table 8-367. Register AWR8_RFMODE_FMKG_SE_PPC Bits Description
8.9.3.12.9 KeyGen Scheme Entry Generic Extract Command Register (AWR<9+i>_RFMODE_FMKG_SE_GEC)
Figure 8-330. KeyGen Scheme Entry Generic Extract Command Register (AWR<9+i>_RFMODE_FMKG_SE_GEC)
Table 8-368. AWR<9+i>_RFMODE_FMKG_SE_GEC (0 ..7) Field Descriptions
Figure 8-331. Key Generation Command Description
8.9.3.12.10 KeyGen Scheme Entry Statistic Packet Counter Register (AWR17_RFMODE_FMKG_SE_SPC)
Figure 8-332. KeyGen Scheme Entry Statistic Packet Counter Register (AWR17_RFMODE_FMKG_SE_SPC)
Table 8-369. AWR17_RFMODE_FMKG_SE_SPC Field Descriptions
8.9.3.12.11 KeyGen Scheme Entry Default Value Register (AWR<18+i>_RFMODE_FMKG_SE_DV)
Figure 8-333. KeyGen Scheme Entry Default Value Register (AWR<18+i>_RFMODE_FMKG_SE_DV)
Table 8-370. AWR<18+i>_RFMODE_FMKG_SE_DV Field Descriptions
8.9.3.12.12 KeyGen Scheme Entry Coarse Classification Bit Select Register (AWR20_RFMODE_FMKG_SE_CCBS)
Figure 8-334. KeyGen Scheme Entry Coarse Classification Bit Select Register (AWR20_RFMODE_FMKG_SE_CCBS)
Table 8-371. AWR20_RFMODE_FMKG_SE_CCBS Field Descriptions
8.9.3.12.13 KeyGen Scheme Entry Match Vector Register (AWR21_RFMODE_FMKG_SE_MV)
Figure 8-335. KeyGen Scheme Entry Match Vector Register (AWR21_RFMODE_FMKG_SE_MV)
Table 8-372. AWR21_RFMODE_FMKG_SE_MV Field Descriptions
8.9.3.13 KeyGen Classification Plan Entry Memory Map
Figure 8-336. Classification Plan Tables
8.9.3.13.1 KeyGen Classification Plan Entry Register (AWR<1+i>_RFMODE_FMKG_CPE)
Figure 8-337. KeyGen Classification Plan Entry Register (AWR<1+i>_RFMODE_FMKG_CPE)
Table 8-373. AWR<1+i>_RFMODE_FMKG_CPE Field Descriptions
8.9.3.14 KeyGen Port Partition Configuration
8.9.3.14.1 KeyGen Port Entry Scheme Partition Register (AWR1_RFMODE_FMKG_PE_SP)
Figure 8-338. KeyGen Port Entry Scheme Partition Register (AWR1_RFMODE_FMKG_PE_SP)
Table 8-374. AWR1_RFMODE_FMKG_PE_SP Field Descriptions
8.9.3.14.2 KeyGen Port Entry Classification Plan Partition Register (AWR2_RFMODE_FMKG_PE_CPP)
Figure 8-339. KeyGen Port Entry Classification Plan Partition Register (AWR2_RFMODE_FMKG_PE_CPP)
Table 8-375. AWR2_RFMODE_FMKG_PE_CPP Field Descriptions
8.9.3.15 KeyGen Debug Registers
8.9.3.15.1 KeyGen Debug Control Register (FMKG_DCR)
Figure 8-340. KeyGen Debug Control Register (FMKG_DCR)
Table 8-376. FMKG_DCR Field Descriptions
8.9.3.15.2 KeyGen Debug Flow Trap Counter Register (FMKG_DTC)
Figure 8-341. KeyGen Debug Flow Trap Counter Register (FMKG_DTC)
Table 8-377. FMKG_DTC Field Descriptions
8.9.3.15.3 KeyGen Debug Flow Trap Configuration Register (FMKG_DTCR)
Figure 8-342. KeyGen Debug Flow Trap Configuration Register (FMKG_DTCR)
Table 8-378. FMKG_DTCR Field Descriptions
8.9.3.15.4 KeyGen Debug Flow Trap Value Register (FMKG_DTVR)
Figure 8-343. KeyGen Debug Flow Trap Value Register (FMKG_DTVR)
Table 8-379. FMKG_DTVR Field Descriptions
8.9.3.15.5 KeyGen Debug Flow Trap Mask Register (FMKG_DTMR)
Figure 8-344. KeyGen Debug Flow Trap Mask Register (FMKG_DTMR)
Table 8-380. FMKG_DTMR Field Descriptions
8.9.4 KeyGen Functional Description
Figure 8-345. KeyGen Functional Flow
8.9.4.1 Scheme Selection
8.9.4.1.1 Direct Scheme Selection
8.9.4.1.2 Indirect Scheme Selection
Figure 8-346. Scheme Selection Flow
Table 8-381. LECM Configuration
Table 8-382. Scheme Match Vector Configuration
Table 8-383. HXS Configuration
8.9.4.2 Key Generation
8.9.4.2.1 Extract Known Field Commands
8.9.4.2.2 Generic Known Field Commands
8.9.4.2.3 Field Validation
8.9.4.3 Hash Value Generation
8.9.4.3.1 Symmetric Hash Function
8.9.4.4 Keygen Distribution Function Value (KDFV)
8.9.4.4.1 OR Data Vector Generation
8.9.4.5 Frame Queue ID (FQID) Generation
Figure 8-347. FQID Generation Flow
8.9.4.6 Policer Profile Number (PNUM) Generation
8.9.4.7 KeyGen Storage Profile ID Generation
8.9.4.8 Coarse Classification Base (CCBASE) Update
Figure 8-348. Coarse Classification Offset Calculation
8.9.4.9 Next Invoke Action (NIA) Generation
8.9.4.10 KeyGen Inputs and Outputs
8.9.4.10.1 KeyGen NIA Action Codes
Figure 8-349. KeyGen NIA Bit Mapping
Table 8-384. KeyGen NIA Action Code (AC) Fields Description
8.9.4.10.2 KeyGen Inputs from FMan Memory
Table 8-385. KeyGen Read Data
8.9.4.10.3 KeyGen Outputs to FMan Memory
Table 8-386. KeyGen Write Data
Table 8-387. Frame Descriptor (FD) Status Entry
Table 8-388. Action Descriptor (AD) Entry
8.9.4.11 KeyGen Debug Functionality
8.9.4.11.1 Debug Trace
Table 8-389. FMan KeyGen Trace Debug Format
8.9.4.11.2 Debug Traps
8.9.5 KeyGen Initialization
8.9.5.1 Initialize the KeyGen Port Partition
8.9.5.2 Initialize the KeyGen Scheme Entry
8.9.5.2.1 Initialize a Full Scheme Entry
8.9.5.2.2 Initialize a Partial Scheme Entry
8.9.5.3 Initialize the KeyGen Classification Plan Group
8.9.5.3.1 Initialize a Full Classification Plan Group
8.9.5.3.2 Initialize a Partial Classification Plan Group
8.9.6 KeyGen Events
Table 8-390. Types of KeyGen Events
8.10 Frame Manager-FMan Controller
8.10.1 FMan Controller Overview
8.10.2 FMan Controller Features Summary
8.10.3 FMan Controller Memory Map/Register Definition
Table 8-391. FMan controller Configuration Data Download Registers
8.10.3.1 FMan Controller Configuration Data Address Register (FMCDADDR)
Figure 8-350. FMan Controller Configuration Data, Address Register
Table 8-392. FMCDADDR Field Descriptions
8.10.3.2 FMan Controller Configuration Data, Data Register (FMCDDATA)
Figure 8-351. FMan Controller Configuration Data, Data Register
Table 8-393. FMCDDATA Field Descriptions
8.10.3.3 FMan Controller Configuration Data Ready Register (FMCDREADY)
Figure 8-352. FMan Controller Configuration Data Ready Register
Table 8-394. FMCDREADY Field Descriptions
8.10.3.4 FMan Controller Configuration Data Download Flow
Table 8-395. FMan Controller Configuration Data Download Flow
8.10.4 FMan Controller Functional Description
8.10.4.1 Matching Table Structure
Figure 8-353. Matching Table Structure
8.10.4.2 TTL/Hop Limit Equals One Identification
8.10.4.3 Look-Up on Internal Context Fields
8.10.4.4 Using KeyGen HASH Result for Indexed Look-Up
Figure 8-354. KeyGen/Coarse Classification HASH Look-Up Flow
Figure 8-355. IC Look-Up with Aging mechanism
8.10.4.5 Coarse Classification Generic Flow
Figure 8-356. Coarse Classification Generic Flow Example
8.10.5 Coarse Classification Action Descriptors (ADs)
8.10.5.1 New Classification Result
Figure 8-357. New Classification Result Action Descriptor (AD) (Type = 00)
Table 8-396. New Classification Action Descriptor (Type = 00)
8.10.5.2 Keep Classification Result
Figure 8-358. Keep Classification Action Descriptor (Type = 10)
8.10.5.3 Table Descriptor
Table 8-397. Keep Classification Action Descriptor (Type=10)
Figure 8-359. Table Descriptor (Type = 01)
Table 8-398. Table Descriptor (Type = 01)
Table 8-399. Operation Code Description
8.10.6 First Coarse Classification Action Descriptor Location
8.10.7 Coarse Classification Search Tree Example
8.10.8 FMan Controller Important Often-Overlooked Details
8.10.8.1 Dynamic Update of Coarse Classification Tables
8.10.8.1.1 Direct Table Access Direct Access Sync Flow
Figure 8-360. Old AD First 4 Bytes Temporary Value (Type = 11)
Table 8-400. Old AD First 4 Bytes Temporary Value (Type = 11)
8.10.8.1.2 Direct Table access Host Command Sync Flow
8.10.8.1.3 Full Host Command Flow
8.10.9 Ethernet Independent Mode (IM)
8.10.9.1 IM Introduction
8.10.9.2 IM Features
8.10.9.3 Frame Transmitter Overview
Figure 8-361. Independent Mode Flow
Figure 8-362. Transmit Structures
8.10.9.4 Frame Receiver Overview
Figure 8-363. Receive Structures
8.10.9.5 IM Programming Model
8.10.9.5.1 Parameter RAM
Table 8-401. Independent Mode Global Parameter RAM
Figure 8-364. Independent Mode Register
Table 8-402. Independent Mode Register Field Descriptions
8.10.9.5.2 Rx Queue Descriptor
Figure 8-365. Rx Queue Descriptor
Table 8-403. Rx Queue Descriptor Field Descriptions
8.10.9.5.3 FPM FMan Controller Event Register
Figure 8-366. FPM FMan Controller Event Register
Table 8-404. FPM FMan Controller Event Register Field Descriptions
8.10.9.5.4 RxBD
Figure 8-367. RxBD data structure
Table 8-405. RxBD Data Structure Field Descriptions
8.10.9.5.5 Tx Queue Descriptor
Figure 8-368. Tx Queue Descriptor
Table 8-406. Tx Queue Descriptor Field Descriptions
8.10.9.5.6 TxBD
Figure 8-369. TxBD Data Structure
Table 8-407. TxBD Data Structure Field Descriptions
8.10.9.6 IM Application Notes
8.10.10 Host Commands
8.10.10.1 Host Command Introduction
8.10.10.2 Host Command Features
8.10.10.3 Host Command Flow
Figure 8-370. Host Command Flow
8.10.10.4 Host Command Programing Model
Figure 8-371. Data Frame Description for Host Command (External Memory)
8.10.10.4.1 Host Command Opcode Register (HCOR)
Figure 8-372. Host Command Opcode Register
Table 8-408. Host Command Opcode Register Description
8.10.10.4.2 Host Command Action Register (HCAR)
Figure 8-373. Policer Profile Host Command Action Register
Figure 8-374. KeyGen Scheme/Classification Plan/Port Partition Host Command Action Register
Figure 8-375. HCAR for Aging Support
8.10.10.4.3 Host Command Extra Register (HCER)
Figure 8-376. KeyGen Scheme Host Command Extra Register
Table 8-409. KeyGen Scheme Host Command Extra Register Field Descriptions
Figure 8-377. Policer Profile Host Command Extra Register
Table 8-410. Policer Profile Host Command Extra Register Field Descriptions
Figure 8-378. HCER for Dynamic Update of Coarse Classification Tables Command
Figure 8-379. HCER for Aging Support
8.10.10.4.4 Host Command Sequence Number (HCSN)
8.10.10.4.5 Host Command Data Area
Table 8-411. Host Command Data Area Description
8.10.10.5 Host Command Application Notes
Figure 8-380. Example Per-Port IP Reassembly Data Structures
8.10.11 FMan Controller NIA-Action Codes
Table 8-412. FMan controller Dispatch Commands
8.11 Frame Manager-MACsec
8.11.1 MACsec Overview
8.11.2 MACsec Features Summary
8.11.3 MACsec Memory Map/Register Definition
Table 8-413. MACsec Individual Register Memory Map
8.11.3.1 Register Descriptions
8.11.3.2 MACsec Configuration
8.11.3.2.1 MACsec configuration (MACSEC_CFG)
Figure 8-381. MACsec configuration Register Format
Table 8-414. Register MACSEC_CFG Bits Description
8.11.3.2.2 MACsec EtherType (MACSEC_ET)
Figure 8-382. MACsec EtherType Register Format
Table 8-415. Register MACSEC_ET Bits Description
8.11.3.2.3 Maximum Frame Length (MACSEC_MFL)
Figure 8-383. Maximum Frame Length Register Format
Table 8-416. Register MACSEC_MFL Bits Description
8.11.3.2.4 TX Packet Number exhaustion threshold (MACSEC_TPNET)
Figure 8-384. TX Packet Number exhaustion threshold Register Format
Table 8-417. Register MACSEC_TPNET Bits Description
8.11.3.2.5 RX SC access select (MACSEC_RXSCA)
Figure 8-385. RX SC access select Register Format
Table 8-418. Register MACSEC_RXSCA Bits Description
8.11.3.2.6 TX SC access select (MACSEC_TXSCA)
Figure 8-386. TX SC access select Register Format
Table 8-419. Register MACSEC_TXSCA Bits Description
8.11.3.3 RX Configuration, Status and Statistic
8.11.3.3.1 RX Secure Channel Identifier first half (MACSEC_RXSCI1H)
Figure 8-387. RX Secure Channel Identifier first half Register Format
Table 8-420. Register MACSEC_RXSCI1H Bits Description
8.11.3.3.2 RX Secure Channel Identifier second half (MACSEC_RXSCI2H)
Figure 8-388. RX Secure Channel Identifier second half Register Format
Table 8-421. Register MACSEC_RXSCI2H Bits Description
8.11.3.3.3 RX Secure Channel configuration (MACSEC_RXSCCFG)
Figure 8-389. RX Secure Channel configuration Register Format
Table 8-422. Register MACSEC_RXSCCFG Bits Description
8.11.3.3.4 replayWindow (MACSEC_RPW)
Figure 8-390. replayWindow Register Format
Table 8-423. Register MACSEC_RPW Bits Description
8.11.3.3.5 SecY Controlled Port Statistics
8.11.3.3.6 ifInOctets First Half Statistic (MACSEC_IFIO1HS)
Figure 8-391. ifInOctets first half Statistic Register Format
Table 8-424. Register MACSEC_IFIO1HS Bits Description
8.11.3.3.7 ifInOctets Second Half Statistic (MACSEC_IFIO2HS)
Figure 8-392. ifInOctets second half Statistic Register Format
Table 8-425. Register MACSEC_IFIO2HS Bits Description
8.11.3.3.8 ifInUcastPkts Statistic (MACSEC_IFIUPS)
Figure 8-393. ifInUcastPkts Statistic Register Format
Table 8-426. Register MACSEC_IFIUPS Bits Description
8.11.3.3.9 ifInMulticastPkts Statistic (MACSEC_IFIMPS)
Figure 8-394. ifInMulticastPkts Statistic Register Format
Table 8-427. Register MACSEC_IFIMPS Bits Description
8.11.3.3.10 ifInBroadcastPkts Statistic (MACSEC_IFIBPS)
Figure 8-395. ifInBroadcastPkts Statistic Register Format
Table 8-428. Register MACSEC_IFIBPS Bits Description
8.11.3.3.11 InOctetsValidated first half Statistic (MACSEC_INOV1HS)
Figure 8-396. InOctetsValidated first half Statistic Register Format
Table 8-429. Register MACSEC_INOV1HS Bits Description
8.11.3.3.12 InOctetsValidated second half Statistic (MACSEC_INOV2HS)
Figure 8-397. InOctetsValidated second half Statistic Register Format
Table 8-430. Register MACSEC_INOV2HS Bits Description
8.11.3.3.13 InOctetsDecrypted first half Statistic (MACSEC_INOD1HS)
Figure 8-398. InOctetsDecrypted first half Statistic Register Format
Table 8-431. Register MACSEC_INOD1HS Bits Description
8.11.3.3.14 InOctetsDecrypted second half Statistic (MACSEC_INOD2HS)
Figure 8-399. InOctetsDecrypted second half Statistic Register Format
Table 8-432. Register MACSEC_INOD2HS Bits Description
8.11.3.3.15 Per RX SC statistics
8.11.3.3.16 RX Secure Channel InPktsUnchecked Statistic (MACSEC_RXSCIPUS)
Figure 8-400. RX Secure Channel InPktsUnchecked Statistic Register Format
Table 8-433. Register MACSEC_RXSCIPUS Bits Description
8.11.3.3.17 RX Secure Channel InPktsDelayed Statistic (MACSEC_RXSCIPDS)
Figure 8-401. RX Secure Channel InPktsDelayed Statistic Register Format
Table 8-434. Register MACSEC_RXSCIPDS Bits Description
8.11.3.3.18 RX Secure Channel InPktsLate Statistic (MACSEC_RXSCIPLS)
Figure 8-402. RX Secure Channel InPktsLate Statistic Register Format
Table 8-435. Register MACSEC_RXSCIPLS Bits Description
8.11.3.3.19 RX AN InNotUsingSA Statistic (MACSEC_RXANINUSS)
Figure 8-403. RX AN InNotUsingSA Statistic Register Format
Table 8-436. Register MACSEC_RXANINUSS (0 .. 3) Bits Description
8.11.3.3.20 RX AN InPktsUnusedSA Statistic (MACSEC_RXANIPUSS)
Figure 8-404. RX AN InPktsUnusedSA Statistic Register Format
Table 8-437. Register MACSEC_RXANIPUSS (0 .. 3) Bits Description
8.11.3.3.21 RX Security Association A configuration and status (MACSEC_RXSAACS)
Figure 8-405. RX Security Association A configuration and status Register Format
Table 8-438. Register MACSEC_RXSAACS Bits Description
8.11.3.3.22 RX Security Association A nextPN (MACSEC_RXSAANPN)
Figure 8-406. RX Security Association A nextPN Register Format
Table 8-439. Register MACSEC_RXSAANPN Bits Description
8.11.3.3.23 RX Security Association A lowestPN (MACSEC_RXSAALPN)
Figure 8-407. RX Security Association A lowestPN Register Format
Table 8-440. Register MACSEC_RXSAALPN Bits Description
8.11.3.3.24 RX Security Association A InPktsOK Statistic (MACSEC_RXSAAIPOS)
Figure 8-408. RX Security Association A InPktsOK Statistic Register Format
Table 8-441. Register MACSEC_RXSAAIPOS Bits Description
8.11.3.3.25 RX Security Association A key 1 of 4 (MACSEC_RXSAKA1Q)
Figure 8-409. RX Security Association A key 1 of 4 Register Format
Table 8-442. Register MACSEC_RXSAKA1Q Bits Description
8.11.3.3.26 RX Security Association A key 2 of 4 (MACSEC_RXSAKA2Q)
Figure 8-410. RX Security Association A key 2 of 4 Register Format
Table 8-443. Register MACSEC_RXSAKA2Q Bits Description
8.11.3.3.27 RX Security Association A key 3 of 4 (MACSEC_RXSAKA3Q)
Figure 8-411. RX Security Association A key 3 of 4 Register Format
Table 8-444. Register MACSEC_RXSAKA3Q Bits Description
8.11.3.3.28 RX Security Association A key 4 of 4 (MACSEC_RXSAKA4Q)
Figure 8-412. RX Security Association A key 4 of 4 Register Format
Table 8-445. Register MACSEC_RXSAKA4Q Bits Description
8.11.3.3.29 RX Security Association A hash 1 of 4 (MACSEC_RXSAHA1Q)
Figure 8-413. RX Security Association A hash 1 of 4 Register Format
Table 8-446. Register MACSEC_RXSAHA1Q Bits Description
8.11.3.3.30 RX Security Association A hash 2 of 4 (MACSEC_RXSAHA2Q)
Figure 8-414. RX Security Association A hash 2 of 4 Register Format
Table 8-447. Register MACSEC_RXSAHA2Q Bits Description
8.11.3.3.31 RX Security Association A hash 3 of 4 (MACSEC_RXSAHA3Q)
Figure 8-415. RX Security Association A hash 3 of 4 Register Format
Table 8-448. Register MACSEC_RXSAHA3Q Bits Description
8.11.3.3.32 RX Security Association A hash 4 of 4 (MACSEC_RXSAHA4Q)
Figure 8-416. RX Security Association A hash 4 of 4 Register Format
Table 8-449. Register MACSEC_RXSAHA4Q Bits Description
8.11.3.3.33 RX Security Association A InPktsInvalid Statistic (MACSEC_RXSAAIPIS)
Figure 8-417. RX Security Association A InPktsInvalid Statistic Register Format
Table 8-450. Register MACSEC_RXSAAIPIS Bits Description
8.11.3.3.34 RX Security Association A InPktsNotValid Statistic (MACSEC_RXSAAIPNVS)
Figure 8-418. RX Security Association A InPktsNotValid Statistic Register Format
Table 8-451. Register MACSEC_RXSAAIPNVS Bits Description
8.11.3.3.35 RX Security Association B configuration and status (MACSEC_RXSABCS)
Figure 8-419. RX Security Association B configuration and status Register Format
Table 8-452. Register MACSEC_RXSABCS Bits Description
8.11.3.3.36 RX Security Association B nextPN (MACSEC_RXSABNPN)
Figure 8-420. RX Security Association B nextPN Register Format
Table 8-453. Register MACSEC_RXSABNPN Bits Description
8.11.3.3.37 RX Security Association B lowestPN (MACSEC_RXSABLPN)
Figure 8-421. RX Security Association B lowestPN Register Format
Table 8-454. Register MACSEC_RXSABLPN Bits Description
8.11.3.3.38 RX Security Association B InPktsOK Statistic (MACSEC_RXSABIPOS)
Figure 8-422. RX Security Association B InPktsOK Statistic Register Format
Table 8-455. Register MACSEC_RXSABIPOS Bits Description
8.11.3.3.39 RX Security Association B key 1 of 4 (MACSEC_RXSAKB1Q)
Figure 8-423. RX Security Association B key 1 of 4 Register Format
Table 8-456. Register MACSEC_RXSAKB1Q Bits Description
8.11.3.3.40 RX Security Association B key 2 of 4 (MACSEC_RXSAKB2Q)
Figure 8-424. RX Security Association B key 2 of 4 Register Format
Table 8-457. Register MACSEC_RXSAKB2Q Bits Description
8.11.3.3.41 RX Security Association B key 3 of 4 (MACSEC_RXSAKB3Q)
Figure 8-425. RX Security Association B key 3 of 4 Register Format
Table 8-458. Register MACSEC_RXSAKB3Q Bits Description
8.11.3.3.42 RX Security Association B key 4 of 4 (MACSEC_RXSAKB4Q)
Figure 8-426. RX Security Association B key 4 of 4 Register Format
Table 8-459. Register MACSEC_RXSAKB4QBits Description
8.11.3.3.43 RX Security Association B hash 1 of 4 (MACSEC_RXSAHB1Q)
Figure 8-427. RX Security Association B hash 1 of 4 Register Format
Table 8-460. Register MACSEC_RXSAHB1Q Bits Description
8.11.3.3.44 RX Security Association B hash 2 of 4 (MACSEC_RXSAHB2Q)
Figure 8-428. RX Security Association B hash 2 of 4 Register Format
Table 8-461. Register MACSEC_RXSAHB2Q Bits Description
8.11.3.3.45 RX Security Association B hash 3 of 4 (MACSEC_RXSAHB3Q)
Figure 8-429. RX Security Association B hash 3 of 4 Register Format
Table 8-462. Register MACSEC_RXSAHB3Q Bits Description
8.11.3.3.46 RX Security Association B hash 4 of 4 (MACSEC_RXSAHB4Q)
Figure 8-430. RX Security Association B hash 4 of 4 Register Format
Table 8-463. Register MACSEC_RXSAHB4QBits Description
8.11.3.3.47 RX Security Association B InPktsInvalid Statistic (MACSEC_RXSABIPIS)
Figure 8-431. RX Security Association B InPktsInvalid Statistic Register Format
Table 8-464. Register MACSEC_RXSABIPIS Bits Description
8.11.3.3.48 RX Security Association B InPktsNotValid Statistic (MACSEC_RXSABIPNVS)
Figure 8-432. RX Security Association B InPktsNotValid Statistic Register Format
Table 8-465. Register MACSEC_RXSABIPNVS Bits Description
8.11.3.4 TX Configuration, Status and Statistic
8.11.3.4.1 TX Secure Channel Identifier first half (MACSEC_TXSCI1H)
Figure 8-433. TX Secure Channel Identifier first half Register Format
Table 8-466. Register MACSEC_TXSCI1H Bits Description
8.11.3.4.2 TX Secure Channel Identifier second half (MACSEC_TXSCI2H)
Figure 8-434. TX Secure Channel Identifier second half Register Format
Table 8-467. Register MACSEC_TXSCI2H Bits Description
8.11.3.4.3 TX Secure Channel configuration (MACSEC_TXSCCFG)
Figure 8-435. TX Secure Channel configuration and status Register Format
Table 8-468. Register MACSEC_TXSCCFG Bits Description
8.11.3.4.4 SecY Controlled Port Statistics
8.11.3.4.5 ifOutOctets first half Statistic (MACSEC_IFOO1HS)
Figure 8-436. ifOutOctets first half Statistic Register Format
Table 8-469. Register MACSEC_IFOO1HS Bits Description
8.11.3.4.6 ifOutOctets second half Statistic (MACSEC_IFOO2HS)
Figure 8-437. ifOutOctets second half Statistic Register Format
Table 8-470. Register MACSEC_IFOO2HS Bits Description
8.11.3.4.7 ifOutUcastPkts Statistic (MACSEC_IFOUPS)
Figure 8-438. ifOutUcastPkts Statistic Register Format
Table 8-471. Register MACSEC_IFOUPS Bits Description
8.11.3.4.8 ifOutMulticastPkts Statistic (MACSEC_IFOMPS)
Figure 8-439. ifOutMulticastPkts Statistic Register Format
Table 8-472. Register MACSEC_IFOMPS Bits Description
8.11.3.4.9 ifOutBroadcastPkts Statistic (MACSEC_IFOBPS)
Figure 8-440. ifOutBroadcastPkts Statistic Register Format
Table 8-473. Register MACSEC_IFOBPS Bits Description
8.11.3.4.10 OutPktsUntagged Statistic (MACSEC_OPUS)
Figure 8-441. OutPktsUntagged Statistic Register Format
Table 8-474. Register MACSEC_OPUS Bits Description
8.11.3.4.11 OutPktsTooLong Statistic (MACSEC_OPTLS)
Figure 8-442. OutPktsTooLong Statistic Register Format
Table 8-475. Register MACSEC_OPTLS Bits Description
8.11.3.4.12 OutOctetsProtected first half Statistic (MACSEC_OOP1HS)
Figure 8-443. OutOctetsProtected first half Statistic Register Format
Table 8-476. Register MACSEC_OOP1HS Bits Description
8.11.3.4.13 OutOctetsProtected second half Statistic (MACSEC_OOP2HS)
Figure 8-444. OutOctetsProtected second half Statistic Register Format
Table 8-477. Register MACSEC_OOP2HS Bits Description
8.11.3.4.14 OutOctetsEncrypted first half Statistic (MACSEC_OOE1HS)
Figure 8-445. OutOctetsEncrypted first half Statistic Register Format
Table 8-478. Register MACSEC_OOE1HS Bits Description
8.11.3.4.15 OutOctetsEncrypted second half Statistic (MACSEC_OOE2HS)
Figure 8-446. OutOctetsEncrypted second half Statistic Register Format
Table 8-479. Register MACSEC_OOE2HS Bits Description
8.11.3.4.16 TX Security Association A configuration and status (MACSEC_TXSAACS)
Figure 8-447. TX Security Association A configuration and status Register Format
Table 8-480. Register MACSEC_TXSAACS Bits Description
8.11.3.4.17 TX Security Association A nextPN (MACSEC_TXSAANPN)
Figure 8-448. TX Security Association A nextPN Register Format
Table 8-481. Register MACSEC_TXSAANPN Bits Description
8.11.3.4.18 TX Security Association A OutPktsProtected Statistic (MACSEC_TXSAAOPPS)
Figure 8-449. TX Security Association A OutPktsProtected Statistic Register Format
Table 8-482. Register MACSEC_TXSAAOPPS Bits Description
8.11.3.4.19 TX Security Association A OutPktsEncrypted Statistic (MACSEC_TXSAAOPES)
Figure 8-450. TX Security Association A OutPktsEncrupted Statistic Register Format
Table 8-483. Register MACSEC_TXSAAOPES Bits Description
8.11.3.4.20 TX Security Association A key 1 of 4 (MACSEC_TXSAKA1Q)
Figure 8-451. TX Security Association A key 1 of 4 Register Format
Table 8-484. Register MACSEC_TXSAKA1Q Bits Description
8.11.3.4.21 TX Security Association A key 2 of 4 (MACSEC_TXSAKA2Q)
Figure 8-452. TX Security Association A key 2 of 4 Register Format
Table 8-485. Register MACSEC_TXSAKA2Q Bits Description
8.11.3.4.22 TX Security Association A key 3 of 4 (MACSEC_TXSAKA3Q)
Figure 8-453. TX Security Association A key 3 of 4 Register Format
Table 8-486. Register MACSEC_TXSAKA3Q Bits Description
8.11.3.4.23 TX Security Association A key 4 of 4 (MACSEC_TXSAKA4Q)
Figure 8-454. TX Security Association A key 4 of 4 Register Format
Table 8-487. Register MACSEC_TXSAKA4Q Bits Description
8.11.3.4.24 TX Security Association A hash 1 of 4 (MACSEC_TXSAHA1Q)
Figure 8-455. TX Security Association A hash 1 of 4 Register Format
Table 8-488. Register MACSEC_TXSAHA1Q Bits Description
8.11.3.4.25 TX Security Association A hash 2 of 4 (MACSEC_TXSAHA2Q)
Figure 8-456. TX Security Association A hash 2 of 4 Register Format
Table 8-489. Register MACSEC_TXSAHA2Q Bits Description
8.11.3.4.26 TX Security Association A hash 3 of 4 (MACSEC_TXSAHA3Q)
Figure 8-457. TX Security Association A hash 3 of 4 Register Format
Table 8-490. Register MACSEC_TXSAHA3Q Bits Description
8.11.3.4.27 TX Security Association A hash 4 of 4 (MACSEC_TXSAHA4Q)
Figure 8-458. TX Security Association A hash 4 of 4 Register Format
Table 8-491. Register MACSEC_TXSAHA4Q Bits Description
8.11.3.4.28 TX Security Association B configuration and status (MACSEC_TXSABCS)
Figure 8-459. TX Security Association B configuration and status Register Format
Table 8-492. Register MACSEC_TXSABCS Bits Description
8.11.3.4.29 TX Security Association B nextPN (MACSEC_TXSABNPN)
Figure 8-460. TX Security Association B nextPN Register Format
Table 8-493. Register MACSEC_TXSABNPN Bits Description
8.11.3.4.30 TX Security Association B OutPktsProtected Statistic (MACSEC_TXSABOPPS)
Figure 8-461. TX Security Association B OutPktsProtected Statistic Register Format
Table 8-494. Register MACSEC_TXSABOPPS Bits Description
8.11.3.4.31 TX Security Association B OutPktsEncrypted Statistic (MACSEC_TXSABOPES)
Figure 8-462. TX Security Association B OutPktsEncrupted Statistic Register Format
Table 8-495. Register MACSEC_TXSABOPES Bits Description
8.11.3.4.32 TX Security Association B key 1 of 4 (MACSEC_TXSAKB1Q)
Figure 8-463. TX Security Association B key 1 of 4 Register Format
Table 8-496. Register MACSEC_TXSAKB1Q Bits Description
8.11.3.4.33 TX Security Association B key 2 of 4 (MACSEC_TXSAKB2Q)
Figure 8-464. TX Security Association B key 2 of 4 Register Format
Table 8-497. Register MACSEC_TXSAKB2Q Bits Description
8.11.3.4.34 TX Security Association B key 3 of 4 (MACSEC_TXSAKB3Q)
Figure 8-465. TX Security Association B key 3 of 4 Register Format
Table 8-498. Register MACSEC_TXSAKB3Q Bits Description
8.11.3.4.35 TX Security Association B key 4 of 4 (MACSEC_TXSAKB4Q)
Figure 8-466. TX Security Association B key 4 of 4 Register Format
Table 8-499. Register MACSEC_TXSAKB4Q Bits Description
8.11.3.4.36 TX Security Association B hash 1 of 4 (MACSEC_TXSAHB1Q)
Figure 8-467. TX Security Association B hash 1 of 4 Register Format
Table 8-500. Register MACSEC_TXSAHB1Q Bits Description
8.11.3.4.37 TX Security Association B hash 2 of 4 (MACSEC_TXSAHB2Q)
Figure 8-468. TX Security Association B hash 2 of 4 Register Format
Table 8-501. Register MACSEC_TXSAHB2Q Bits Description
8.11.3.4.38 TX Security Association B hash 3 of 4 (MACSEC_TXSAHB3Q)
Figure 8-469. TX Security Association B hash 3 of 4 Register Format
Table 8-502. Register MACSEC_TXSAHB3Q Bits Description
8.11.3.4.39 TX Security Association B hash 4 of 4 (MACSEC_TXSAHB4Q)
Figure 8-470. TX Security Association B hash 4 of 4 Register Format
Table 8-503. Register MACSEC_TXSAHB4Q Bits Description
8.11.3.5 Global configuration and Status
8.11.3.5.1 MACsec IP Block Revision 1 Register (MACSEC_IP_REV_1)
Figure 8-471. MACsec IP Block Revision 1 Register (MACSEC_IP_REV_1)
Table 8-504. Register MACSEC_IP_REV_1 Bits Description
8.11.3.5.2 MACsec IP Block Revision 2 Register (MACSEC_IP_REV_2)
Figure 8-472. MACsec IP Block Revision 2 Register (MACSEC_IP_REV_2)
Table 8-505. Register MACSEC_IP_REV_2 Bits Description
8.11.3.5.3 MACsec Event Register (MACSEC_EVR)
Figure 8-473. MACsec Event Register Format
Table 8-506. Register MACSEC_EVR Bits Description
8.11.3.5.4 MACsec Event Enable Register (MACSEC_EVER)
Figure 8-474. MACsec Event Enable Register Format
Table 8-507. Register MACSEC_EVER Bits Description
8.11.3.5.5 MACsec Error Register (MACSEC_ERR)
Figure 8-475. MACsec Error Register Format
Table 8-508. Register MACSEC_ERR Bits Description
8.11.3.5.6 MACsec Error Enable Register (MACSEC_ERER)
Figure 8-476. MACsec Event Enable Register Format
Table 8-509. Register MACSEC_ERER Bits Description
8.11.3.5.7 MACsec Memory ECC Error Capture Registers (MACSEC_MEEC)
Figure 8-477. MACsec Memory ECC Error Capture Register Format
Table 8-510. Register MACSEC_MEEC Bits Description
8.11.3.5.8 MACsec Idle status Registers (MACSEC_IDLE)
Figure 8-478. MACsec Idle status Register Format
Table 8-511. Register MACSEC_IDLE Bits Description
8.11.3.6 MACsec RX Global Statistics
8.11.3.6.1 ifInOctetsCp first half Statistic (MACSEC_IFIOCP1HS)
Figure 8-479. ifInOctetsCp first half Statistic Register Format
Table 8-512. Register MACSEC_IFIOCP1HS Bits Description
8.11.3.6.2 ifInOctetsCp second half Statistic (MACSEC_IFIOCP2HS)
Figure 8-480. ifInOctetsCp second half Statistic Register Format
Table 8-513. Register MACSEC_IFIOCP2HS Bits Description
8.11.3.6.3 ifInUcastPktsCp Statistic (MACSEC_IFIUPCPS)
Figure 8-481. ifInUcastPktsCp Statistic Register Format
Table 8-514. Register MACSEC_IFIUPCPS Bits Description
8.11.3.6.4 ifInMulticastPktsCp Statistic (MACSEC_IFIMPCPS)
Figure 8-482. ifInMulticastPktsCp Statistic Register Format
Table 8-515. Register MACSEC_IFIMPCPS Bits Description
8.11.3.6.5 ifInBroadcastPktsCp Statistic (MACSEC_IFIBPCPS)
Figure 8-483. ifInBroadcastPktsCp Statistic Register Format
Table 8-516. Register MACSEC_IFIBPCPS Bits Description
8.11.3.6.6 ifInOctetsUp first half Statistic (MACSEC_IFIOUP1HS)
Figure 8-484. ifInOctetsUp first half Statistic Register Format
Table 8-517. Register MACSEC_IFIOUP1HS Bits Description
8.11.3.6.7 ifInOctetsUp second half Statistic (MACSEC_IFIOUP2HS)
Figure 8-485. ifInOctetsUp second half Statistic Register Format
Table 8-518. Register MACSEC_IFIOUP2HS Bits Description
8.11.3.6.8 ifInUcastPktsUp Statistic (MACSEC_IFIUPUPS)
Figure 8-486. ifInUcastPktsUp Statistic Register Format
Table 8-519. Register MACSEC_IFIUPUPS Bits Description
8.11.3.6.9 ifInMulticastPktsUp Statistic (MACSEC_IFIMPUPS)
Figure 8-487. ifInMulticastPktsUp Statistic Register Format
Table 8-520. Register MACSEC_IFIMPUPS Bits Description
8.11.3.6.10 ifInBroadcastPktsUp Statistic (MACSEC_IFIBPUPS)
Figure 8-488. ifInBroadcastPktsUp Statistic Register Format
Table 8-521. Register MACSEC_IFIBPUPS Bits Description
8.11.3.6.11 InPktsWithoutTag Statistic (MACSEC_INPWTS)
Figure 8-489. InPktsWithoutTag Statistic Register Format
Table 8-522. Register MACSEC_INPWTS Bits Description
8.11.3.6.12 InPktsKaY Statistic (MACSEC_INPKAYS)
Figure 8-490. InPktsKaY Statistic Register Format
Table 8-523. Register MACSEC_INPKAYS Bits Description
8.11.3.6.13 InPktsBadTag Statistic (MACSEC_INPBTS)
Figure 8-491. InPktsBadTag Statistic Register Format
Table 8-524. Register MACSEC_INPBTS Bits Description
8.11.3.6.14 InPktsSCINotFound Statistic (MACSEC_IPSNFS)
Figure 8-492. InPktsSCINotFound Statistic Register Format
Table 8-525. Register MACSEC_IPSNFS Bits Description
8.11.3.6.15 InPktsUnsupportedEC Statistic (MACSEC_IPUECS)
Figure 8-493. InPktsUnsupportedEC Statistic Register Format
Table 8-526. Register MACSEC_IPUECS Bits Description
8.11.3.6.16 InPktsEponSingleCopyBroadcast Statistic (MACSEC_IPESCBS)
Figure 8-494. InPktsEponSingleCopyBroadcast Statistic Register Format
Table 8-527. Register MACSEC_IPESCBS Bits Description
8.11.3.6.17 InPktsTooLong Statistic (MACSEC_IPTLS)
Figure 8-495. InPktsTooLong Statistic Register Format
Table 8-528. Register MACSEC_IPTLS Bits Description
8.11.3.7 MACsec TX Global Statistics
8.11.3.7.1 OutPktsDiscarded Statistic (MACSEC_OPDS)
Figure 8-496. OutPktsDiscarded Statistic Register Format
Table 8-529. Register MACSEC_OPDS Bits Description
8.11.4 MACsec - Functional Description
8.11.4.1 MACsec frame format
Figure 8-497. 802.1AE MACsec Frame Format
Table 8-530. SecTag TCI and AN
8.11.4.2 RX Frame Processing
8.11.4.2.1 SCI resolution / search
Table 8-531. SCI resolution
8.11.4.2.2 RX Secure Association
8.11.4.2.3 Frame PDU Validation
Table 8-532. SecTag E and C bit validation
8.11.4.2.4 Frame data integrity
Figure 8-498. 802.1AE MACsec Frame example with padding
8.11.4.2.5 Frame data confidentiality
8.11.4.2.6 Replay check
8.11.4.2.7 Controlled port vs. uncontrolled port
8.11.4.3 TX Frame Processing
8.11.4.3.1 SCI Insertion
8.11.4.3.2 SecTag generation
8.11.4.3.3 TX Secure Association
8.11.4.3.4 Frame data integrity
8.11.4.3.5 Frame data confidentiality
8.11.4.4 Key and hash value privacy
8.11.4.5 MACsec Bypass
8.11.4.6 Double ECC error handling
8.11.5 MACsec - Initialization Information
8.11.5.1 Startup or re-start
8.11.5.1.1 RX SC and SA configuration
8.11.5.1.2 TX SC and SA configuration
8.11.5.2 Run time configuration change
8.11.5.2.1 Re-key on RX
8.11.5.2.2 Re-Key on TX
8.11.5.2.3 Retire or re-configure a SC
8.11.6 MACsec conformance to 802.1AE standard
Table 8-533. Major capabilities
Table 8-534. Support and use of Service Access Points
Table 8-535. MAC status and point-to-point parameters
Table 8-536. Secure Frame Generation
Table 8-537. Secure Frame Verification
Table 8-538. MACsec PDU encoding and decoding
Table 8-539. Key Agreement Entity LMI
Table 8-540. Management - control and status information
Table 8-541. Management - basic controls
Table 8-542. Management - control over secure communication
Table 8-543. Management - statistics
Table 8-544. Additional fully conformant Cipher Suite capabilities
Table 8-545. Additional variant Cipher Suite capabilities
8.12 Frame Manager-Policer
8.12.1 Policer Overview
8.12.2 Policer Features
8.12.3 Policer Modes of Operation
8.12.3.1 Disabled Mode
8.12.3.2 Active Mode
8.12.4 Policer Memory Map and Register Definition
Table 8-546. Policer Memory Map
8.12.4.1 FMan Policer General Configuration Register (FMPL_GCR)
Figure 8-499. FMan Policer General Configuration Register (FMPL_GCR)
Table 8-547. FMPL_GCR Field Descriptions
8.12.4.2 FMan Policer Global Status Register (FMPL_GSR)
Figure 8-500. FMan Policer Global Status Register (FMPL_GSR)
Table 8-548. FMPL_GSR Field Descriptions
8.12.4.3 FMan Policer Event Register (FMPL_EVR)
Figure 8-501. FMan Policer Event Register (FMPL_EVR)
Table 8-549. FMPL_EVR Field Descriptions
8.12.4.4 FMan Policer Interrupt Enable Register (FMPL_IER)
Figure 8-502. FMan Policer Interrupt Enable Register (FMPL_IER)
Table 8-550. FMPL_IER Field Descriptions
8.12.4.5 FMan Policer Interrupt Force Register (FMPL_IFR)
Figure 8-503. FMan Policer Interrupt Force Register (FMPL_IFR)
Table 8-551. FMPL_IFR Field Descriptions
8.12.4.6 FMan Policer Error Event Register (FMPL_EEVR)
Figure 8-504. FMan Policer Error Event Register (FMPL_EEVR)
Table 8-552. MPL_EEVR Field Descriptions
8.12.4.7 FMan Policer Error Interrupt Enable Register (FMPL_EIER)
Figure 8-505. FMan Policer Error Interrupt Enable Register (FMPL_EIER)
Table 8-553. FMPL_EIER Field Descriptions
8.12.4.8 FMan Policer RED Packet Counter Register (FMPL_RPC)
Figure 8-506. FMan Policer RED Packet Counter Register (FMPL_RPC)
Table 8-554. FMPL_RPC Field Descriptions
8.12.4.9 FMan Policer YELLOW Packet Counter Register (FMPL_YPC)
Figure 8-507. FMan Policer YELLOW Packet Counter Register (FMPL_YPC)
Table 8-555. FMPL_YPC Field Descriptions
8.12.4.10 FMan Policer Recolored RED Packet Counter Register (FMPL_RRPC)
Figure 8-508. FMan Policer Recolored RED Packet Counter Register (FMPL_RRPC)
Table 8-556. FMPL_RRPC Field Descriptions
8.12.4.11 FMan Policer Recolored YELLOW Packet Counter Register (FMPL_RYPC)
Figure 8-509. FMan Policer Recolored YELLOW Packet Counter Register (FMPL_RYPC)
Table 8-557. FMPL_RYPC Field Descriptions
8.12.4.12 FMan Policer Total Packet Counter Register (FMPL_TPC)
Figure 8-510. FMan Policer Total Packet Counter Register (FMPL_TPC)
Table 8-558. FMPL_TPC Field Descriptions
8.12.4.13 FMan Policer Frame Length Mismatch Counter Register (FMPL_FLMC)
Figure 8-511. FMan Policer Frame Length Mismatch Counter Register (FMPL_FLMC)
Table 8-559. MPL_FLMC Field Descriptions
8.12.4.14 FMan Policer Profile Action Register (FMPL_PAR)
Figure 8-512. FMan Policer Profile Action Register (FMPL_PAR)
Table 8-560. FMPL_PAR Field Descriptions
8.12.4.15 FMan Policer Profile Entry Access Word Registers (FMPL_PE*)
Figure 8-513. FMan Policer Profile Entry Access Word Registers (FMPL_PE*)
Table 8-561. FMPL_PE* Field Descriptions
8.12.4.16 FMan Policer Soft Error Capture Register (FMPL_SERC)
Figure 8-514. FMan Policer Soft Error Capture Register (FMPL_SERC)
Table 8-562. FMPL_SERC Field Descriptions
8.12.4.17 FMan Policer Uninitialized Profile Capture Register (FMPL_UPCR)
Figure 8-515. FMan Policer Uninitialized Profile Capture Register (FMPL_UPCR)
Table 8-563. FMPL_UPCR Field Descriptions
8.12.4.18 FMan Policer Debug Trace Configuration Register (FMPL_DTRCR)
Figure 8-516. FMan Policer Debug Trace Configuration Register (FMPL_DTRCR)
Table 8-564. FMPL_DTRCR Field Descriptions
8.12.4.19 FMan Policer Flow A Debug Trap Configuration Registers (FMPL_FADBTCRn)
Figure 8-517. FMan Policer Flow A Debug Trap Configuration Registers (FMPL_FADBTCRn)
Table 8-565. FMPL_FADBTCRn Field Descriptions
8.12.4.20 FMan Policer Flow A Debug Value Registers (FMPL_FADBVALRn)
Figure 8-518. FMan Policer Flow A Debug Value Registers (FMPL_FADBVALRn)
Table 8-566. FMPL_FADBVALRn Field Descriptions
8.12.4.21 FMan Policer Flow A Debug Trap Mask Registers (FMPL_FADBTMRn)
Figure 8-519. FMan Policer Flow A Debug Trap Mask Registers (FMPL_FADBTMRn)
Table 8-567. FMPL_FADBTMRn Field Descriptions
8.12.4.22 FMan Policer Flow A Debug Trap Match Counter Register (FMPL_FADBTMC)
Figure 8-520. FMan Policer Flow A Debug Trap Match Counter Register (FMPL_FADBTMC)
Table 8-568. FMPL_FADBTMC Field Descriptions
8.12.4.23 FMan Policer Default Profile Mapping Register (FMPL_DPMR)
Figure 8-521. FMan Policer Default Profile Mapping Register (FMPL_DPMR)
Table 8-569. FMPL_DPMR Field Descriptions
8.12.4.24 FMan Policer Profile Mapping Registers (FMPL_PMRn)
Table 8-570. Port ID to FMPL_PMRn Mapping
Figure 8-522. FMan Policer Profile Mapping Registers (FMPL_PMRn)
Table 8-571. FMPL_PMRn Field Descriptions
8.12.4.25 Policer Profile Entry Memory Map
8.12.4.25.1 FMan Policer Profile Entry MODE Configuration Word Register (MODE)
Figure 8-523. FMan Policer Profile Entry MODE Configuration Word Register (MODE)
Table 8-572. MODE Field Descriptions
8.12.4.25.2 GREEN Next Invoked Action Configuration Word Register (GNIA)
Figure 8-524. GREEN Next Invoked Action Configuration Word Register (GNIA)
Table 8-573. GNIA Field Descriptions
8.12.4.25.3 YELLOW Next Invoked Action Address Configuration Word Register (YNIA)
Figure 8-525. YELLOW Next Invoked Action Address Configuration Word Register (YNIA)
Table 8-574. YNIA Field Descriptions
8.12.4.25.4 RED Next Invoked Action Configuration Word Register (RNIA)
Figure 8-526. RED Next Invoked Action Configuration Word (RNIA)
Table 8-575. RNIA Field Descriptions
8.12.4.25.5 Committed Information Rate Configuration Word Register (CIR)
Figure 8-527. Committed Information Rate Configuration Word (CIR)
Table 8-576. CIR Field Descriptions
8.12.4.25.6 Committed Burst Size Configuration Word Register (CBS)
Figure 8-528. Committed Burst Size Configuration Word (CBS)
Table 8-577. CBS Field Descriptions
8.12.4.25.7 Peak/Excess Information Rate Configuration Word Register (PIR_EIR)
Figure 8-529. Peak/Excess Information Rate Configuration Word (PIR_EIR)
Table 8-578. PIR_EIR Field Descriptions
8.12.4.25.8 Peak/Excess Burst Size Configuration Word Register (PBS_EBS)
Figure 8-530. Peak/Excess Burst Size Configuration Word Register (PBS_EBS)
Table 8-579. PBS_EBS Field Descriptions
8.12.4.25.9 Last Timestamp Variable Register (LTS)
Figure 8-531. Last Timestamp Variable Register (LTS)
Table 8-580. LTS Field Descriptions
8.12.4.25.10 Committed Token-Bucket Status Variable Register (CTS)
Figure 8-532. Committed Token-Bucket Status Variable Register (CTS)
Table 8-581. CTS Field Descriptions
8.12.4.25.11 Peak/Excess Token-Bucket Status Variable Register (PTS_ETS)
Figure 8-533. Peak/Excess Token-Bucket Status Variable Register (PTS_ETS)
Table 8-582. PTS_ETS Field Descriptions
8.12.4.25.12 GREEN Packet Counter Variable Register (GPC)
Figure 8-534. GREEN Packet Counter Variable Register (GPC)
Table 8-583. GPC Field Descriptions
8.12.4.25.13 YELLOW Packet Counter Variable Register (YPC)
Figure 8-535. YELLOW Packet Counter Variable Register (YPC)
Table 8-584. YPC Field Descriptions
8.12.4.25.14 RED Packet Counter Variable Register (RPC)
Figure 8-536. RED Packet Counter Variable Register (RPC)
Table 8-585. RPC Field Descriptions
8.12.4.25.15 Recolored YELLOW Packet Counter Variable Register (RYPC)
Figure 8-537. Recolored YELLOW Packet Counter Variable Register (RYPC)
Table 8-586. RYPC Field Descriptions
8.12.4.25.16 Recolored RED Packet Counter Variable Register (RRPC)
Figure 8-538. Recolored RED Packet Counter Variable Register (RRPC)
Table 8-587. RRPC Field Descriptions
8.12.5 Policer Functional Description
8.12.5.1 Policer Flow Description
8.12.5.1.1 Receiving an Incoming Packet
8.12.5.1.2 Avoiding Calculation Errors in Policer Profile Using Refresh Packets
8.12.5.1.3 Atomic Profile Update
8.12.5.2 Policer Profile Operation Modes
8.12.5.2.1
8.12.5.2.2 Pass-Through Modes
8.12.5.2.3 Color-Aware Pass-Through Mode
8.12.5.2.4 Color-Blind Pass-Through Mode
8.12.5.3 Traffic Metering and Marking Modes
8.12.5.3.1 Token Bucket Metering Principles
Figure 8-539. Token Bucket Concept
8.12.5.3.2 Rate Measurement Implementation by Time-Stamp
8.12.5.3.3 RFC-2698 Profile Mode Description
8.12.5.3.4 RFC-2698 Profile Mode Configuration
Figure 8-540. RFC-2968 Token Buckets Implementation
8.12.5.3.5 RFC-2698 Profile Mode Metering and Marking
8.12.5.3.6 RFC-4115 Profile Mode Description
8.12.5.3.7 RFC-4115 Profile Mode Configuration
8.12.5.3.8 RFC-4115 Profile Mode Metering and Marking
8.12.5.4 Functional Description-Next Invoked Action (NIA)
8.12.5.5 Debug Support
8.12.5.5.1 Packet-Based Debug Trace
8.12.5.5.2 Debug Flow Traps
8.12.5.5.3 Debug Trace
Table 8-588. FMan Policer Debug Trace Format
Table 8-589. Debug Flags and PNUM Dump Field Descriptions
Table 8-590. Debug Mode Dump Field Descriptions
8.12.5.5.4 Flow-Based Debug Trace
8.12.6 FMan Policer-Initialization Information
8.12.6.1 Reset Initialization
8.12.6.1.1 Hard Reset Sequence
8.12.6.1.2 Activating the PRAM Self Initialization
8.12.6.1.3 FMan Soft Reset Initialization
8.12.6.2 Profile Entry Initialization
8.12.6.3 PRAM Re-Initialization after Software Reset
8.12.6.3.1 Specific Profile Re-initialization
8.12.6.3.2 Full PRAM Re-Initialization
8.12.6.4 Profile Mapping Initialization
8.12.6.4.1 Next Invoked Action (NIA)
Table 8-591. NIA Example
8.12.6.5 Profile Concatenation Initialization
8.12.6.6 Writing to the Statistic Counters
8.12.7 Application Information
8.12.7.1 Load Spreading and Policing Traffic per Core
Figure 8-541. Load Spreading Application Example
8.12.7.2 Profile Concatenation for Combined PACKET/BYTE Based Policing
Figure 8-542. Double Policing Scheme by Profile Concatenation
8.12.7.3 Profile Concatenation for Aggregating Multiple Streams
Figure 8-543. Aggregating Multiple Streams by Profile Concatenation
8.12.7.4 Profile Concatenation with Per Color Aggregation
Chapter 9 Pattern Matching Engine (PME)
9.1 PME Overview
9.1.1 Overview
Figure 9-1. High Level Block Diagram of the PM
9.1.2 Features
9.1.3 Modifications from Pattern Matcher 1.X
9.1.4 CoreNet SrcID, LIODN and PID
9.1.4.1 CoreNet SrcID
9.1.4.2 CoreNet LIODN and PID
9.2 Memory Map and Register Definition
Table 9-1. Pattern Matcher Overall Register Memory Map
Table 9-2. PM Individual Register Memory Map
9.2.1 Pattern Matcher Frame Agent Control Registers
9.2.1.1 ISR-Interrupt Status Register
Figure 9-2. ISR Format
Table 9-3. ISR Field Descriptions
9.2.1.2 IER-Interrupt Enable Register
Figure 9-3. IER Format
Table 9-4. IER Field Descriptions
9.2.1.3 ISDR-Interrupt Status Disable Register
Figure 9-4. ISDR Format
Table 9-5. ISDR Field Descriptions
9.2.1.4 IIR-Interrupt Inhibit Register
Figure 9-5. IIR Format
Table 9-6. IIR Field Descriptions
9.2.1.5 IFR-Interrupt Force Register
Figure 9-6. IFR Format
Table 9-7. IFR Field Descriptions
9.2.1.6 RLL-Report Length Limit
Figure 9-7. Report Length Limit Register Format
Table 9-8. Report Length Limit Register Field Descriptions
9.2.1.7 CDCR-Caching Disable Control Register
Figure 9-8. Caching Disable Control Register Format
Table 9-9. Caching Disable Control Register Field Descriptions
9.2.1.8 TRUNCI-Output Truncated Incidence Counter
Figure 9-9. TRUNCI Format
Table 9-10. TRUNCI Field Descriptions
9.2.1.9 RBC-Read Byte Counter
Figure 9-10. RBC Format
Table 9-11. RBC Field Descriptions
9.2.1.10 ESR-Error Status Register
Figure 9-11. ESR Format
Table 9-12. ESR Field Descriptions
9.2.1.11 ECR0-Error Capture Register 0 and ECR1-Error Capture Register 1
Figure 9-12. ESR0-1 Format
Table 9-13. ESR0-1 Field Descriptions
9.2.1.12 EFQC-Exclusive Frame Queue Control
Figure 9-13. EFQC Format
Table 9-14. EFQC Field Descriptions
9.2.1.13 SRAM_ADDR-SRAM Address
Figure 9-14. SRAM_ADDR Format
Table 9-15. SRAM_ADDR Field Descriptions
9.2.1.14 SRAM_RDAT-SRAM Read Data
Figure 9-15. SRAM_RDAT Format
Table 9-16. SRAM_RDAT Field Descriptions
9.2.1.15 SRAM_WDAT-SRAM Write Data
Figure 9-16. SRAM_WDAT Format
Table 9-17. SRAM_WDAT Field Descriptions
9.2.1.16 FACONF-Frame Agent Configuration
Figure 9-17. FACONF Format
Table 9-18. FACONF Field Descriptions
9.2.1.17 PMSTAT-Pattern Matcher Status
Figure 9-18. PMSTAT Format
Table 9-19. PMSTAT Field Descriptions
9.2.1.18 FAMCR-Frame Agent Memory Control Register
Figure 9-19. FAMCR Format
Table 9-20. FAMCR Field Descriptions
9.2.1.19 PMTR-Performance Monitor Threshold Register
Figure 9-20. PMTR Format
Table 9-21. PMTR Field Descriptions
9.2.1.20 PEHD-PM Error Handling Disables
Figure 9-21. PEHD Format
Table 9-22. PEHD Field Descriptions
9.2.1.21 BSC0-Buffer Size Configuration 0 through BSC7-Buffer Size Configuration 7
Figure 9-22. BSC0 Format
Table 9-23. BSC0 Field Descriptions
9.2.1.22 QMBFD0-Queue Manager Bypass Frame Descriptor 0 through QMBFD3-Queue Manager Bypass Frame Descriptor 3
Figure 9-23. QMBFD0 Format
Table 9-24. QMBFD0 Field Descriptions
9.2.1.23 QMBCTXTAH-Queue Manager Bypass CONTEXT_A High and QMBCTXTAL-Queue Manager Bypass CONTEXT_A Low
Figure 9-24. QMBCTXTAH Format
Table 9-25. QMBCTXTAH Field Descriptions
Figure 9-25. QMBCTXTAL Format
Table 9-26. QMBCTXTAL Field Descriptions
9.2.1.24 QMBCTXTB-Queue Manager Bypass CONTEXT_B
Figure 9-26. QMBCTXTB Format
Table 9-27. QMBCTXTB Field Descriptions
9.2.1.25 QMBCTL-Queue Manager Bypass Control
Figure 9-27. QMBCTL Format
Table 9-28. QMBCTL Field Descriptions
9.2.1.26 ECC1BES-ECC 1-Bit Error Status
Figure 9-28. ECC1BES Format
Table 9-29. ECC1BES Field Descriptions
9.2.1.27 ECC2BES-ECC 2-Bit Error Status
Figure 9-29. ECC2BES Format
Table 9-30. ECC2BES Field Descriptions
9.2.1.28 ECCADDR-ECC Address
Figure 9-30. ECCADDR Format
Table 9-31. ECCADDR Field Descriptions
9.2.1.29 ECCCODE-ECC Code
Figure 9-31. ECCCODE Format
Table 9-32. ECCCODE Field Descriptions
9.2.1.30 TBT0ECC1TH-2-byte Trigger 0 ECC 1-Bit Threshold
Figure 9-32. TBT0ECC1TH Format
Table 9-33. TBT0ECC1TH Field Descriptions
9.2.1.31 TBT0ECC1EC-2-byte Trigger 0 ECC 1-Bit Error Count
Figure 9-33. TBT0ECC1EC Format
Table 9-34. TBT0ECC1EC Field Descriptions
9.2.1.32 TBT1ECC1TH-2-byte Trigger 1 ECC 1-Bit Threshold
Figure 9-34. TBT1ECC1TH Format
Table 9-35. TBT1ECC1TH Field Descriptions
9.2.1.33 TBT1ECC1EC-2-byte Trigger 1 ECC 1-Bit Error Count
Figure 9-35. TBT1ECC1EC Format
Table 9-36. TBT1ECC1EC Field Descriptions
9.2.1.34 VLT0ECC1TH-Variable Length Trigger 0 ECC 1-Bit Threshold
Figure 9-36. VLT0ECC1TH Format
Table 9-37. VLT0ECC1TH Field Descriptions
9.2.1.35 VLT0ECC1EC-Variable Length Trigger 0 ECC 1-Bit Error Count
Figure 9-37. VLT0ECC1EC Format
Table 9-38. VLT0ECC1EC Field Descriptions
9.2.1.36 VLT1ECC1TH-Variable Length Trigger 1 ECC 1-Bit Threshold
Figure 9-38. VLT1ECC1TH Format
Table 9-39. VLT1ECC1TH Field Descriptions
9.2.1.37 VLT1ECC1EC-Variable Length Trigger 1 ECC 1-Bit Error Count
Figure 9-39. VLT1ECC1EC Format
Table 9-40. VLT1ECC1EC Field Descriptions
9.2.1.38 CMECC1TH-Confidence Memory ECC 1-Bit Threshold
Figure 9-40. CMECC1TH Format
Table 9-41. CMECC1TH Field Descriptions
9.2.1.39 CMECC1EC-Confidence Memory ECC 1-Bit Error Count
Figure 9-41. CMECC1EC Format
Table 9-42. CMECC1EC Field Descriptions
9.2.1.40 DXCMECC1TH-DXE Context Memory ECC 1-Bit Threshold
Figure 9-42. DXCMECC1TH Format
Table 9-43. DXCMECC1TH Field Descriptions
9.2.1.41 DXCMECC1EC-DXE Context Memory ECC 1-Bit Error Count
Figure 9-43. DXCMECC1EC Format
Table 9-44. DXCMECC1EC Field Descriptions
9.2.1.42 DXEMECC1TH-DXE Examination Memory ECC 1-Bit Threshold
Figure 9-44. DXEMECC1TH Format
Table 9-45. DXEMECC1TH Field Descriptions
9.2.1.43 DXEMECC1EC-DXE Examination Memory ECC 1-Bit Error Count
Figure 9-45. DXEMECC1EC Format
Table 9-46. DXEMECC1EC Field Descriptions
9.2.2 Key Element Scanner Control Registers
9.2.2.1 STNIB-Statistic - Number of Input Bytes Scanned for Pattern Matching
Figure 9-46. STNIB Format
Table 9-47. STNIB Field Descriptions
9.2.2.2 STNIS-Statistic - Number of Input SUIs
Figure 9-47. STNIS Format
Table 9-48. STNIS Field Descriptions
9.2.2.3 STNTH1-Statistic - Number of Trigger Hits Against 1-Byte Trigger
Figure 9-48. STNTH1 Format
Table 9-49. STNTH1 Field Descriptions
9.2.2.4 STNTH2-Statistic - Number of Trigger Hits Against 2-Byte Trigger
Figure 9-49. STNTH2 Format
Table 9-50. STNTH2 Field Descriptions
9.2.2.5 STNTHV-Statistic - Number of Trigger Hits Against Variable Length Trigger
Figure 9-50. STNTHV Format
Table 9-51. STNTHV Field Descriptions
9.2.2.6 STNTHS-Statistic - Number of Trigger Hits Against Special Trigger
Figure 9-51. STNTHS Format
Table 9-52. STNTHS Field Descriptions
9.2.2.7 STNCH-Statistic - Number of Confidence Stage Hits
Figure 9-52. STNCH Format
Table 9-53. STNCH Field Descriptions
9.2.2.8 SWDB-Software Database Version Reg/Scratch Pad
Figure 9-53. SWDB Format
Table 9-54. SWDB Field Descriptions
9.2.2.9 KVLTS-KES Variable Length Trigger Size
Figure 9-54. KVLTS Format
Table 9-55. KVLTS Field Descriptions
9.2.2.10 KEC-KES Error Configuration
Figure 9-55. KEC Format
Table 9-56. KEC Field Descriptions
9.2.3 Data Examination Engine Control Registers
9.2.3.1 STNPM-Statistic - Number of Pattern Matches
Figure 9-56. STNPM Format
Table 9-57. STNPM Field Descriptions
9.2.3.2 STNS1M-Statistic - Number of SUIs With At Least 1 Pattern Match
Figure 9-57. STNS1M Format
Table 9-58. STNS1M Field Descriptions
9.2.3.3 DRCIC-DXE Pattern Range Counter Index Configuration
Figure 9-58. DRCIC Format
Table 9-59. DRCIC Field Descriptions
9.2.3.4 DRCMC-DXE Pattern Range Counter Mask Configuration
Figure 9-59. DRCMC Format
Table 9-60. DRCMC Field Descriptions
9.2.3.5 STNPMR-Statistic - Number of Pattern Matches Within Range of Indices
Figure 9-60. STNPMR Format
Table 9-61. STNPMR Field Descriptions
9.2.3.6 PDSRBAH-Pattern Description and Stateful Rule Base Address High and PDSRBAL-Pattern Description and Stateful Rule Base Address Low
Figure 9-61. PDSRBAH Format
Table 9-62. PDSRBAH Field Descriptions
Figure 9-62. PDSRBAL Format
Table 9-63. PDSRBAL Field Descriptions
9.2.3.7 DMCR-DXE Memory Control Register
Figure 9-63. DMCR Format
Table 9-64. DMCR Field Descriptions
9.2.3.8 DEC0-DXE Error Configuration 0
Figure 9-64. DEC0 Format
Table 9-65. DEC0 Field Descriptions
9.2.3.9 DEC1-DXE Error Configuration 1
Figure 9-65. DEC1 Format
Table 9-66. DEC1 Field Descriptions
9.2.3.10 DLC-DXE Limit Configuration
Figure 9-66. DLC Format
Table 9-67. DLC Field Descriptions
9.2.4 Stateful Rule Engine Control Registers
9.2.4.1 STNDSR-Statistic: Number of DXE Generated Stateful Rule Executions
Figure 9-67. STNDSR Format
Table 9-68. STNDSR Field Descriptions
9.2.4.2 STNESR-Statistic: Number of End of SUI Generated Stateful Rule Executions
Figure 9-68. STNESR Format
Table 9-69. STNESR Field Descriptions
9.2.4.3 STNS1R-Statistic: Number of SUIs Scanned with at Least 1 Report
Figure 9-69. STNS1R Format
Table 9-70. STNS1R Field Descriptions
9.2.4.4 STNOB-Statistic: Number of Output Bytes Produced in Reports
Figure 9-70. STNOB Format
Table 9-71. STNOB Field Descriptions
9.2.4.5 SCBARH-SRE Context Base Address Register High and SCBARL-SRE Context Base Address Register Low
Figure 9-71. SCBARH Format
Table 9-72. SCBARH Field Descriptions
Figure 9-72. SCBARL Format
Table 9-73. SCBARL Field Descriptions
9.2.4.6 SMCR-SRE Memory Control Register
Figure 9-73. SRE Memory Control Register Format
Table 9-74. SRE Memory Control Register Field Descriptions
9.2.4.7 SREC-SRE Configuration
Figure 9-74. SREC Format
Table 9-75. SREC Field Descriptions
9.2.4.8 ESRP-End of SUI Reaction Pointer Register
Figure 9-75. ESRP Register Format
Table 9-76. ESRP Register Field Descriptions
9.2.4.9 SRRV0-SRE Rule Reset Vector 0
Figure 9-76. SRRV0-SRRV7 Format
Table 9-77. SRRV0-SRRV7 Field Descriptions
9.2.4.10 SRRFI-SRE Rule Reset First Index
Figure 9-77. SRRFI Format
Table 9-78. SRRFI Field Descriptions
9.2.4.11 SRRI-SRE Rule Reset 32-byte Increment
Figure 9-78. SRRI Format
Table 9-79. SRRI Field Descriptions
9.2.4.12 SRRR-SRE Rule Reset Repetitions
Figure 9-79. SRRR Format
Table 9-80. SRRR Field Descriptions
9.2.4.13 SRRWC-SRE Rule Reset Work Configuration
Figure 9-80. SRRWC Format
Table 9-81. SRRWC Field Descriptions
9.2.4.14 SFRCC-SRE Free Running Counter Configuration
Figure 9-81. SFRCC Format
Table 9-82. SFRCC Field Descriptions
9.2.4.15 SEC1-SRE Error Configuration 1
Figure 9-82. SEC1 Format
Table 9-83. SEC1 Field Descriptions
9.2.4.16 SEC2-SRE Error Configuration 2
Figure 9-83. SEC2 Format
Table 9-84. SEC2 Field Descriptions
9.2.4.17 SEC3-SRE Error Configuration 3
Figure 9-84. SEC3 Format
Table 9-85. SEC3 Field Descriptions
9.2.5 Memory Interface Arbiter Control Registers
9.2.5.1 MIA_BYC-MIA Byte Count
Figure 9-85. MIA_BYC Format
Table 9-86. MIA_BYC Field Descriptions
9.2.5.2 MIA_BLC-MIA Block Count
Figure 9-86. MIA_BLC Format
Table 9-87. MIA_BLC Field Descriptions
9.2.5.3 MIA_CE-MIA Count Enable
Figure 9-87. MIA_CE Format
Table 9-88. MIA_CE Field Descriptions
9.2.5.4 MIA_CR-MIA Control Register
Figure 9-88. MIA_CR Format
Table 9-89. MIA_CR Field Descriptions
9.2.6 General Registers
9.2.6.1 LIODNBR-LIODN Base Register
Figure 9-89. LIODNBR Format
Table 9-90. LIODNBR Field Descriptions
9.2.6.2 SRCIDR-Source ID Register
Figure 9-90. SRCIDR Format
Table 9-91. SRCIDR Field Descriptions
9.2.6.3 LIODNR-LIODN Register
Figure 9-91. LIODNR Format
Table 9-92. LIODNR Field Descriptions
9.2.6.4 PM_IP_REV_1-PM IP Block Revision 1 Register
Figure 9-92. PM_IP_REV_1 Format
Table 9-93. PM_IP_REV_1 Field Descriptions
9.2.6.5 PM_IP_REV_2-PM IP Block Revision 2 Register
Figure 9-93. PM_IP_REV_2 Format
Table 9-94. PM_IP_REV_2 Field Descriptions
9.3 Functional Description
Table 9-95. Pattern Matcher Functional Units
9.3.1 Pattern Matcher Frame Agent
Figure 9-94. Pattern Matcher Frame Agent
9.3.1.1 Pattern Matcher Supported Frame Structures
9.3.1.2 PMFA Input Frame Processing
Table 9-96. Processing Mode Enumeration
9.3.1.2.1 Direct Action Mode
Figure 9-95. CONTEXT_A Direct Action Format
Table 9-97. CONTEXT_A Direct Action Format Field Descriptions
9.3.1.2.2 Flow Mode
Figure 9-96. CONTEXT_A Flow Mode Format
Table 9-98. CONTEXT_A Flow Mode Format Field Descriptions
Table 9-99. Flow Context Format
Table 9-100. Residue Data Format
9.3.1.2.3 CONTEXT_B Formatting
Figure 9-97. CONTEXT_B Encoding Scheme
Table 9-101. CONTEXT_B Field Descriptions
9.3.1.2.4 Frame STATUS/CMD Treatment
Table 9-102. Frame Command Code Enumeration
Figure 9-98. STATUS/CMD NOP Command Encoding
Table 9-103. NOP Command Field Descriptions
Figure 9-99. STATUS/CMD Flow Context Write Command Encoding
Table 9-104. Flow Context Write Command Field Descriptions
Figure 9-100. STATUS/CMD Flow Context Read Command Encoding
Table 9-105. Flow Context Read Command Field Descriptions
Figure 9-101. STATUS/CMD PMTCC Command Encoding
Table 9-106. PMTCC Command Field Descriptions
Figure 9-102. STATUS/CMD Scan Command Encoding
Table 9-107. Scan Command Field Descriptions
9.3.1.2.5 Sequence Number
9.3.1.2.6 Start Of Flow and End Of Flow
9.3.1.3 PMFA Output Frame Processing
9.3.1.3.1 NOP Command Output Frame
Figure 9-103. NOP Output Frame STATUS/CMD Encoding Scheme
Table 9-108. NOP Output Frame STATUS/CMD Output Field Descriptions
9.3.1.3.2 Flow Context Write Command Output Frame
Figure 9-104. Flow Context Write Output Frame STATUS/CMD Encoding Scheme
Table 9-109. Flow Context Write Output Frame STATUS/CMD Output Field Descriptions
9.3.1.3.3 Flow Context Read Command Output Frame
Figure 9-105. Flow Context Read Output Frame STATUS/CMD Encoding Scheme
Table 9-110. Flow Context Read Output Frame STATUS/CMD Output Field Descriptions
9.3.1.3.4 PMTCC Command Output Frame
Figure 9-106. PMTCC Output Frame STATUS/CMD Encoding Scheme
Table 9-111. PMTCC Output Frame STATUS/CMD Output Field Descriptions
9.3.1.3.5 Scan Command Output Frame
Figure 9-107. Scan Output Frame STATUS/CMD Encoding Scheme
Table 9-112. Scan Output Frame STATUS/CMD Output Field Descriptions
9.3.1.3.6 Output Frame Buffer Pool ID
9.3.1.3.7 Output Frame Queue ID
9.3.1.3.8 Output Frame Color Field
9.3.1.3.9 Output Frame Formats
9.3.1.3.10 Output Frame Truncation
9.3.1.4 Queue Manager Bypass Mechanism
9.3.1.5 Pattern Matcher Table Configuration Commands
9.3.1.5.1 Pattern Matcher Table Configuration Command Exceptions
9.3.1.5.2 Pattern Matcher Table Configuration Command Formats
Table 9-113. Read Table Entry Command Format
Table 9-114. Read Table Entry Response Format
Table 9-115. Write Table Entry Command Format
Table 9-116. Clear Session Context by Session ID Command Format
9.3.1.6 Exclusive Frame Queue Control Mechanism
9.3.1.7 Pattern Matcher Software Reset
9.3.2 Internal Caching of System Memory Data
9.3.2.1 Flow Context Record Caching
9.3.2.2 Residue Data Caching
9.3.2.3 DXE Pattern Description Caching
9.3.2.4 SRE Session Context Caching
9.3.3 Error Handling and Recovery
9.3.3.1 Operational Errors
9.3.3.2 Serious Errors
9.3.3.2.1 Pattern Matcher Re-initialization
9.3.3.3 Status Code Enumeration
Table 9-117. Status Code Enumeration
9.3.4 Key Element Scanner
Table 9-118. Pre-Defined Group Mapping Table
Table 9-119. Key Element Regex Syntax Examples
Figure 9-108. Trigger and Confidence Stage
9.3.4.1 Trigger Stage
9.3.4.1.1 Variable Length Trigger
Figure 9-109. Variable Length Trigger Table
Figure 9-110. Variable Length Trigger (VLT) Table Hash
Figure 9-111. Variable Length Trigger Table Row Structure
9.3.4.1.2 2-Byte Trigger
Figure 9-112. 2-Byte Trigger (2BT) Table Hash
9.3.4.1.3 1-Byte Trigger
Figure 9-113. 1-Byte Trigger (1BT)
9.3.4.1.4 Special Triggers
Figure 9-114. Special Trigger (ST)
Table 9-120. Special Triggers Description
9.3.4.2 Confidence Stage
Figure 9-115. Confidence Table
Table 9-121. Confidence Table Row Structure
Figure 9-116. Confidence Hash
9.3.4.2.1 Variable Length Trigger to Confidence Mapping
9.3.4.2.2 2-Byte Trigger to Confidence Mapping
9.3.4.2.3 1-Byte Trigger to Confidence Mapping
9.3.4.2.4 Special Trigger to Confidence Mapping
9.3.4.2.5 Guest Transform Code Hash Distribution Function
9.3.4.2.6 Confidence Collision Resolution
Figure 9-117. 2-Byte and Variable Length Trigger Collision Linking Algorithm
Figure 9-118. 1-Byte Trigger Collision Linking Algorithm
9.3.4.2.7 Confidence Mask Codes
Figure 9-119. Confidence Mask Codes
9.3.5 Data Examination Engine
9.3.5.1 Pattern Description
Figure 9-120. DXE NFA Operation
Figure 9-121. DXE 128 byte SUI Window Formats
9.3.5.1.1 Anchor Instruction
9.3.5.1.2 Element Compare Instruction
9.3.5.1.3 Repetition
9.3.5.1.4 Capture
9.3.5.1.5 Inconclusive Match
Table 9-122. DXE Pattern Match Reporting - “Default” Inconclusive Mode
Table 9-123. DXE Pattern Match Reporting - “Alternate” Inconclusive Mode
9.3.5.1.6 Test Line Block Format
Table 9-124. Test Line First Block (128 byte) Format
Table 9-125. Test Line First Block Field Description
Table 9-126. Test Line Extension Block (128-byte) Format
Table 9-127. Instruction Test Line Format
Table 9-128. Instruction Test Line Field Description
Table 9-129. Capture Codes Description
Table 9-130. Element Codes
9.3.5.1.7 Pattern Description Memory Space
Figure 9-122. Pattern Description and Stateful Rule Memory Space
9.3.5.1.8 Pattern Description Block Caching
9.3.5.1.9 Test Line Examples
Table 9-131. Example 1 Head Test Lines
Table 9-132. Example 1 Test Lines
Table 9-133. Example 2 Head Test Lines
Table 9-134. Example 2 Test Lines
9.3.6 Stateful Rule Engine
9.3.6.1 Stateful Rule Physical Structure
Figure 9-123. Reaction Linked List Structure
Table 9-135. 1 Reaction Head 128-Byte Block Format
Table 9-136. Reaction Extension 128-Byte Block Format
9.3.6.2 SRE Instruction Set
9.3.6.2.1 Instruction Set Operands
9.3.6.2.2 Instruction Set Description
Table 9-137. SRE Instructions Format
Table 9-138. SRE Instruction Descriptions
Table 9-139. SRE Instruction Field Descriptions
Table 9-140. Operand Register Select Table (for Load Accumulator Instruction)
Table 9-141. Pattern Match Event Meta Data Registers
9.3.6.3 SRE Context Table
Figure 9-124. SRE Session Context Entries
9.3.6.4 SRE Report Format
9.3.6.4.1 Simple Match Report
Table 9-142. Simple Match Report
9.3.6.4.2 Simple End of SUI Report
Table 9-143. Simple End of SUI Report
9.3.6.4.3 Reaction Reports
9.3.6.4.4 Verbose Reports
Table 9-144. Verbose Mode 1 Report
Table 9-145. Verbose Mode 2 Report - Stateless Rule
Table 9-146. Verbose Mode 2 Report - Dualstate Without Context Rule
Table 9-147. Verbose Mode 2 Report - Dualstate With Context Rule
Table 9-148. Verbose Mode 2 Report - Multistate Rule
Table 9-149. Verbose Mode 3 Report - Dualstate with Context Rule
Table 9-150. Verbose Mode 3 Report - Multistate Rule
9.3.7 Memory Interface Arbiter
9.3.7.1 MIA Read and Write Ports
Table 9-151. MIA read and write port assignments
9.3.7.2 MIA Read/Write Port Arbitration
9.3.7.3 MIA Transaction Cache Attributes
9.3.8 Pattern Matcher Register Interface
9.3.9 Cache Awareness
9.3.9.1 Accesses to Frame Data
9.3.9.1.1 Stashing of Frame Data
9.3.9.1.2 Snooping of Frame Data
9.3.9.2 Accesses to Flow Context and Residue
9.3.9.2.1 Stashing of Flow Context and Residue
9.3.9.2.2 Snooping of Flow Context and Residue
9.3.9.3 Accesses to DXE/SRE Pattern Table Entries
9.3.9.4 Accesses to SRE Context Table
9.3.10 Performance Monitor Event Interface
Table 9-152. Pattern Matcher Performance Monitor Events
9.3.10.1 System Memory Access Performance Monitoring
9.3.10.2 Internal Sequencer Performance Monitoring
9.4 Initialization Information
9.4.1 Initialization Sequence
9.4.1.1 PMFA Register Space Initialization
9.4.1.2 KES Register Space Initialization
9.4.1.3 DXE Register Space Initialization
9.4.1.4 SRE Register Space Initialization
9.4.1.5 Memory Interface Arbiter Register Space Initialization
9.4.1.6 General Register Space Initialization
9.4.1.7 Pattern Matcher Table Configuration
9.4.1.8 Pattern Matcher Operational Mode
9.5 Application Information
Chapter 10 RapidIO Message Manager (RMan)
10.1 RMan Introduction
10.2 RMan Overview
Figure 10-1. RapidIO Message Manager Block Diagram
10.3 RMan Features Summary
10.4 RMan Modes of Operation
10.4.1 Outbound Mode of Operation-Type11 Multicast Mode
10.4.2 Inbound Mode of Operation-Frame Queue Mode
10.5 RMan Memory Map and Register Definition
10.5.1 Global Memory Resource Allocation Map
Table 10-1. RMan Global Memory Map (continued)
10.5.2 Inbound Classification Memory Map
10.5.2.1 Inbound Classification Type8 Memory Map
Table 10-2. RMan Type8 Memory Map
10.5.2.2 Inbound Classification Type9 Memory Map
Table 10-3. RMan Inbound Type9 Classification Mode Memory Map (continued)
10.5.2.3 Inbound Classification Type10 Memory Map
Table 10-4. RMan Inbound Type10 Memory Map (continued)
10.5.2.4 Inbound Classification Type11 Memory Map
Table 10-5. RMan Inbound Type11 Memory Map
10.5.3 Global Memory Map
Table 10-6. RMan Global Memory Map (continued)
10.6 RapidIO Message Manager Registers
10.6.1 RapidIO Message Manager Global Registers
10.6.1.1 Message Manager Mode Register (MMMR)
Figure 10-2. Message Manager Mode Register (MMMR)
Table 10-7. MMMR Field Descriptions
10.6.1.2 Message Manager Status Register (MMSR)
Figure 10-3. Message Manager Status Register (MMSR)
Table 10-8. MMSR Field Descriptions
10.6.1.3 Message Manager T8 Frame Queue Assembly Register (MMT8FQAR)
Figure 10-4. Message Manager T8 Frame Queue Assembly Register (MMT8FQAR)
Table 10-9. MMT8FQAR Field Descriptions (continued)
10.6.1.4 Message Manager T9 Frame Queue Assembly Register (MMT9FQAR)
Figure 10-5. Message Manager T9 Frame Queue Assembly Register (MMT9FQAR)
Table 10-10. MMT9FQAR Field Descriptions (continued)
10.6.1.5 Message Manager T10 Frame Queue Assembly Register (MMT10FQAR)
Figure 10-6. Message Manager T10 Frame Queue Assembly Register (MMT10FQAR)
Table 10-11. MMT10FQAR Field Descriptions
10.6.1.6 Message Manager T11 Frame Queue Assembly Register (MMT11FQAR)
Figure 10-7. Message Manager T11 Frame Queue Assembly Register (MMT11FQAR)
Table 10-12. MMT11FQAR Field Descriptions (continued)
10.6.1.7 Message Manager Interrupt Enable Registers (MMIER)
Figure 10-8. Message Manager Interrupt Enable Register (MMIER)
Table 10-13. MMIER Field Descriptions (continued)
10.6.1.8 Message Manager Error Detect Registers (MMEDR)
Figure 10-9. Message Manager Error Detect Register (MMEDR)
Table 10-14. MMEDR Field Descriptions (continued)
10.6.1.9 Message Manager Interrupt Coalescing Register (MMICR)
Figure 10-10. Message Manager Interrupt Coalescing Register (MMICR)
Table 10-15. MMICR Field Descriptions
10.6.1.10 Message Manager T8 Drop Counter Register (MMT8DCR)
Figure 10-11. Message Manager T8 Drop Counter Register (MMT8DCR)
Table 10-16. MMT8DCR Field Descriptions
10.6.1.11 Message Manager T9 Drop Counter Register (MMT9DCR)
Figure 10-12. Message Manager T9 Drop Counter Register (MMT9DCR)
Table 10-17. MMT9DCR Field Descriptions
10.6.1.12 Message Manager Error Capture FQ Register (MMECFQR)
Figure 10-13. Message Manager Error Capture FQ Register (MMECFQR)
Table 10-18. MMECFQR Field Descriptions
10.6.1.13 Message Manager Error Capture FD Register 0 (MMECFDR0)
Figure 10-14. Message Manager Error Capture FD Register 0 (MMECFDR0)
Table 10-19. MMECFDR0 Field Descriptions
10.6.1.14 Message Manager Error Capture FD Register 1 (MMECFDR1)
Figure 10-15. Message Manager Error Capture FD Register 1 (MMECFDR1)
Table 10-20. MMECFDR1 Field Descriptions
10.6.1.15 Message Manager Error Capture FD Register 2 (MMECFDR2)
Figure 10-16. Message Manager Error Capture FD Register 2 (MMECFDR2)
Table 10-21. MMECFDR2 Field Descriptions
10.6.1.16 Message Manager Error Capture FD Register 3 (MMECFDR3)
Figure 10-17. Message Manager Error Capture FD Register 3 (MMECFDR3)
Table 10-22. MMECFDR3 Field Descriptions
10.6.1.17 Message Manager Error Capture Address Registers (MMECARn)
Figure 10-18. Message Manager Error Capture Address Register 0 (MMECAR0)
Table 10-23. MMECAR0 Field Descriptions
Figure 10-19. Message Manager Error Capture Address Register 1 (MMECAR1)
Table 10-24. MMECAR1 Field Descriptions
10.6.1.18 Message Manager Arbitration Weight Register (MMAWR)
Figure 10-20. Message Manager Arbitration Weight Register (MMAWR)
Table 10-25. MMAWR Field Descriptions
10.6.1.19 Message Manager Outbound Interleaving Mask Register (MMOIMR)
Figure 10-21. Message Manager Outbound Interleaving Mask Register (MMOIMR)
Table 10-26. MMOIMR Field Descriptions (continued)
10.6.1.20 Message Manager Logical I/O Device Number Base Register (MMLIODNBR)
Figure 10-22. Message Manager Logical I/O Device Number Base Register (MMLIODNBR)
Table 10-27. MMLIODNBR Field Descriptions
10.6.1.21 Message Manager Inbound Translation Address Register (MMITAR)
Figure 10-23. Message Manager Inbound Translation Address Register (MMITAR)
Table 10-28. MMITAR Field Descriptions
10.6.1.22 Message Manager Inbound Translation Data Register (MMITDR)
Figure 10-24. Message Manager Inbound Translation Data Register (MMITDR)
Table 10-29. MMITDR Field Descriptions
10.6.1.23 Message Manager Segmentation Execution Privilege Register (MMSEPR0)
Table 10-30. Default SU Execution Privileges Based on AG
Figure 10-25. Message Manager Segmentation Execution Privilege Register (MMSEPR0)
Table 10-31. MMSEPR0 Field Descriptions
10.6.1.24 Message Manager Reassembly Context Assignment Registers (MMRCARn)
Figure 10-26. Message Manager Reassembly Context Assignment Register 0 (MMRCAR0)
Table 10-32. MMRCAR0 Field Descriptions (continued)
Figure 10-27. Message Manager Reassembly Context Assignment Register 1 (MMRCAR1)
Table 10-33. MMRCAR1 Field Descriptions
Figure 10-28. Message Manager Reassembly Context Assignment Register 2 (MMRCAR2)
Table 10-34. MMRCAR2 Field Descriptions
10.6.1.25 IP Block Revision Register 0 (IPBRR0)
Figure 10-29. IP Block Revision Register 0 (IPBRR0)
Table 10-35. IPBRR0 Field Descriptions
10.6.1.26 IP Block Revision Register 1 (IPBRR1)
Figure 10-30. IP Block Revision Register 1 (IPBRR1)
Table 10-36. IIPBRR1 Field Descriptions
10.6.2 RapidIO Inbound Type8 Classification Registers
10.6.2.1 Inbound Block m Type8 Classification n Mode Registers (IBmT8CnMR)
Figure 10-31. Inbound Block m Type8 Classification n Mode Registers (IBmT8CnMR)
Table 10-37. IBmT8CnMR Field Descriptions
10.6.2.2 Inbound Block m Type8 Classification n Frame Queue Registers (IBmT8CnFQR)
Figure 10-32. Inbound Block m Type8 Classification n Frame Queue Registers (IBmT8CnFQR)
Table 10-38. IBmT8CnFQR Field Descriptions
10.6.2.3 Inbound Block m Type8 Classification n Rule Value Registers (IBmT8CnRVRn)
Figure 10-33. Inbound Block m Type8 Classification n Rule Value Register 0 (IBmT8CnRVR0)
Table 10-39. IBmT8CnRVR0 Field Descriptions
Figure 10-34. Inbound Block m Type8 Classification n Rule Value Register 1 (IBmT8CnRVR1)
Table 10-40. IBmT8CnRVR1 Field Descriptions
10.6.2.4 Inbound Block m Type8 Classification n Rule Mask Registers (IBmT8CnRMRn)
Figure 10-35. Inbound Block m Type8 Classification n Rule Mask Register 0 (IBmT8CnRMR0)
Table 10-41. IBmT8CnRMR0 Field Descriptions
Figure 10-36. Inbound Block m Type8 Classification n Rule Mask Register 1 (IBmT8CnRMR1)
Table 10-42. IBmT8nRMR1 Field Descriptions
10.6.2.5 Inbound Block m Type8 Classification n Data Buffer Pool Registers (IBmT8CnDBPR)
Figure 10-37. Inbound Block m Type8 Classification n Data Buffer Pool Registers (IBmT8CnDBPR)
Table 10-43. IBmT8CnDBPR Field Descriptions
10.6.2.6 Inbound Block m Type8 Classification n Data Offset Registers (IBmT8CnDOR)
Figure 10-38. Inbound Block m Type8 Classification n Data Offset Registers (IBmT8CnDOR)
Table 10-44. IBmT8CnDOR Field Descriptions
10.6.3 RapidIO Inbound Type9 Classification Registers
10.6.3.1 Inbound Block m Type9 Classification n Mode Registers (IBmT9CnMR)
Figure 10-39. Inbound Block m Type9 Classification n Mode Registers (IBmT9CnMR)
Table 10-45. IBmT9CnMR Field Description (continued)
10.6.3.2 Inbound Block m Type9 Classification n Frame Queue Registers (IBmT9CnFQR)
Figure 10-40. Inbound Block m Type9 Classification n Frame Queue Register (IBmT9CnFQR)
Table 10-46. IBmT9CnFQR Field Descriptions
10.6.3.3 Inbound Block m Type9 Classification n Rule Value Registers (IBmT9CnRVRn)
Figure 10-41. Inbound Block m Type9 Classification n Rule Value Register 0 (IBmT9CnRVR0)
Table 10-47. IBmT9CnRVR0 Field Descriptions
Figure 10-42. Inbound Block m Type9 Classification n Rule Value Register 1 (IBmT9CnRVR1)
Table 10-48. IBmT9CnRVR1 Field Descriptions
10.6.3.4 Inbound Block m Type9 Classification n Rule Mask Registers (IBmT9CnRMRn)
Figure 10-43. Inbound Block m Type9 Classification n Rule Mask Register 0 (IBmT9CnRMR0)
Table 10-49. IBmT9CnRMR0 Field Descriptions
Figure 10-44. Inbound Block m Type9 Classification n Rule Mask Register 1 (IBmT9CnRMR1)
Table 10-50. IBmT9CnRMR1 Field Descriptions (continued)
10.6.3.5 Inbound Block m Type9 Classification n Flow Control Destination Register (IBmT9CnFCDR)
Figure 10-45. Inbound Block m Type9 Classification n Flow Control Destination Register (IBmT9CnFCDR)
Table 10-51. IBmT9CnFCDR Field Descriptions
10.6.3.6 Inbound Block m Type9 Classification n Data Buffer Pool Registers (IBmT9CnDBPR)
Figure 10-46. Inbound Block m Type9 Classification n Data Buffer Pool Registers (IBmT9CnDBPR)
Table 10-52. IBmT9CnDBPR Field Descriptions
10.6.3.7 Inbound Block m Type9 Classification n Data Offset Registers (IBmT9CnDOR)
Figure 10-47. Inbound Block m Type9 Classification n Data Offset Register (IBmT9CnDOR)
Table 10-53. IBmT9CnDOR Field Descriptions
10.6.3.8 Inbound Block m Type9 Classification n Scatter/Gather Buffer Pool Registers (IBmT9CnSGBPR)
Figure 10-48. Inbound Block m Type9 Classification n Scatter/Gather Buffer Pool Register (IBmT9CnSGBPR)
Table 10-54. IBmT9CnSGBPR Field Descriptions
10.6.4 RapidIO Inbound Type10 Classification Registers
10.6.4.1 Inbound Block m Type10 Classification n Mode Register (IBmT10CnMR)
Figure 10-49. Inbound Block m Type8 Classification n Mode Registers (IBmT8CnMR)
Table 10-55. IBmT10CnMR Field Descriptions
10.6.4.2 Inbound Block m Type10 Classification n Frame Queue Register
Figure 10-50. Inbound Block m Type10 Classification n Frame Queue Register (IBmT10CnFQR)
Table 10-56. IBmT10CnFQR Field Descriptions
10.6.4.3 Inbound Block m Type10 Classification n Rule Value Registers (IBmT10CnRVRn)
Figure 10-51. Inbound Block m Type10 Classification n Rule Value Register 0 (IBmT10CnRVR0)
Table 10-57. IBmT10CnRVR0 Field Descriptions
Figure 10-52. Inbound Block m Type10 Classification n Rule Value Register 1 (IBmT10CnRVR1)
Table 10-58. IBmT10CnRVR1 Field Descriptions
10.6.4.4 Inbound Block m Type10 Classification n Rule Mask Registers (IBmT10CnRMRn)
Figure 10-53. Inbound Block m Type10 Classification n Rule Mask Register 0 (IBmT10CnRMR0)
Table 10-59. IBmT10CnRMR0 Field Descriptions (continued)
Figure 10-54. Inbound Block m Type10 Classification n Rule Mask Register 1 (IBmT10CnRMR1)
Table 10-60. IBmT10nRMR1 Field Descriptions
10.6.4.5 Inbound Block m Type10 Classification n Data Buffer Pool Registers (IBmT10CnDBPR)
Figure 10-55. Inbound Block m Type10 Classification n Data Buffer Pool Registers (IBmT10CnDBPR)
Table 10-61. IBmT10CnDBPR Field Descriptions
10.6.4.6 Inbound Block m Type10 Classification n Data Offset Registers (IBmT10CnDOR)
Figure 10-56. Inbound Block m Type10 Classification n Data Offset Registers (IBmT10CnDOR)
Table 10-62. IBmT10CnDOR Field Descriptions
10.6.5 RapidIO Inbound Type11 Classification Registers
10.6.5.1 Inbound Block m Type11 Classification n Mode Registers (IBmT11CnMR)
Figure 10-57. Inbound Block m Type8 Classification n Mode Registers (IBmT8CnMR)
Table 10-63. IBmT11CnMR Field Descriptions
10.6.5.2 Inbound Block m Type11 Classification n Frame Queue Register (IBmT11CnFQR)
Figure 10-58. Inbound Block m Type11 Classification n Frame Queue Register (IBmT11CnFQR)
Table 10-64. IBmT11CnFQR Field Descriptions
10.6.5.3 Inbound Block m Type11 Classification n Rule Value Registers (IBmT11CnRVRn)
Figure 10-59. Inbound Block m Type11 Classification n Rule Value Register 0 (IBmT11CnRVR0)
Table 10-65. IBmT11CnRVR0 Field Descriptions
Figure 10-60. Inbound Block m Type11 Classification n Rule Value Register 1 (IBmT11CnRVR1)
Table 10-66. IBmT11CnRVR1 Field Descriptions
10.6.5.4 Inbound Block m Type11 Classification n Rule Mask Registers (IBmT11CnRMRn)
Figure 10-61. Inbound Block m Type11 Classification n Rule Mask Register 0 (IBmT11CnRMR0)
Table 10-67. IBmT11CnRMR0 Field Descriptions
Figure 10-62. Inbound Block m Type11 Classification n Rule Mask Register 1 (IBmT11CnRMR1)
Table 10-68. IBmT11CnRMR1 Field Descriptions (continued)
10.6.5.5 Inbound Block m Type11 Classification Manager n Data Buffer Pool Registers (IBmT11CnDBPR)
Figure 10-63. Inbound Block m Type11 Classification Manager n Data Buffer Pool Registers (IBmT11CnDBPR)
Table 10-69. IBmT11CnDBPR Field Descriptions
10.6.5.6 Inbound Block m Type11 Classification Manager n Data Offset Registers (IBmT11CnDOR)
Figure 10-64. Inbound Block m Type11 Classification n Data Offset Registers (IBmT11CnDOR)
Table 10-70. IBmT11CnDOR Field Descriptions
10.7 Frame Descriptor Format
10.7.1 Inbound Frame Descriptor Format
Figure 10-65. Inbound Frame Descriptor Format
Table 10-71. Inbound Frame Descriptor Field Descriptions (continued)
10.7.2 Outbound Frame Descriptor Format
Figure 10-66. Outbound Frame Descriptor Format
Table 10-72. Outbound Frame Descriptor Field Descriptions (continued)
10.7.3 Status Frame Descriptor
10.7.3.1 Outbound Completion Queues
10.7.4 Frame Annotations
Figure 10-67. Alternate Message Descriptor Location Supports Frame Annotations
10.8 Scatter/Gather Tables
Figure 10-68. Scatter/Gather Table Entry Format
Table 10-73. Scatter/Gather Table Entry Field Descriptions
Figure 10-69. Type9 Scatter/Gather Table Chaining
10.9 Type5 NWrite Manager Functional Description
10.9.1 Type5 Outbound NWrite Descriptor Format
Figure 10-70. Type5 Outbound NWrite Descriptor
Table 10-74. Type5 Outbound NWrite Descriptor Field Descriptions (continued)
Figure 10-71. Outbound Type5 Scatter/Gather Table Format
10.9.2 Type5 Outbound NWrite Operation
10.9.2.1 Work Scheduling
10.9.2.1.1 Adding NWrites to a Frame Queue
10.9.2.2 Error Handling
Table 10-75. Outbound Segmentation Hardware Errors
10.9.2.2.1 Descriptor Error
10.9.2.2.2 Transaction Errors
10.10 Type6 Streaming Write Functional Description
10.10.1 Type6 Outbound SWrite Descriptor Format
Figure 10-72. Type6 Outbound SWrite Descriptor
Table 10-76. Type6 Outbound SWrite Descriptor Field Descriptions (continued)
Figure 10-73. Outbound Type6 Scatter/Gather Table Format
10.10.2 Type6 Outbound SWrite Operation
10.10.2.1 Work Scheduling
10.10.2.1.1 Adding NWrites To A Frame Queue
10.10.2.2 Error Handling
Table 10-77. Outbound Segmentation Hardware Errors (continued)
10.10.2.2.1 Descriptor Error
10.10.2.2.2 Transaction Errors
10.11 Type8 Port-Write Functional Description
10.11.1 Type8 Outbound Port-Write Descriptor Format
Figure 10-74. Type8 Outbound Port-Write Descriptor
Table 10-78. Type8 Outbound Port-Write Descriptor Field Descriptions (continued)
Figure 10-75. Frame Descriptor Referencing Outbound Type8 Port-Write Descriptor
10.11.2 Type8 Inbound Port-Write Descriptor Format
Figure 10-76. Frame Descriptor Referencing Inbound Type8 Port-Write Data Payload
10.11.3 Type8 Outbound Port-Write Operation
10.11.3.1 Work Scheduling
10.11.3.1.1 Adding Port-Writes To A Frame Queue
10.11.3.2 Error Handling
Table 10-79. Outbound Port-Write Hardware Errors
10.11.3.2.1 Descriptor Error
10.11.3.2.2 Transaction Errors
10.11.4 Type8 Inbound Port-Write Operation
10.11.4.1 Error Handling
Table 10-80. Inbound Port-Write Hardware Errors
10.11.4.1.1 Buffer Size Errors
10.11.4.1.2 Transaction Errors
10.12 Type9 Data Streaming Functional Description
10.12.1 Type9 Segmentation Descriptor Format
Figure 10-77. Type9 Outbound PDU Descriptor
Table 10-81. Type9 Outbound PDU Descriptor Field Descriptions (continued)
Figure 10-78. Outbound Type9 Scatter/Gather Table Format
10.12.2 Type9 Reassembly Descriptor Format
Figure 10-79. Type9 Inbound PDU Descriptor
Table 10-82. Type9 Inbound PDU Descriptor Field Descriptions (continued)
Figure 10-80. Inbound Type9 Scatter/Gather Table Format
10.12.3 Type9 Outbound Segmentation Operation
10.12.3.1 Work Scheduling
10.12.3.1.1 Adding PDUs To A Frame Queue
10.12.3.2 Error Handling
Table 10-83. Outbound Segmentation Hardware Errors (continued)
10.12.3.2.1 Descriptor Error
10.12.3.2.2 Transaction Errors
10.12.4 Type9 Reassembly Operation
10.12.4.1 Packet Steering
10.12.4.2 Packet Drop Condition
10.12.4.3 Error Handling
Table 10-84. Inbound Reassembly Hardware Errors (continued)
10.12.4.3.1 Single/Start Segment Error
10.12.4.3.2 Continuation Segment Error
10.12.4.3.3 End Segment Error
10.12.4.3.4 Segment Request Time-out Errors
10.12.4.3.5 MTU Violation Errors
10.12.4.3.6 Source Errors
10.12.4.3.7 Size Mismatch Errors
10.12.4.3.8 Transaction Errors
10.12.5 Flow Control Management
10.12.5.1 Receiving Flow Control Messages
10.12.5.2 Sending Flow Control Messages
Figure 10-81. Example of Outbound Type9 Flow Control Generation
10.13 Type10 Doorbell Functional Description
10.13.1 Type10 Outbound Doorbell Descriptor Format
Figure 10-82. Type10 Outbound Doorbell Descriptor
Table 10-85. Type10 Outbound Doorbell Descriptor Field Descriptions (continued)
Figure 10-83. FD Using Single Buffer Referencing Type10 Outbound Message
10.13.2 Type10 Inbound Doorbell Descriptor Format
Figure 10-84. Type10 Inbound Doorbell Descriptor
Table 10-86. Type10 Inbound Doorbell Descriptor Field Descriptions (continued)
Figure 10-85. Frame Descriptor Referencing a Type10 Inbound Doorbell
10.13.3 Type10 Outbound Doorbell Operation
10.13.3.1 Work Scheduling
10.13.3.1.1 Adding Doorbells To A Frame Queue
10.13.3.2 Error Handling
Table 10-87. Outbound Doorbell Hardware Errors
10.13.3.2.1 Descriptor Error
10.13.3.2.2 Doorbell Error Response Errors
10.13.3.2.3 Doorbell Response Time-out Errors
10.13.3.2.4 Retry Threshold Exceeded Errors
10.13.3.2.5 Transaction Errors
10.13.4 Type10 Inbound Doorbell Operation
10.13.4.1 Doorbell Steering
10.13.4.2 Retry Response Condition
10.13.4.3 Error Response Condition
10.13.4.4 Error Handling
Table 10-88. Inbound Doorbell Hardware Errors
10.13.4.4.1 Buffer Size Errors
10.13.4.4.2 Transaction Errors
10.14 Type11 Message Functional Description
10.14.1 Type11 Outbound Message Descriptor Format
Figure 10-86. Type11 Outbound Message Descriptor
Table 10-89. Type11 Outbound Message Descriptor Field Descriptions (continued)
Figure 10-87. Frame Descriptor Using Single Buffer Referencing Type11 Outbound Message
10.14.2 Type11 Inbound Message Descriptor Format
Figure 10-88. Type11 Inbound Message Descriptor
Table 10-90. Type11 Inbound Message Descriptor Field Descriptions (continued)
Figure 10-89. Frame Descriptor Referencing a Type11 Inbound Message
10.14.3 Type11 Outbound Message Operation
10.14.3.1 Work Scheduling
10.14.3.1.1 Adding Messages to a Frame Queue
10.14.3.2 Error Handling
Table 10-91. Outbound Message Hardware Errors (continued)
10.14.3.2.1 Descriptor Error
10.14.3.2.2 Message Error Response Errors
10.14.3.2.3 Segment Response Time-Out Errors
10.14.3.2.4 Retry Threshold Exceeded Errors
10.14.3.2.5 Multicast Errors
10.14.3.2.6 Transaction Errors
10.14.4 Type11 Inbound Message Operation
10.14.4.1 Message Steering
10.14.4.2 Retry Response Condition
10.14.4.3 Error Response Condition
10.14.4.4 Error Handling
Table 10-92. Inbound Message Hardware Errors (continued)
10.14.4.4.1 Segment Request Time-Out Errors
10.14.4.4.2 Buffer Size Errors
10.14.4.4.3 Message Format Errors
10.14.4.4.4 Transaction Errors
10.15 Functional Description Caveats
10.15.1 Buffer Prefetching
10.16 Session Management
10.16.1 Classification
Figure 10-90. Inbound Traffic Classification
10.17 Hardware Context Management
10.17.1 Segmentation and Reassembly
Figure 10-91. Per-Flow Context Counters
Table 10-93.
10.17.2 Examples
10.18 Address Alignment Requirements
10.19 Ordering Rules
10.19.1 Inbound Ordering Rules
10.19.2 Outbound Ordering Rules
10.19.2.1 Outbound Segmentation Interleaving
10.19.3 Transaction Priorities
Table 10-94. Memory Read/Write Priorities
10.20 Congestion Management
10.21 Interrupts
Figure 10-92. Interrupt Structure
10.22 Initialization Information
10.22.1 Initializing the Global Registers
10.22.1.1 Algorithmic Frame Queue ID Generation
Figure 10-93. Algorithmic Frame Queue ID Generation
10.22.2 Classification Initialization
10.22.2.1 Dynamically Changing Rules
10.22.2.2 Mixing Classification Rule Types
Appendix A Revision History
A.1 Changes From Revision 1 to Revision 2
A.2 Changes From Revision 0 to Revision 1
QorIQ Data Path Acceleration
Architecture (DPAA)
Reference Manual
Supports
P1023
P2040/P2041
P3041
P4080/P4040
P5020/P5010
DPAARM
Rev. 2
11/2011
Note: The DPAARM Rev. 3 will support the P5040; however, until it is available please refer to the P5020 in the DPAARM Rev. 2 and consult the P5040RM for actual ports available on the device package.
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Document Number: DPAARM
Rev. 2, 11/2011
Paragraph
Number
Contents
Title
Contents
Page
Number
Terminology, Conventions, and Resources
Terms, Acronyms, and Abbreviations ................................................................................ci
Notational Conventions ....................................................................................................civ
Suggested Reading.............................................................................................................cv
Data Path Acceleration Architecture (DPAA) Overview
Chapter 1
General DPAA Functionality ........................................................................................... 1-1
Packet Distribution and Queue/Congestion Management ........................................... 1-2
Content Processing Acceleration ................................................................................. 1-2
DPAA Programming Model............................................................................................. 1-3
DPAA Terms and Definitions .......................................................................................... 1-4
Major DPAA Components............................................................................................... 1-5
Queue Manager (QMan).............................................................................................. 1-5
Buffer Manager (BMan) .............................................................................................. 1-6
Frame Manager (FMan)............................................................................................... 1-6
FMan Network Interfaces........................................................................................ 1-6
FMan Parse Function............................................................................................... 1-7
FMan Distribution and Policing .............................................................................. 1-8
FMan Policer ....................................................................................................... 1-8
Security Engine (SEC 4.x)........................................................................................... 1-9
Pattern Matching Engine (PME) 2.0.......................................................................... 1-10
PME Regular Expressions (Regex) ....................................................................... 1-10
PME Match Detection ........................................................................................... 1-10
Data Formats Used in the DPAA ................................................................................... 1-11
Frame Descriptor (FD)............................................................................................... 1-11
FD Format.............................................................................................................. 1-11
Frame Descriptor (FD) Considerations ................................................................. 1-12
Multi-Buffer Frames .................................................................................................. 1-13
Scatter/Gather Entry Format.................................................................................. 1-13
Multi-Buffer Frame Considerations....................................................................... 1-14
Situations Where Multi-Buffer-Frame Processing Stops ...................................... 1-15
Single-Buffer Frames................................................................................................. 1-15
Compound Frames..................................................................................................... 1-15
When to Use Compound Frames........................................................................... 1-15
Compound Frame Considerations ......................................................................... 1-16
Simple Frames ........................................................................................................... 1-17
Frame Format Codes.................................................................................................. 1-17
1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.3.1
1.4.3.2
1.4.3.3
1.4.3.3.1
1.4.4
1.4.5
1.4.5.1
1.4.5.2
1.5
1.5.1
1.5.1.1
1.5.1.2
1.5.2
1.5.2.1
1.5.2.2
1.5.2.3
1.5.3
1.5.4
1.5.4.1
1.5.4.2
1.5.5
1.5.6
QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 2
Freescale Semiconductor
iii
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1.5.7
1.5.8
1.5.9
1.6
1.6.1
1.6.2
1.6.2.1
1.6.2.2
1.7
1.8
Contents
Title
Page
Number
Frame Formats Supported by Accelerators ............................................................... 1-18
Special Values and Exceptions .................................................................................. 1-18
Releasing Buffers to the BMan.................................................................................. 1-18
Accessing Memory Using Logical IO Device Numbers (LIODNs).............................. 1-19
Role of the PAMU in the DPAA................................................................................ 1-19
Using Multiple LIODNs ............................................................................................ 1-19
Benefit of Using Multiple LIODNs....................................................................... 1-19
LIODN Requirements............................................................................................ 1-19
Packet Walk-Through Example ..................................................................................... 1-20
Differences between DPAA Modules per SoC .............................................................. 1-21
Chapter 2
Memory Map
2.1
2.1.1
2.1.2
Memory Map Overview................................................................................................... 2-1
Considerations When Accessing Reserved Registers and Bits ................................... 2-1
DPAA Address Map .................................................................................................... 2-1
Datapath Three Speed Ethernet Controller (dTSEC)
Chapter 3
dTSEC Overview ............................................................................................................. 3-1
dTSEC Features Summary............................................................................................... 3-2
dTSEC Modes of Operation ............................................................................................ 3-3
Full- and Half-Duplex Operation................................................................................. 3-3
10- and 100-Mbps RMII Interface Operation.............................................................. 3-3
MAC Address Recognition Options............................................................................ 3-4
dTSEC External Signals Description............................................................................... 3-4
dTSEC Detailed Signal Descriptions........................................................................... 3-5
dTSEC Memory Map/Register Definition....................................................................... 3-9
dTSEC Top-Level Module Memory Map ................................................................. 3-10
dTSEC Detailed Memory Map .................................................................................. 3-10
dTSEC Memory-Mapped Register Descriptions....................................................... 3-16
General Control and Status Registers .................................................................... 3-16
Controller ID Register (dTSEC_ID).................................................................. 3-16
Controller ID Register 2 (TSEC_ID2)............................................................... 3-17
Interrupt Event Register (IEVENT) .................................................................. 3-17
Interrupt Mask Register (IMASK) .................................................................... 3-20
Ethernet Control Register (ECNTRL)............................................................... 3-21
Pause Time Value Register (PTV) ..................................................................... 3-24
TBI Physical Address Register (TBIPA) ........................................................... 3-24
QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 2
Freescale Semiconductor
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.5
3.5.1
3.5.2
3.5.3
3.5.3.1
3.5.3.1.1
3.5.3.1.2
3.5.3.1.3
3.5.3.1.4
3.5.3.1.5
3.5.3.1.6
3.5.3.1.7
iv
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3.5.3.2.1
3.5.3.2.2
3.5.3.3
3.5.3.3.1
3.5.3.3.2
3.5.3.4
3.5.3.4.1
3.5.3.4.2
3.5.3.4.3
3.5.3.4.4
3.5.3.4.5
3.5.3.4.6
3.5.3.4.7
3.5.3.4.8
3.5.3.4.9
3.5.3.4.10
3.5.3.4.11
3.5.3.4.12
3.5.3.4.13
3.5.3.4.14
3.5.3.4.15
3.5.3.5
3.5.3.5.1
3.5.3.5.2
3.5.3.5.3
3.5.3.5.4
3.5.3.5.5
3.5.3.5.6
3.5.3.5.7
3.5.3.5.8
3.5.3.5.9
3.5.3.5.10
3.5.3.5.11
3.5.3.5.12
Contents
Title
Page
Number
Timer Control Register (TMR_CTRL) ............................................................. 3-25
Timer PTP Packet Event Register (TMR_PEVENT)........................................ 3-26
Timer Event Mask Register (TMR_PEMASK) ................................................ 3-27
Transmit/Receive and Interface Control and Status Registers .............................. 3-27
Transmit Control Register (TCTRL) ................................................................. 3-27
Receive Control Register (RCTRL) .................................................................. 3-29
Hash Function Registers........................................................................................ 3-30
Individual/Group Address Registers 0–7 (IGADDRn) ..................................... 3-31
Group Address Registers 0–7 (GADDRn) ........................................................ 3-31
MAC Registers ...................................................................................................... 3-31
MAC Configuration 1 Register (MACCFG1)................................................... 3-32
MAC Configuration 2 Register (MACCFG2)................................................... 3-33
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ..................................... 3-35
Half-Duplex Register (HAFDUP) ..................................................................... 3-35
Maximum Frame Length Register (MAXFRM) ............................................... 3-36
MII Management Configuration Register (MIIMCFG) .................................... 3-37
MII Management Command Register (MIIMCOM)......................................... 3-38
MII Management Address Register (MIIMADD)............................................. 3-39
MII Management Control Register (MIIMCON).............................................. 3-39
MII Management Status Register (MIIMSTAT) ............................................... 3-39
MII Management Indicator Register (MIIMIND)............................................. 3-40
Interface Status Register (IFSTAT).................................................................... 3-40
MAC Station Addresses .................................................................................... 3-41
MAC Exact Match Address 1–15 Part 1 Registers
(MAC01ADDR1–MAC15ADDR1).............................................................. 3-42
MAC Exact Match Address 1–15 Part 2 Registers
(MAC01ADDR2–MAC15ADDR2).............................................................. 3-43
MIB Registers: Transmit and Receive Counters ................................................... 3-44
Transmit and Receive 64-Byte Frame Counter (TR64) .................................... 3-44
Transmit and Receive 65- to 127-Byte Frame Counter (TR127) ...................... 3-45
Transmit and Receive 128- to 255-Byte Frame Counter (TR255) .................... 3-45
Transmit and Receive 256- to 511-Byte Frame Counter (TR511) .................... 3-45
Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K) ................... 3-46
Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)............. 3-46
Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter
(TRMGV) ...................................................................................................... 3-47
Receive Byte Counter (RBYT).......................................................................... 3-47
Receive Packet Counter (RPKT)....................................................................... 3-47
Receive FCS Error Counter (RFCS) ................................................................. 3-48
Receive Multicast Packet Counter (RMCA) ..................................................... 3-48
Receive Broadcast Packet Counter (RBCA) ..................................................... 3-49
QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 2
Freescale Semiconductor
v
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3.5.3.5.19
3.5.3.5.20
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3.5.3.5.22
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3.5.3.5.29
3.5.3.5.30
3.5.3.5.31
3.5.3.5.32
3.5.3.5.33
3.5.3.5.34
3.5.3.5.35
3.5.3.5.36
3.5.3.5.37
3.5.3.5.38
3.5.3.5.39
3.5.3.5.40
3.5.3.5.41
3.5.3.5.42
3.5.3.5.43
3.5.3.5.44
3.5.3.5.45
3.5.3.5.46
3.5.3.5.47
3.5.4
3.5.4.1
3.5.4.1.1
3.5.4.1.2
3.5.4.1.3
3.5.4.2
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Title
Page
Number
Receive Control Frame Packet Counter (RXCF) .............................................. 3-49
Receive Pause Frame Packet Counter (RXPF).................................................. 3-49
Receive Unknown Opcode Packet Counter (RXUO)........................................ 3-50
Receive Alignment Error Counter (RALN) ...................................................... 3-50
Receive Frame Length Error Counter (RFLR).................................................. 3-51
Receive Code Error Counter (RCDE) ............................................................... 3-51
Receive Carrier Sense Error Counter (RCSE)................................................... 3-51
Receive Undersize Packet Counter (RUND)..................................................... 3-52
Receive Oversize Packet Counter (ROVR)....................................................... 3-52
Receive Fragments Counter (RFRG) ................................................................ 3-53
Receive Jabber Counter (RJBR)........................................................................ 3-53
Receive Dropped Packet Counter (RDRP)........................................................ 3-53
Transmit Byte Counter (TBYT) ........................................................................ 3-54
Transmit Packet Counter (TPKT)...................................................................... 3-54
Transmit Multicast Packet Counter (TMCA) .................................................... 3-55
Transmit Broadcast Packet Counter (TBCA) .................................................... 3-55
Transmit Pause Control Frame Counter (TXPF)............................................... 3-55
Transmit Deferral Packet Counter (TDFR) ....................................................... 3-56
Transmit Excessive Deferral Packet Counter (TEDF) ...................................... 3-56
Transmit Single Collision Packet Counter (TSCL) ........................................... 3-57
Transmit Multiple Collision Packet Counter (TMCL) ...................................... 3-57
Transmit Late Collision Packet Counter (TLCL).............................................. 3-57
Transmit Excessive Collision Packet Counter (TXCL)..................................... 3-58
Transmit Total Collision Counter (TNCL) ........................................................ 3-58
Transmit Drop Frame Counter (TDRP)............................................................. 3-59
Transmit Jabber Frame Counter (TJBR) ........................................................... 3-59
Transmit FCS Error Counter (TFCS) ................................................................ 3-59
Transmit Control Frame Counter (TXCF)......................................................... 3-60
Transmit Oversize Frame Counter (TOVR) ...................................................... 3-60
Transmit Undersize Frame Counter (TUND).................................................... 3-60
Transmit Fragment Counter (TFRG)................................................................. 3-61
Carry Register One (CAR1) .............................................................................. 3-61
Carry Register Two (CAR2).............................................................................. 3-62
Carry Mask Register One (CAM1) ................................................................... 3-63
Carry Mask Register Two (CAM2) ................................................................... 3-65
Ten-Bit Interface (TBI).............................................................................................. 3-66
TBI Transmit Process ............................................................................................ 3-66
Packet Encapsulation......................................................................................... 3-66
8B10B Encoding................................................................................................ 3-66
Preamble Shortening.......................................................................................... 3-66
TBI Receive Process.............................................................................................. 3-67
QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 2
Freescale Semiconductor
Paragraph
Number
3.5.4.2.1
3.5.4.2.2
3.5.4.3
3.5.4.3.1
3.5.4.3.2
3.5.4.3.3
3.5.4.3.4
3.5.4.3.5
3.5.4.3.6
3.5.4.3.7
3.5.4.3.8
3.5.4.3.9
3.5.4.3.10
3.6
3.6.1
3.6.1.1
3.6.1.2
3.6.1.3
3.6.1.4
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
3.6.2.4
3.6.2.5
3.6.3
3.6.3.1
3.6.3.1.1
3.6.3.1.2
3.6.3.2
3.6.3.3
3.6.3.4
3.6.3.5
3.6.3.5.1
3.6.3.5.2
3.6.3.6
3.6.3.7
3.6.3.7.1
3.6.3.7.2
3.6.3.8
3.6.3.9
Contents
Title
Page
Number
Synchronization ................................................................................................. 3-67
Auto-Negotiation for 1000BASE-X.................................................................. 3-67
TBI MII Set Register Descriptions........................................................................ 3-67
Control Register (CR)........................................................................................ 3-68
Status Register (SR)........................................................................................... 3-69
AN Advertisement Register (ANA) .................................................................. 3-70
AN Link Partner Base Page Ability Register (ANLPBPA)............................... 3-72
AN Expansion Register (ANEX) ...................................................................... 3-73
AN Next Page Transmit Register (ANNPT)...................................................... 3-74
AN Link Partner Ability Next Page Register (ANLPANP) .............................. 3-74
Extended Status Register (EXST) ..................................................................... 3-75
Jitter Diagnostics Register (JD)......................................................................... 3-76
TBI Control Register (TBICON)....................................................................... 3-77
dTSEC Functional Description...................................................................................... 3-78
Connecting the dTSEC to Physical Interfaces on Ethernet ....................................... 3-78
Reduced Media-Independent Interface (RMII) ..................................................... 3-79
Reduced Gigabit Media-Independent Interface (RGMII) ..................................... 3-79
Serial Gigabit Media-Independent Interface (SGMII) .......................................... 3-81
Ethernet Physical Interfaces Signal Summary....................................................... 3-82
MAC Functionality.................................................................................................... 3-85
Configuring the MAC............................................................................................ 3-85
Controlling CSMA/CD.......................................................................................... 3-86
Handling Packet Collisions.................................................................................... 3-86
Controlling Packet Flow ........................................................................................ 3-86
Controlling PHY Links.......................................................................................... 3-87
Gigabit Ethernet Controller Channel Operation ........................................................ 3-88
Initialization Sequence........................................................................................... 3-88
Hardware Controlled Initialization.................................................................... 3-88
User Initialization .............................................................................................. 3-88
Soft Reset and Reconfiguring Procedure............................................................... 3-89
Gigabit Ethernet Frame Transmission ................................................................... 3-89
Gigabit Ethernet Frame Reception ........................................................................ 3-90
Ethernet Preamble Customization ......................................................................... 3-91
User-Defined Preamble Transmission ............................................................... 3-91
User-Visible Preamble Reception...................................................................... 3-92
RMON Support...................................................................................................... 3-93
Frame Recognition................................................................................................. 3-93
Destination Address Recognition and Frame Filtering ..................................... 3-94
Hash Table Algorithm........................................................................................ 3-95
Magic Packet Mode ............................................................................................... 3-97
Flow Control.......................................................................................................... 3-97
QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 2
Freescale Semiconductor
vii
Paragraph
Number
3.6.3.10
3.6.3.11
3.6.3.12
3.6.3.13
3.7
3.7.1
3.7.1.1
3.7.1.2
3.7.1.3
3.7.2
3.7.2.1
3.7.2.2
3.7.2.2.1
3.7.2.3
3.7.2.4
3.7.2.5
4.1
4.2
4.3
4.3.1
4.4
4.4.1
4.4.2
4.4.3
4.4.3.1
4.4.3.1.1
4.4.3.1.2
4.4.3.1.3
4.4.3.1.4
4.4.3.1.5
4.4.3.1.6
4.4.3.1.7
4.4.3.1.8
4.4.3.1.9
4.4.3.1.10
4.4.3.1.11
4.4.3.1.12
viii
Contents
Title
Page
Number
Interrupt Handling ................................................................................................. 3-98
Inter-Frame Gap Time ......................................................................................... 3-100
Internal and External Loop Back......................................................................... 3-101
Error-Handling Procedure.................................................................................... 3-101
dTSEC Initialization/Application Information ............................................................ 3-102
Interface Mode Configuration ................................................................................. 3-102
RGMII Interface Mode ....................................................................................... 3-103
RMII Interface Mode........................................................................................... 3-108
SGMII Interface Support ..................................................................................... 3-112
Hardware Assist for IEEE Std 1588-Compliant Time-Stamping ............................ 3-115
IEEE 1588 dTSEC Time-Stamping Features Summary...................................... 3-115
Time-Stamp Inline Insertion on Receive Packets................................................ 3-116
Required Time-Stamp Point ............................................................................ 3-116
Time-Stamps For Transmit Packets..................................................................... 3-116
Time-Stamp Latency............................................................................................ 3-116
Timer Soft Reset Procedure ................................................................................. 3-117
10-Gigabit Ethernet Media Access Controller (10GEC)
Chapter 4
10GEC Overview............................................................................................................. 4-1
10GEC Features Summary .............................................................................................. 4-2
10GEC External Signals Descriptions............................................................................. 4-2
10GEC Detailed Signal Descriptions .......................................................................... 4-3
10GEC Memory Map/Register Definition ...................................................................... 4-4
10GEC Top-Level Memory Map................................................................................. 4-4
10GEC Detailed Memory Map.................................................................................... 4-5
10GEC Memory-Mapped Register Descriptions......................................................... 4-8
10GEC General Control and Status Registers ......................................................... 4-8
10-gigabit Ethernet MAC Controller ID (EC10G_ID)........................................ 4-8
Command and Configuration Register (COMMAND_CONFIG) ...................... 4-9
First MAC Lower Address Register (MAC_ADDR_0).................................... 4-10
First MAC Upper Address Register (MAC_ADDR_1) .................................... 4-11
Maximum Frame Length Register (MAXFRM) ............................................... 4-11
Pause Quanta Register (PAUSE_QUANT) ....................................................... 4-12
Hashtable Control Register (HASHTABLE_CTRL) ........................................ 4-12
MAC Status Register (STATUS) ....................................................................... 4-13
Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) ................... 4-14
Second MAC Lower Address Register (MAC_ADDR_2) ............................... 4-14
Second MAC Upper Address Register (MAC_ADDR_3)................................ 4-15
Interrupt Mask Register (IMASK) .................................................................... 4-15
QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 2
Freescale Semiconductor
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