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zynq 7000详细手册.pdf
Zynq-7000 All Programmable SoC
Table of Contents
Ch. 1: Introduction
Overview
Block Diagram
Documentation Resources
Notices
Processing System (PS) Features and Descriptions
Application Processor Unit (APU)
Memory Interfaces
I/O Peripherals
Programmable Logic Features and Descriptions
Interconnect Features and Description
PS Interconnect Based on AXI High Performance Datapath Switches
PS-PL Interfaces
System Software
Ch. 2: Signals, Interfaces, and Pins
Introduction
Notices
Power Pins
PS I/O Pins
PS–PL Voltage Level Shifter Enables
PS-PL MIO-EMIO Signals and Interfaces
I/O Peripheral (IOP) Interface Routing
IOP Interface Connections
MIO Pin Assignment Considerations
MIO-at-a-Glance Table
MIO Signal Routing
Default Logic Levels
MIO Pin Electrical Parameters
PS–PL AXI Interfaces
PS–PL Miscellaneous Signals
Clocks and Resets
Interrupt Signals
Event Signals
Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals
DMA Req/Ack Signals
PL I/O Pins
Ch. 3: Application Processing Unit
Introduction
Basic Functionality
System-Level View
Cortex-A9 Processors
Summary
Central Processing Unit (CPU)
Level 1 Caches
Memory Ordering
Memory Management Unit (MMU)
Interfaces
NEON
Performance Monitoring Unit
Snoop Control Unit (SCU)
Summary
Address Filtering
SCU Master Ports
L2-Cache
Summary
Exclusive L2-L1 Cache Configuration
Cache Replacement Strategy
Cache Lockdown
Enabling and Disabling the L2 Cache Controller
RAM Access Latency Control
Store Buffer Operation
Optimizations Between Cortex-A9 and L2 Controller
Pre-fetching Operation
Programming Model
APU Interfaces
PL Co-processing Interfaces
Interrupt Interface
Support for TrustZone
Application Processing Unit (APU) Reset
Reset Functionality
APU State After Reset
Power Considerations
Introduction
Standby Mode
Dynamic Clock Gating in the L2 Controller
CPU Initialization Sequence
Implementation-Defined Configurations
Ch. 4: System Addresses
Address Map
System Bus Masters
SLCR Registers
CPU Private Bus Registers
SMC Memory
PS I/O Peripherals
Miscellaneous PS Registers
Ch. 5: Interconnect
Introduction
Features
Block Diagram
Datapaths
Clock Domains
Connectivity
AXI ID
Read/Write Request Capability
Register Overview
Quality of Service (QoS)
Basic Arbitration
Advanced QoS
DDR Port Arbitration
AXI_HP Interfaces
Features
Block Diagram
Functional Description
Performance
Register Overview
Bandwidth Management Features
Transaction Types
Command Interleaving and Re-Ordering
Performance Optimization Summary
AXI_ACP Interface
AXI_GP Interfaces
Features
Performance
PS-PL AXI Interface Signals
AXI Signals
AXI Clocks and Resets
Loopback
Exclusive AXI Accesses
CPU/L2
ACP
DDRC
System Summary
Ch. 6: Boot and Configuration
Introduction
PS Hardware Boot Stages
PS Software Boot Stages
Boot Device Content
Boot Modes
BootROM Execution
FSBL / User Code Execution
PL Boot Process
PL Configuration Paths
Device Configuration Interface
Starting Code on CPU 1
Development Environment
Device Start-up
Introduction
Power Requirements
Clocks and PLLs
Reset Operations
Boot Mode Pin Settings
I/O Pin Connections for Boot Devices
BootROM Code
BootROM Flowchart
BootROM Header
BootROM Performance
Quad-SPI Boot
NAND Boot
NOR Boot
SD Card Boot
JTAG Boot
Reset, Boot, and Lockdown States
BootROM Header Search
MultiBoot
BootROM Error Codes
Post BootROM State
Registers Modified by the BootROM – Examples
Device Boot and PL Configuration
PL Control via PS Software
Boot Sequence Examples
PCAP Bridge to PL
PCAP Datapath Configurations
PL Control via User-JTAG
Reference Section
PL Configuration Considerations
Boot Time Reference
Register Overview
PS Version and Device Revision
Ch. 7: Interrupts
Environment
Private, Shared and Software Interrupts
Generic Interrupt Controller (GIC)
Resets and Clocks
Block Diagram
CPU Interrupt Signal Pass-through
Functional Description
Software Generated Interrupts (SGI)
CPU Private Peripheral Interrupts (PPI)
Shared Peripheral Interrupts (SPI)
Interrupt Sensitivity, Targeting and Handling
Wait for Interrupt Event Signal (WFI)
Register Overview
Write Protection Lock
Programming Model
Interrupt Prioritization
Interrupt Handling
ARM Programming Topics
Legacy Interrupts and Security Extensions
Ch. 8: Timers
Introduction
System Diagram
Notices
CPU Private Timers and Watchdog Timers
Clocking
Interrupt to PS Interrupt Controller
Resets
Register Overview
Global Timer (GT)
Clocking
Register Overview
System Watchdog Timer (SWDT)
Features
Block Diagram
Functional Description
Register Overview
Programming Model
Clock Input Option for SWDT
Reset Output Option for SWDT
Triple Timer Counters (TTC)
Features
Block Diagram
Functional Description
Register Overview
Programming Model
Clock Input Option for Counter/Timer
I/O Signals
Ch. 9: DMA Controller
Introduction
Features
System Viewpoint
Block Diagram
Notices
Functional Description
DMA Transfers on the AXI Interconnect
AXI Transaction Considerations
DMA Manager
Multi-channel Data FIFO (MFIFO)
Memory-to-Memory Transfers
PL Peripheral AXI Transactions
PL Peripheral Request Interface
PL Peripheral - Length Managed by PL Peripheral
PL Peripheral - Length Managed by DMAC
Events and Interrupts
Aborts
Security
IP Configuration Options
Programming Guide for DMA Controller
Startup
Execute a DMA Transfer
Interrupt Service Routine
Register Overview
Programming Guide for DMA Engine
Write Microcode to Program CCRx for AXI Transactions
Memory-to-Memory Transfers
PL Peripheral DMA Transfer Length Management
Restart Channel using an Event
Interrupting a Processor
Instruction Set Reference
Programming Restrictions
Updating Channel Control Registers During a DMA Cycle
System Functions
Clocks
Resets
Reset Configuration of Controller
I/O Interface
AXI Master Interface
Peripheral Request Interface
Ch. 10: DDR Memory Controller
Introduction
Features
Block Diagram
Notices
Interconnect
DDR Memory Types, Densities, and Data Widths
I/O Signals
AXI Memory Port Interface (DDRI)
Introduction
Block Diagram
AXI Feature Support and Limitations
TrustZone
DDR Core and Transaction Scheduler (DDRC)
Row/Bank/Column Address Mapping
DDRC Arbitration
Priority, Aging Counter and Urgent Signals
Page-Match
Aging Counter
Stage 1 – AXI Port Arbitration
Stage 2 – Read Versus Write
High Priority Read Ports
Stage 3 – Transaction State
Read Priority Management
Write Combine
Credit Mechanism
Controller PHY (DDRP)
Functional Programming Model
Clock Operating Frequencies
DDR IOB Impedance Calibration
DDR IOB Configuration
DDR Controller Register Programming
DRAM Reset and Initialization
DDR Initialization Sequence
DRAM Input Impedance (ODT) Calibration
DRAM Output Impedance (RON) Calibration
DRAM Training
Write Data Eye Adjustment
Alternatives to Automatic DRAM Training
DRAM Write Latency Restriction
Register Overview
DDRI
DDRC
DDRP
Error Correction Code (ECC)
ECC Initialization
ECC Error Behavior
Data Mask During ECC Mode
ECC Programming Model
Operational Programming Model
Operating Modes
Changing Clock Frequencies
Power Down
Deep Power Down
Self Refresh
DDR Power Reduction
Ch. 11: Static Memory Controller
Introduction
Features
Block Diagram
Notices
Functional Operation
Boot Device
Clocks
Resets
ECC Support
Interrupts
PL353 Functionality
Address Map
I/O Signals
Wiring Diagrams
Register Overview
Programming Model
NOR Flash Bandwidth
Ch. 12: Quad-SPI Flash Controller
Introduction
Features
System Viewpoint
Block Diagram
Notices
Functional Description
Operational Modes
I/O Mode
I/O Mode Transmit Registers (TXD)
I/O Mode Considerations
Linear Addressing Mode
Unsupported Devices
Supported Memory Read and Write Commands
Programming Guide
Configuration
Linear Addressing Mode
Configure I/O Mode
I/O Mode Interrupts
Rx/Tx FIFO Response to I/O Command Sequences
Register Overview
System Functions
Clocks
Resets
I/O Interface
Wiring Connections
MIO Programming
MIO Signals
Ch. 13: SD/SDIO Controller
Introduction
Key Features
System Viewpoint
Functional Description
AHB Interface and Interrupt Controller
SD/SDIO Host Controller
Data FIFO
Command and Control Logic
Bus Monitor
Stream Write and Read
Clocks
Soft Resets
FIFO Overrun and Underrun Conditions
Programming Model
Data Transfer Protocol Overview
Data Transfers Without DMA
Using DMA
Using ADMA
Abort Transaction
External Interface Usage Example
Supported Configurations
Bus Voltage Translation
SDIO Controller Media Interface Signals
SDIO EMIO Considerations
Ch. 14: General Purpose I/O (GPIO)
Introduction
Features
Block Diagram
Notices
Functional Description
GPIO Control of Device Pins
EMIO Signals
Bank0, Bits[8:7] are Outputs
Interrupt Function
Programming Guide
Start-up Sequence
GPIO Pin Configurations
Writing Data to GPIO Output Pins
Reading Data from GPIO Input Pins
GPIO as Wake-up Event
Register Overview
System Functions
Clocks
Resets
Interrupts
I/O Interface
MIO Programming
Ch. 15: USB Host, Device, and OTG Controller
Introduction
Features
Operating Modes
Hardware System Viewpoint
Controller Block Diagram
Configuration, Control and Status
Data Structures
Implementation Summary
Documentation
Notices
Chapter Overview
Functional Description
Controller Flow Diagram
DMA Engine
Protocol Engine
Port Controller
ULPI Link Wrapper
General Purpose Timers
Programming Overview and Reference
Hardware/Software System
Operational Mode Control
Power Management
Register Overview
Interrupt and Status Bits Overview
OTG Status/Interrupt and Control Register
Device Mode Control
Controller State
USB Bus Reset Response
Device Endpoint Data Structures
Link-list Endpoint Descriptors
Manage Endpoints
Endpoint Registers
Endpoint Initialization
Device Endpoint Packet Operational Model
Prime Transmit Endpoints
Prime Receive Endpoints
Interrupt and Bulk Endpoint Operational Model
Isochronous Endpoint Operational Model
Control Endpoint Operational Model
Device Endpoint Descriptor Reference
Endpoint Queue Head Descriptor (dQH)
Endpoint Transfer Descriptor (dTD)
Endpoint Transfer Overlay Area
Programming Guide for Device Controller
Software Model
USB Reset
Register Controlled Reset
Programming Guide for Device Endpoint Data Structures
Device Controller Initialization Overview
Manage Transfer Descriptors
Manage Transfers with Transfer Descriptors
Service Device Mode Interrupts
Host Mode Data Structures
Host Controller Transfer Schedule Structures
Periodic Schedule
Asynchronous Schedule
EHCI Implementation
Overview
Embedded Transaction Translator
EHCI Functional Changes for the TT
Port Reset Timer Enhancement
Port Speed Detection Mechanism
FS/LS Data Structures
Operational Model of the TT
Port Test Mode
Host Data Structures Reference
Descriptor Usage
Transfer Descriptor Type (TYP) Field
Isochronous (High Speed) Transfer Descriptor (iTD)
Split Transaction Isochronous Transfer Descriptor (siTD)
Queue Element Transfer Descriptor (qTD)
Queue Head (QH)
Transfer Overlay Area
Periodic Frame Span Traversal Node (FSTN)
Programming Guide for Host Controller
Controller Reset
Run/Stop
OTG Description and Reference
Hardware Assistance Features
OTG Interrupt and Control Bits
System Functions
Clocks
Reset Types
System Interrupt
APB Slave Interface
AHB Master Interface
I/O Interfaces
Wiring Connections
MIO-EMIO Programming
MIO-EMIO Signals
Ch. 16: Gigabit Ethernet Controller
Introduction
Block Diagram
Features
System Viewpoint
Clock Domains
Notices
Application Notes
Functional Description and Programming Model
MAC Transmitter
MAC Receiver
MAC Filtering
Wake-on-LAN Support
DMA Block
Checksum Offloading
IEEE 1588 Time Stamp Unit
MAC 802.3 Pause Frame Support
Programming Guide
Initialize the Controller
Configure the Controller
I/O Configuration
Configure the PHY
Configure the Buffer Descriptors
Configure Interrupts
Enable the Controller
Transmitting Frames
Receiving Frames
Debug Guide
IEEE 1588 Time Stamping
Overview
Controller Initialization
Best Master Clock Algorithm (BMCA)
PTP Packet Handling at the Master
PTP Packet Handling at the Slave
Register Overview
Control Registers
Status and Statistics Registers
Signals and I/O Connections
MIO–EMIO Interface Routing
Precision Time Protocol
Programmable Logic (PL) Implementations
RGMII Interface via MIO
GMII/MII Interface via EMIO
MDIO Interface Signals via MIO and EMIO
MIO Pin Considerations
Known Issues
Ch. 17: SPI Controller
Introduction
Features
System Viewpoint
Block Diagram
Notices
Functional Description
Master Mode
Multi-Master Capability
Slave Mode
FIFOs
FIFO Interrupts
Interrupt Register Bits, Logic Flow
SPI-to-SPI Connection
Programming Guide
Start-up Sequence
Controller Configuration
Master Mode Data Transfer
Slave Mode Data Transfer
Interrupt Service Routine
Register Overview
System Functions
Resets
Clocks
I/O Interfaces
Protocol
Back-to-Back Transfers
MIO/EMIO Routing
Wiring Connections
MIO/EMIO Signal Tables
Ch. 18: CAN Controller
Introduction
Features
System Viewpoint
Block Diagram
Notices
Functional Description
Controller Modes
Message Format
Message Buffering
Interrupts
Rx Message Filtering
Protocol Engine
CAN0-to-CAN1 Connection
Programming Guide
Overview
Configuration Mode State
Start-up Controller
Change Operating Mode
Write Messages to TxFIFO
Write Messages to TxHPB
Read Messages from RxFIFO
Register Overview
System Functions
Clocks
Resets
I/O Interface
MIO Programming
MIO-EMIO Signals
Ch. 19: UART Controller
Introduction
Features
System Viewpoint
Notices
Functional Description
Block Diagram
Control Logic
Baud Rate Generator
Transmit FIFO
Transmitter Data Stream
Receiver FIFO
Receiver Data Capture
I/O Mode Switch
UART0-to-UART1 Connection
Status and Interrupts
Modem Control
Programming Guide
Start-up Sequence
Configure Controller Functions
Transmit Data
Receive Data
RxFIFO Trigger Level Interrupt
Register Overview
System Functions
Clocks
Resets
I/O Interface
MIO Programming
MIO – EMIO Signals
Ch. 20: I2C Controller
Introduction
Features
System Block Diagram
Notices
Functional Description
Block Diagram
Master Mode
Slave Monitor Mode
Slave Mode
I2C Speed
Multi-Master Operation
I2C0-to-I2C1 Connection
Status and Interrupts
Programmer’s Guide
Start-up Sequence
Controller Configuration
Configure Interrupts
Data Transfers
Register Overview
System Functions
Clocks
Reset Controller
I/O Interface
Pin Programming
MIO-EMIO Interfaces
Ch. 21: Programmable Logic Description
Introduction
Features
PL Resources by Device Type
Notices
PL Components
CLBs, Slices, and LUTs
Clock Management
Block RAM
Digital Signal Processing — DSP Slice
Input/Output
PS-PL Interfaces
SelectIO
GTX Low-Power Serial Transceivers
GTP Low-Power Serial Transceivers
Integrated I/O Block for PCIe
Configuration
Ch. 22: Programmable Logic Design Guide
Introduction
Programmable Logic for Software Offload
Benefits of Using PL to Implement Software Algorithms
Designing PL Accelerators
PL Acceleration Limits
Power Offload
Real Time Offload
Reconfigurable Computing
PL and Memory System Performance Overview
Theoretical Bandwidth
DDR Efficiency
OCM Efficiency
Interconnect Throughput Bottlenecks
Choosing a Programmable Logic Interface
PL Interface Comparison Summary
Cortex-A9 CPU via General Purpose Masters
PS DMA Controller (DMAC) via General Purpose Masters
PL DMA via AXI High-Performance (HP) Interface
PL DMA via AXI ACP
PL DMA via General Purpose AXI Slave (GP)
Ch. 23: Programmable Logic Test and Debug
Introduction
Features
Block Diagram
System Viewpoint
Functional Description
Basic Operation
Packet Generation
Packet Format
Signals
General-Purpose Debug Signals
Trigger Signals
Trace Signals
Register Overview
Programming Model
FTM Security
Ch. 24: Power Management
Introduction
Features
System Design Considerations
Device Technology Choice
PL Power-down Control
APU Maximum Frequency
DDR Memory Clock Frequency
DDR Memory Controller Modes and Configurations
Boot Interface Options
PS Clock Gating
Programming Guides
System Modules
Peripherals
I/O Buffers
Sleep Mode
Setup Wake-up Events
Programming Guide
Register Overview
Ch. 25: Clocks
Introduction
System Block Diagram
Clock Generation
System Viewpoint
Power Management
CPU Clock
System-wide Clock Frequency Examples
Clock Generator Design
DDR Clocks
IOP Module Clocks
USB Clocks
Ethernet Clocks
SDIO, SMC, SPI, Quad-SPI and UART Clocks
CAN Clocks
GPIO and I2C Clocks
PL Clocks
Clock Throttle
Clock Throttle Programming
Trace Port Clock
Register Overview
Programming Model
Branch Clock Generator
DDR Clocks
Digitally Controlled Impedance (DCI) Clock
PLLs
Ch. 26: Reset System
Introduction
Features
Block Diagram
Reset Hierarchy
Boot Flow
Reset Sources
Power-on Reset (PS_POR_B)
External System Reset (PS_SRST_B)
System Software Reset
Watchdog Timer Resets
Secure Violation Lock Down
Debug Resets
Reset Effects
Peripherals
PL Resets
PL General Purpose User Resets
Register Overview
Persistent Registers
System Reset Control
Peripheral Reset Control
Ch. 27: JTAG and DAP Subsystem
Introduction
Block Diagram
Features
Functional Description
I/O Signals
Programming Model
Use Case I: Software Debug with Trace Port Enabled
Use Case II: PS and PL Debug with Trace Port Enabled
ARM DAP Controller
Trace Port Interface Unit (TPIU)
Xilinx TAP Controller
Ch. 28: System Test and Debug
Introduction
Features
Notices
Functional Description
Debug Access Port (DAP)
Embedded Cross Trigger (ECT)
Program Trace Macrocell (PTM)
Instrumentation Trace Macrocell (ITM)
Funnel
Embedded Trace Buffer (ETB)
Trace Packet Output (TPIU)
I/O Signals
Register Overview
Memory Map
Functionality
Programming Model
Authentication Requirements
Ch. 29: On-Chip Memory (OCM)
Introduction
Block Diagram
Features
System Viewpoint
Functional Description
Overview
Optimal Transfer Alignment
Clocking
Arbitration Scheme
Address Mapping
Interrupts
Register Overview
Programming Model
Changing Address Mapping
AXI Responses
Ch. 30: XADC Interface
Introduction
Features
System Viewpoint
PS-XADC Interface Block Diagram
Programming Guide
Functional Description
Interface Arbiter (PL-JTAG and PS-XADC)
Serial Communication Channel (PL-JTAG and PS-XADC)
Analog-to-Digital Converter (All)
Sensor Alarms (PS-XADC and DRP)
PS-XADC Interface Description
Serial Channel Clock Frequency
Command and Data Packets
Command Format
Read Data Format
Min/Max Voltage Thresholds
Critical Over-temperature Alarm
Programming Guide for the PS-XADC Interface
Read and Write to the FIFOs
Interrupts
Command Preparation
Register Overview
Programming Guide for the DRP Interface
Programming Guide for the PL-JTAG Interface
System Functions
Clocks
Resets
Ch. 31: PCI Express
Introduction
Block Diagram
Features
Endpoint Use Case
Root Complex Use Case
Ch. 32: Device Secure Boot
Introduction
Block Diagram
Features
Functional Description
Master Secure Boot
External Boot Devices
Secure Boot Image
eFUSE Settings
RSA Authentication
Boot Image and Bitstream Encryption
Boot Image and Bitstream Decryption and Authentication
HMAC Signature
AES Key Management
Secure Boot Features
Non-Secure Boot State
Secure Boot State
Security Lockdown
Boot Partition Search
JTAG and Debug Considerations
Readback
Secure Boot Modes of Operation
Programming Considerations
Appx. A: Additional Resources
Xilinx Resources
Solution Centers
References
Zynq-7000 AP SoC Documents
PL Documents – Device and Boards
Additional Zynq-7000 AP SoC Documents
Software Programming Documents
git Information
Design Tool Resources
Xilinx Problem Solvers
Third-Party IP and Standards Documents
Appx. B: Register Details
Overview
Acronyms
Module Summary
AXI_HP Interface (AFI) (axi_hp)
CAN Controller (can)
DDR Memory Controller (ddrc)
CoreSight Cross Trigger Interface (cti)
Performance Monitor Unit (cortexa9_pmu)
CoreSight Program Trace Macrocell (ptm)
Debug Access Port (dap)
CoreSight Embedded Trace Buffer (etb)
PL Fabric Trace Monitor (ftm)
CoreSight Trace Funnel (funnel)
CoreSight Intstrumentation Trace Macrocell (itm)
CoreSight Trace Packet Output (tpiu)
Device Configuration Interface (devcfg)
DMA Controller (dmac)
Gigabit Ethernet Controller (GEM)
General Purpose I/O (gpio)
Interconnect QoS (qos301)
NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
I2C Controller (IIC)
L2 Cache (L2Cpl310)
Application Processing Unit (mpcore)
On-Chip Memory (ocm)
Quad-SPI Flash Controller (qspi)
SD Controller (sdio)
System Level Control Registers (slcr)
Static Memory Controller (pl353)
SPI Controller (SPI)
System Watchdog Timer (swdt)
Triple Timer Counter (ttc)
UART Controller (UART)
USB Controller (usb)
Zynq-7000
All Programmable SoC
Technical Reference Manual
UG585 (v1.12.1) December 6, 2017
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The following table shows the revision history for this document. Change bars indicate the latest revisions.
Date
04/08/2012
06/25/2012
08/08/2012
Version
1.0
1.1
1.2
Revision
Xilinx initial release.
Removed Chapter 30, Board Design (now part of UG933, Zynq-7000 All Programmable
SoC PCB Design and Pin Planning Guide).
Added information about the 7z010 CLG225 device and references to section
2.5.4 MIO-at-a-Glance Table throughout document. Added section headings
1.1.1 Block Diagram and 1.1.2 Documentation Resources, added sections 1.1.3 Notices
and TrustZone Capabilities, and clarified PS MIO I/Os in Chapter 1. Updated Table 2-1.
Changed 2.4.2 MIO-EMIO Connections heading to 2.5.2 IOP Interface Connections and
clarified first paragraph. Updated Table 2-4. Added section 2.7.1 Clocks and Resets and
Table 2-7, and updated Table 2-13 PS MIO I/Os in Chapter 2. Added note under Branch
Prediction and Table 3-8 in Chapter 3. Updated Table 4-1 in Chapter 4. Added section
5.1.7 Read/Write Request Capability in Chapter 5. Updated NAND Boot MIO pin
assignments and Table 6-6 in Chapter 6. Updated section 7.1.5 CPU Interrupt Signal
Pass-through in Chapter 7. Added section heading 10.1.1 Features and added section
10.1.3 Notices in Chapter 10. Updated Parallel (SRAM/NOR) Interface features list and
added section 11.1.3 Notices in Chapter 11. Reorganized, clarified, and expanded
Chapter 12 to include programming models (added sections 12.1.4 Notices,
12.3 Programming Guide, and 12.5.2 MIO Programming). Added last note in section
13.3.4 Using ADMA in Chapter 13. Added Restrictions in Chapter 14. Clarified first
paragraph, added section 15.1.3 Notices, and clarified Figure 15-7 through
Figure 15-17 in Chapter 15. Added section 16.1.4 Notices in Chapter 16. Clarified
sections 17.2.5 SPI FIFOs, 17.2.6 SPI Clocks, and 17.2.7 SPI EMIO Considerations in
Chapter 17. Reorganized, clarified, and expanded Chapter 18 to include programming
models (added sections 18.1.4 Notices and 18.5.1 MIO Programming).
Zynq-7000 AP SoC Technical Reference Manual
UG585 (v1.12.1) December 6, 2017
www.xilinx.com
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Date
08/08/2012
Version
1.2
(Cont’d)
10/30/2012
1.3
11/16/2012
1.4
Revision
Reorganized, clarified, and expanded Chapter 19 to include programming models
(added sections 19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO
Programming). Updated Table 22-2 and Table 22-3 in Chapter 22. Added section CPU
Clock Divisor Restriction in Chapter 25. Updated Table 26-4 in Chapter 26. Clarified
section 27.3 I/O Signals in Chapter 27. Added section 28.1.2 Notices in Chapter 28.
Clarified Mapping Summary and updated Table 29-1, Table 29-3, and Table 29-5 in
Chapter 29. Added section 30.1.3 Notices in Chapter 30. Updated data sheet references
in section A.3.1 Zynq-7000 AP SoC Documents of Appendix A. Updated register
database in sections B.3 Module Summary through B.34 USB Controller (usb) in
Appendix B.
Changed product name from Extensible Processing Platform (EPP) to All Programmable
SoC (AP SoC) throughout document. Added Table 1-1. Added 2.1.1 Notices, 2.4 PS–PL
Voltage Level Shifter Enables, A summary of the dedicated PS signal pins is shown in
Table 2-2., VREF Source Considerations, updated Table 2-2, and added warning to
2.5.7 MIO Pin Electrical Parameters. Added Initialization of L1 Caches, 3.2.4 Memory
Ordering, expanded 3.2.5 Memory Management Unit (MMU), added Cache Lockdown
by Way Sequence and 3.9 CPU Initialization Sequence. Added 7z007s and 7z010 Device
Notice and expanded Table 4-7. Updated and expanded tables in 6.3.4 Quad-SPI Boot
through 6.3.13 Post BootROM State, reworked 6.3.6 Debug Status, and added
6.3.13 Post BootROM State and AXI and DMA Done Status Interrupts. Reworked
Table 7-4. Added 8.1.2 Notices, Interrupt to PS Interrupt Controller, and Reset.
Reorganized and expanded Chapter 9, DMA Controller. Added 10.1.3 Notices,
expanded 10.1.6 I/O Signals, added 10.6.12 DRAM Write Latency Restriction,
10.8.1 ECC Initialization, 10.8.4 ECC Programming Model, and 10.9.1 Operating Modes.
Added 12.2.4 I/O Mode Considerations and updated 12.3.5 Rx/Tx FIFO Response to I/O
Command Sequences. Reworked 16.3.3 I/O Configuration, added 16.4 IEEE 1588 Time
Stamping and 16.6.7 MIO Pin Considerations. Added 18.2.7 CAN0-to-CAN1
Connection. Expanded 19.1 Introduction, 19.1.3 Notices, and Table 19-1. Added
Receiver Timeout Mechanism, updated Figure 19-7. Added 19.2.9 UART0-to-UART1
Connection and 19.2.10 Status and Interrupts, expanded 19.2.11 Modem Control,
reworked 19.3 Programming Guide and 19.4.2 Resets. Added 20.2.7 I2C0-to-I2C1
Connection. Added 21.1.2 PL Resources by Device Type, Voltage Level Shifters and
reorganized content of Chapter 21, Programmable Logic Description. Added
25.7.1 Clock Throttle. Expanded 26.4.1 PL General Purpose User Resets. Updated
register database in sections B.3 Module Summary through B.34 USB Controller (usb)
in Appendix B.
Changed second bullet under NAND Flash Interface from “Up to a 4 GB device” to “Up
to a 1 GB device” in Chapter 11, Static Memory Controller.
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Date
03/07/2013
Version
1.5
06/28/2013
1.6
Revision
Added 7z100 device and made minor clarifications to Chapter 1, Introduction. Made
minor clarifications to Chapter 2, Signals, Interfaces, and Pins, Chapter 3, Application
Processing Unit, Chapter 4, System Addresses, and Chapter 5, Interconnect. Clarified
section 6.1 Introduction and other sections, and added PS Independent JTAG
Non-Secure Boot section in Chapter 6, Boot and Configuration. Made minor
clarifications to Chapter 7, Interrupts, Chapter 8, Timers, Chapter 9, DMA Controller,
Chapter 10, DDR Memory Controller, Chapter 11, Static Memory Controller, and
Chapter 12, Quad-SPI Flash Controller. Expanded 12.2 Functional Description in
Chapter 12, Quad-SPI Flash Controller. Made minor clarifications to Chapter 13,
SD/SDIO Controller. Made major clarifications/updates to Chapter 14, General Purpose
I/O (GPIO). Reworked and expanded Chapter 15, USB Host, Device, and OTG Controller.
Made minor clarifications to Chapter 16, Gigabit Ethernet Controller. Reworked and
expanded Chapter 17, SPI Controller. Made minor clarifications to Chapter 18, CAN
Controller, and Chapter 19, UART Controller. Made major clarifications/updates to
Chapter 20, I2C Controller (added new sections, 20.3 Programmer’s Guide, 20.4 System
Functions, and 20.5 I/O Interface). Made minor clarifications to Chapter 21,
Programmable Logic Description and added new sections 21.1.2 PL Resources by Device
Type and 21.1.3 Notices. Made minor clarifications to Chapter 22, Programmable Logic
Design Guide and Chapter 23, Programmable Logic Test and Debug. Reworked and
expanded Chapter 24, Power Management. Made minor clarifications to Chapter 25,
Clocks, Chapter 26, Reset System, Chapter 27, JTAG and DAP Subsystem, Chapter 28,
System Test and Debug, and Chapter 29, On-Chip Memory (OCM). Reworked and
expanded Chapter 30, XADC Interface. Made minor clarifications to Chapter 31, PCI
Express. Reworked and expanded Chapter 32, Device Secure Boot. Updated Appendix A,
Additional Resources. Updated register database in sections B.3 Module Summary
through B.34 USB Controller (usb) in Appendix B.
Added icons where applicable. Enhanced first sentence under Quad-SPI Controller in c.
Clarified first paragraph, added step 2, and clarified step 5 in section 2.4 PS–PL Voltage
Level Shifter Enables. Changed “drive strength” to “slew rate” in section 2.5.7 MIO Pin
Electrical Parameters. Added second sentence and updated Table 2-11 in section
2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals. Corrected Note 4 in Table 4-1
and Table 4-2. Made minor clarifications and added new RSA Authentication Time
section to Chapter 6, Boot and Configuration. Made minor clarifications to sections
7.2.2 CPU Private Peripheral Interrupts (PPI) and 7.2.3 Shared Peripheral Interrupts
(SPI), and updated Table 7-4 and Table 7-5. Clarified first row in Table 9-12. Added tip
to section 10.4.3 Aging Counter, added sentence to Write Leveling, and step 2 in section
10.9.2 Changing Clock Frequencies, and moved section 10.9.6 DDR Power Reduction
from Chapter 24, Power Management to this chapter. Added tip to section
11.2.2 Clocks. Added Table 12-8. Added MMC3.31 standard information to section
13.1 Introduction. Added step 6 to section 14.3.1 Start-up Sequence, added section
14.3.5 GPIO as Wake-up Event, added second paragraph to 14.4.1 Clocks. Added
section 16.7 Known Issues. Added note to 17.4.2 Clocks. Changed value of 107 Mb to
140 Mb in second sentence under section 21.4 Configuration. Added values for the
7z100 device in Table 21-2. Clarified first paragraph in section 24.2.2 PL Power-down
Control and updated Table 24-2. Added note to section 25.6.1 USB Clocks, clarified
second paragraph in section 25.10.4 PLLs, and added sentence to steps 2 and 3 in
Software-Controlled PLL Update section. Changed “RESET_REASON” to
“REBOOT_STATUS in section 26.2.3 System Software Reset, added section 26.5 Register
Overview, deleted first two rows from Table 26-2 and modified last paragraph in section
26.5.1 Persistent Registers. Clarified section 29.1 Introduction, added three paragraphs
to Starvation Scenarios section, and added 29.2.5 Address Mapping heading. Corrected
spelling of “MCTRL” to “MCTL” in sections 30.4 Programming Guide for the PS-XADC
Interface and 30.7.2 Resets.
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Date
06/28/2013
Version
1.6
(Cont’d)
02/11/2014
1.7
09/16/2014
1.8
09/19/2014
11/17/2014
11/19/2014
02/23/2015
1.8.1
1.9
1.9.1
1.10
09/27/2016
1.11
10/20/2017
12/06/2017
1.12
1.12.1
Revision
Added section 31.5 Root Complex Use Case. Added FIPS standards and clarified section
32.1.2 Features, updated configuration file and secure boot process steps in
Figure 32-1, added boot time penalty to Power on Reset section, changed “Secure Boot”
heading to ”Secure FSBL Decryption”, changed “ROM code” to “OCM ROM Memory” in
Figure 32-2 and “ROM” to “OCM ROM” in Table 32-3, updated sections 32.2.7 Boot
Image and Bitstream Decryption and Authentication, 32.2.8 HMAC Signature,
32.2.9 AES Key Management, 32.3.1 Non-Secure Boot State, 32.3.4 Boot Partition
Search, and 32.3.7 Secure Boot Modes of Operation (deleted Table 32-4, “Non-secure
Boot Options”). Updated register database in sections B.3 Module Summary through
B.34 USB Controller (usb) in Appendix B.
Added 7z015 device, updated device notices, and made minor clarifications throughout
document (denoted with change bars). Added section 3.10 Implementation-Defined
Configurations. Added sections 5.7 Loopback and 5.8 Exclusive AXI Accesses. Reworked
Chapter 6, Boot and Configuration. Added section 7.2.4 Interrupt Sensitivity, Targeting
and Handling. Added sections 8.4.6 Clock Input Option for SWDT and 8.5.6 Clock Input
Option for Counter/Timer. Updated section 10.7 Register Overview. Added section
11.7 NOR Flash Bandwidth. Added sections AXI Read Command Processing and
12.2.7 Supported Memory Read and Write Commands. Added section 16.1.4 Clock
Domains and reworked section 16.7 Known Issues (previously titled “Limitations”.
Updated section 21.1.2 PL Resources by Device Type and added section 21.3.4 GTP
Low-Power Serial Transceivers. Added Peripheral Clock Gating subsection. Updated
Table 26-1 and Table 26-4. Updated register database in sections B.3 Module Summary
through B.34 USB Controller (usb) in Appendix B.
Added position information for available device and package combinations for
the signals associated with each GT serial transceiver channel to sections
21.3.3 GTX Low-Power Serial Transceivers and 21.3.4 GTP Low-Power Serial
Transceivers.
Removed erroneous banner from Chapter 21, Programmable Logic Description.
Corrected send feedback button clarity issue in footers.
Added 7z035 device, updated device notices, and made minor clarifications throughout
document (denoted with change bars).
Corrected document date.
Added clarification on the timing relationship between PL power up and the PS
POR reset signal to section 2.2 Power Pins and section 6.3.3 BootROM
Performance: PS_POR_B De-assertion Guidelines.
Added 7z007s, 7z012s, and 7z014s single-core devices and updated the respective
device notices throughout document (denoted with change bars). Updated Figure 2-1,
Table 21-1, and Table 21-2. Updated device codes in Register PSS_IDCODE Details.
Made minor clarifications throughout document (denoted with change bars).
Removed internal review comment from 6-bit Programmable Divider section.
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Table of Contents
Chapter 1: Introduction
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.1.2 Documentation Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.1.3 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.2 Processing System (PS) Features and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2.1 Application Processor Unit (APU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.2.2 Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.2.3 I/O Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.3 Programmable Logic Features and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.4 Interconnect Features and Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.4.1 PS Interconnect Based on AXI High Performance Datapath Switches . . . . . . . . . . . . . . . . . . . . . . . . . .39
1.4.2 PS-PL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.5 System Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 2: Signals, Interfaces, and Pins
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.1.1 Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.2 Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.3 PS I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.4 PS–PL Voltage Level Shifter Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.5 PS-PL MIO-EMIO Signals and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.5.1 I/O Peripheral (IOP) Interface Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.5.2 IOP Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
2.5.3 MIO Pin Assignment Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
2.5.4 MIO-at-a-Glance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.5.5 MIO Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.5.6 Default Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.5.7 MIO Pin Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.6 PS–PL AXI Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.7 PS–PL Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.7.1 Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.7.2 Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.7.3 Event Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.7.5 DMA Req/Ack Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.8 PL I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Chapter 3: Application Processing Unit
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.1.1 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.1.2 System-Level View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.2 Cortex-A9 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.2.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.2.2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.2.3 Level 1 Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.2.4 Memory Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.2.5 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.2.6 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
3.2.7 NEON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
3.2.8 Performance Monitoring Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.3 Snoop Control Unit (SCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.3.2 Address Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.3.3 SCU Master Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4 L2-Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.4.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3.4.2 Exclusive L2-L1 Cache Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
3.4.3 Cache Replacement Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.4.4 Cache Lockdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.4.5 Enabling and Disabling the L2 Cache Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
3.4.6 RAM Access Latency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
3.4.7 Store Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
3.4.8 Optimizations Between Cortex-A9 and L2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
3.4.9 Pre-fetching Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.4.10 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.5 APU Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.5.1 PL Co-processing Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.5.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
3.6 Support for TrustZone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.7 Application Processing Unit (APU) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.7.1 Reset Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
3.7.2 APU State After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
3.8 Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3.8.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3.8.3 Dynamic Clock Gating in the L2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
3.9 CPU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.10 Implementation-Defined Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 4: System Addresses
4.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.2 System Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.3 SLCR Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.4 CPU Private Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.5 SMC Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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4.6 PS I/O Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.7 Miscellaneous PS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Chapter 5: Interconnect
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
5.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.1.3 Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.1.4 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.1.5 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.1.6 AXI ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.1.7 Read/Write Request Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.1.8 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.2 Quality of Service (QoS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.2.1 Basic Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.2.2 Advanced QoS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.2.3 DDR Port Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.3 AXI_HP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.3.4 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.3.5 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
5.3.6 Bandwidth Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
5.3.7 Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
5.3.8 Command Interleaving and Re-Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
5.3.9 Performance Optimization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
5.4 AXI_ACP Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.5 AXI_GP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.5.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.6 PS-PL AXI Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.6.1 AXI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.6.2 AXI Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
5.7 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.8 Exclusive AXI Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.8.1 CPU/L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
5.8.2 ACP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
5.8.3 DDRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
5.8.4 System Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Chapter 6: Boot and Configuration
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.1.1 PS Hardware Boot Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
6.1.2 PS Software Boot Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
6.1.3 Boot Device Content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
6.1.4 Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
6.1.5 BootROM Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
6.1.6 FSBL / User Code Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
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