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ictown.com_Power Compiler User Guide, version L-2016.03-SP4.pdf
Preface
Part 1: Power Compiler Concepts
Introduction to Power Compiler
Power Compiler Methodology
Power Library Models
Power Analysis Technology
Power Optimization Technology
Getting Started With Power Compiler
Library Requirements
Command-Line Interface
Graphical User Interface
License Requirements
Reading and Writing Designs
Power Compiler Design Flow
Power in the Design Cycle
Power Optimization and Analysis Flow
Simulation
Enable Power Optimization
Synthesis and Power Optimization
Power Analysis and Reporting
Power Modeling and Calculation
Power Types
Static Power
Dynamic Power
Switching Power
Internal Power
Calculating Power
Leakage Power Calculation
Multithreshold Voltage Libraries
Internal Power Calculation
NLDM Models
State and Path Dependency
Rise and Fall Power
Switching Power Calculation
Dynamic Power Calculation
Dynamic Power Unit Derivation
Power Calculation for Multirail Cells
Using CCS Power Libraries
Voltage Scaling
Script Examples for Voltage Scaling
Part 2: Power Analysis
Generating SAIF Files
About Switching Activity
Introduction to SAIF Files
Generating SAIF Files
Generating SAIF Files From Simulation
Generating SAIF Files From SystemVerilog or Verilog Simulations
Generating SAIF Files From VHDL Simulation
Generating SAIF Files From VCD Files
Converting a VCD File to a SAIF File
Generating SAIF Files from FSDB Output Files
Verilog Switching Activity Examples
RTL Example
Verilog Design Description
RTL Testbench
RTL SAIF File
Gate-Level Example
Gate-Level Verilog Module
Verilog Testbench
Gate-Level SAIF File
VHDL Switching Activity Example
VHDL Design Description
RTL Testbench
RTL SAIF File
Annotating Switching Activity
Types of Switching Activity to Annotate
Annotating Switching Activity Using RTL SAIF Files
Using the Name-Mapping Database
Integrating the RTL Annotation With PrimeTime PX
Annotating Switching Activity Using Gate-Level SAIF Files
Reading SAIF Files Using the read_saif Command
Reading SAIF Files Using the merge_saif Command
Annotating Inferred Switching Activity
Annotating Switching Activity Using the set_switching_activity Command
Fully Versus Partially Annotating the Design
Analyzing the Switching Activity Annotation
Removing the Switching Activity Annotation
Design Objects Without Annotated Switching Activity
Default Switching Activity Values
Propagating the Switching Activity
Deriving the State- and Path-Dependent Switching Activity
Performing Power Analysis
Overview
Identifying Power and Accuracy
Factors Affecting the Accuracy of Power Analysis
Switching Activity Annotation
Delay Model
Switching Activity Propagation and Accuracy
Overriding Library Power Characterization
Performing Gate-Level Power Analysis
Using the report_power Command
Using the report_power_calculation Command
Analyzing Power With Partially Annotated Designs
Power Correlation
Performing Power Correlation
Power Correlation Script
Analyzing the Design For Power Analysis
Characterizing a Design for Power
Reporting the Power Attributes of Library Cells
Power Reports
Power Report Summary
Net Power Report
Cell Power Report
Group Report
Hierarchical Power Reports
Power Report for Block Abstraction
Part 3: Power Reduction
Clock Gating
Introduction to Clock Gating
Using Clock-Gating Conditions
Clock-Gating Conditions
Enable Condition
Setup Condition
Enabling or Disabling Clock Gating on Design Objects
Inserting Clock Gates
Using the compile_ultra -gate_clock Command
Using the insert_clock_gating Command
Clock-Gate Insertion in Multivoltage Designs
Clock Gating Flows
Inserting Clock Gates in the RTL Design
Inserting Clock Gates in Gate-Level Design
Ensuring Accuracy When Using Ideal Clocks
Specifying Clock-Gate Latency
The set_clock_latency Command
The set_clock_gate_latency Command
Applying Clock-Gate Latency
Resetting Clock-Gate Latency
Comparison of the Clock-Gate Latency Specification Commands
Calculating the Clock Tree Delay From Clock-Gating Cell to Registers
Specifying Setup and Hold
Predicting the Impact of Clock Tree Synthesis
Choosing a Value for Setup
Choosing a Value for Hold
Clock-Gating Styles
Default Clock-Gating Style
Selecting Clock-Gating Style
Choosing Gating Logic
Choosing an Integrated Clock-Gating Cell
Choosing a Configuration for Discrete Gating Logic
Choosing a Simple Gating Cell by Name
Choosing a Simple Gating Cell and Library by Name
Designating Simple Cells Exclusively for Clock Gating
Choosing a Specific Latch and Library
Choosing a Latch-Free Style
Improving Testability
Connecting the Test Ports Throughout the Hierarchy
Using Instance-Specific Clock-Gating Style
Modifying the Clock-Gating Structure
Changing a Clock-Gated Register to Another Clock-Gating Cell
Removing Clock-Gating Cells From the Design
Rewiring Clock Gating After Retiming
Integrated Clock-Gating Cells
Integrated Clock-Gating Cell Attributes
Pin Attributes
Timing Considerations
Clock-Gating Naming Conventions
Example Script for Naming Style
Example Script of Output Netlist
Keeping Clock-Gating Information in a Structural Netlist
Identifying and Preserving Clock-Gating Cells
Identification of Clock-Gating Cells
Explicit Identification of Clock-Gating Cells
Preserving the Identified Clock-Gating Cells
Identified Clock-Gating Cells and dont_touch
Handling Clock-Gating Edge Conflicts
Comparison of Clock-Gate Identification Methods
Usage Flow With the write_script Command
Usage Flow With the identify_clock_gating Command
Replacing Clock-Gating Cells
Clock-Gate Optimization Performed During Compilation
Hierarchical Clock Gating
Enhanced Register-Based Clock Gating
Multistage Clock Gating
Multistage Clock-Gating Flow
Clock Gate Merging
Placement-Aware Clock Gating in Design Compiler Graphical
Clock Gating Multibit Registers
Performing Clock-Gating on DesignWare Components
Reporting Command for Clock Gates
The report_clock_gating Command
XOR Self-Gating
XOR Self-Gating Concepts
Using XOR Self-Gating in Power Compiler
XOR Self-Gating Flows
Library Requirements for XOR Self-Gating
Unsupported Registers for XOR Self-Gating
Sharing XOR Self-Gates
Inserting XOR Self-Gates
Specifying Objects for XOR Self-Gating
XOR Self-Gating the Clock-Gated Registers
Specifying Options for XOR Self-Gating
Querying the XOR Self-Gates
Reporting the XOR Self-Gates
Power Optimization
Overview
Input and Output of Power Optimization
Power Optimization in Synthesis Flow
General Gate-Level Power Optimization
Leakage Power Optimization
Dynamic Power Optimization
Enabling Power Optimization
Leakage Power Optimization Based on Threshold Voltage
Multiple Threshold Voltage Library Attributes
The set_multi_vth_constraint Command
Analyzing the Multiple Threshold Voltage Library Cells
Leakage Optimization for Multicorner-Multimode Designs
Performing Power Optimization
Settings for Power Optimization
Power Optimization in the Synopsys Physical Guidance Flow
Settings for Low-Power Placement
Multivoltage Design Concepts
Multivoltage and Multisupply Designs
Library Requirements for Multivoltage Designs
Liberty PG Pin Syntax
Level-Shifter Cells
PG Pin Configuration Support
Isolation Cells
Using Standard Cells as Isolation Cells
Single-Rail and Dual-Rail Isolation Cells
NOR-Style Isolation Cells
Requirements of Level-Shifter and Isolation Cells
Retention Register Cells
Multithreshold-CMOS Retention Registers
Power-Switch Cells
Always-On Logic Cells
Power Domains
Shut-Down Blocks
Marking Pass-Gate Library Pins
Voltage Areas
UPF Multivoltage Design Implementation
Multivoltage Design Flow Using UPF
Power Intent Concepts
UPF Script Example
Defining Power Intent in UPF
Name Spacing Rules for UPF Objects and Attributes
Defining the Power Intent in the GUI
UPF Diagram View
Creating Power Domains
Representation of Power Domain in the UPF Diagram View
Scope
Expanding and Collapsing Power Domains in the GUI
Viewing Hierarchical Cell and Power Domain Boundaries
Creating Supply Ports
Adding Port State Information to Supply Ports
Representation of Supply Ports in the UPF Diagram View
Creating Supply Nets
Specifying Primary Supply Nets for a Power Domain
Representing Supply Nets in the UPF Diagram View
Connecting Supply Nets
Converting the PG Information in RTL to UPF
Specifying Supply Sets
Creating Supply Sets
Creating Supply Set Handles
Restricting Supply Sets Available to a Power Domain
Refining Supply Sets
Associating Supply Sets With Supply Set Handles
Rules for Associating Supply Sets
Defining Power States for the Components of a Supply Set
Correlated Grouping of Supply Voltage Triplets
Always-On Logic
Marking Library Cells as Always-On
Marking Pass-Gate Library Pins
Always-On Optimization
Voltage-Aware Always-On Synthesis
Always-On Optimization on Top-Level Feedthrough Nets
Always-On Optimization on Disjoint Voltage Area
Always-On Tie Cells
Basic Always-On Tie Cell Mapping
Enhanced Constant Propagation
Enhanced Always-On Tie Cell Mapping
Specifying Level-Shifter Strategies
Using Specific Library Cells With the Level-Shifter Strategy
Allowing Insertion of Level-Shifters on Clock Nets and Ideal Nets
Representing Level-Shifter Strategies in the UPF Diagram View
Specifying Isolation Strategies
Using the set_isolation_control Command
Rules Applicable for Location Fanout
Order of Precedence of Isolation Strategies
Using Specific Library Cells With Isolation Strategies
Aligning Isolation Strategies to Constant Drivers
Isolation and Level-Shifter Cells Connected Back-to-Back
Representing Isolation Strategies in the UPF Diagram View
Setting UPF Attributes on Ports and Hierarchical Cells
Setting Attributes on Ports
Specifying Supplies for Repeaters
Setting Attributes on Hierarchical Cells
Extending the Power Domain Boundary
Setting Terminal Boundaries
Specifying Retention Strategies
Choosing Specific Library Cells With Retention Strategies
Retention Strategy and Clock-Gating Cells
Representing Retention Strategies in the UPF Diagram View
Creating Power Switches
Representation of Power Switches in the UPF Diagram View
Power State Tables
Creating Power State Tables
Defining the States of Supply Nets
Visually Analyzing Power State Tables in the UPF Diagram View
Support for Well Bias
Inserting Power Management Cells
Reviewing the UPF Specifications
Commands to Query and Edit Design Objects
Reviewing the Power Intent Using the Design Vision GUI
Applying the Power Intent Changes
Examining and Debugging UPF Specifications
The check_mv_design Command
MV Advisor GUI
Checking for Design Violations
Examining Design Violations in the MV Advisor Violation Browser
Exploring the Violations
The analyze_mv_design Command
Analyzing Multivoltage Design Connections in the GUI
Writing the Power Information
Preserving the Command Order in the UPF’ File
Controlling the Line Width in the UPF’ File
Writing and Reading Verilog Netlists With Power and Ground Information
Power and Ground Supply Connection Syntax
Supply Sets
Power Switches
Reading Verilog Netlists With Power and Ground Supply Connections
Golden UPF Flow
Reporting Commands for the UPF Flow
UPF-Based Hierarchical Multivoltage Flow Methodology
Steps in the Hierarchical UPF Design Methodology
Block-Level Implementation
Top-Level Implementation
Assembling Your Design
Characterization of Supply Sets and Supply Nets
Criteria for Characterization
Characterization of Supply Sets
Automatic Inference of Related Supply Net
Top-Level Design Integration
Power Domain Merging
Legacy Blocks
Library Setup for Power Optimization
Basic Library Requirements for Multivoltage Designs
Power and Ground Pin Syntax
Converting Libraries to PG Pin Library Format
Using FRAM View
Using Tcl Commands
Tcl Commands for Low-Power Library Specification
Macro Cells with Fine-Grained Switches
Library Usage in Multicorner-Multimode Designs
Link Libraries With Equal Nominal PVT Values
Setting the dont_use Attribute on Library Cells
Distinct PVT Requirements
Automatic Detection of Driving Cell Library
Relating the Minimum Library to the Maximum Library
Unique Identification of Libraries Based on File Names
Automatic Inference of Operating Conditions for Macro, Pad, and Switch Cells
Using the set_opcond_inference Command
Deviating from the Inferred Operating Condition and Its Impact
Power Optimization in Multicorner-Multimode Designs
Optimizing Multicorner-Multimode Designs
Optimizing for Leakage Power
Optimizing for Dynamic Power Using Low-Power Placement
Reporting Commands
report_scenarios Command
Reporting Examples for Multicorner-Multimode Designs
Script Example for Multicorner-Multimode Flow
Lower Domain Boundary Support
Introduction
Enabling the Lower Domain Boundary Feature
Changes to the Application of the Isolation and Level-Shifter Strategies
Specifying Design Instances Using Wildcard Characters
Specifying Design Instances Using SystemVerilog Elements
Filtering the Design Elements Using the -applies_to Option
Insertion of Back-to-Back Isolation and Level-Shifter Cells
Impact on Hierarchical Flow
Bottom-Up Flow
Top-Down Flow
Characterization of the Related Supply
Integrated Clock-Gating Cell Example
Library Description
Example Schematics
Rising-Edge Latch-Based Integrated Cells
Rising-Edge Latch-Free Integrated Cells
Falling Edge Latch-Based Integrated Cells
Falling-Edge Latch-Free Integrated Cells
Attributes for Querying and Filtering
Derived Attribute Lists
Usage Examples
Power Compiler Command and Variable Reference
Getting Help
Accessing Help
Man Page Viewing Instructions
Viewing Man Pages in SolvNet
Setting Up the UNIX Environment
Viewing Man Pages From UNIX
Viewing Man Pages From dc_shell
Power Compiler Commands
add_power_state
add_pst_state
all_clock_gates
all_isolation_cells
all_level_shifters
all_self_gates
all_upf_repeater_cells
analyze_library
analyze_dw_power
analyze_mv_design
apply_clock_gate_latency
associate_supply_set
characterize
check_level_shifters
check_mv_design
compile
compile_ultra
connect_logic_net
connect_supply_net
convert_pg
create_logic_net
create_logic_port
create_power_domain
create_power_state_group
create_power_switch
create_pst
create_supply_net
create_supply_port
create_supply_set
find_objects
get_power_domains
get_power_switches
get_related_supply_net
get_supply_nets
get_supply_ports
generate_mv_constraints
identify_clock_gating
infer_switching_activity
insert_clock_gating
insert_isolation_cell
insert_mv_cells
lib2saif
load_upf
map_isolation_cell
map_level_shifter_cell
map_power_switch
map_retention_cell
merge_saif
propagate_constraints
propagate_switching_activity
query_cell_instances
query_cell_mapped
query_map_power_switch
query_net_ports
query_port_net
query_port_state
query_power_switch
query_pst
query_pst_state
read_saif
remove_clock_gating
remove_clock_gating_style
remove_dft_clock_gating_pin
remove_isolation_cell
remove_level_shifters
remove_power_domain
remove_upf
replace_clock_gates
report_clock_gating
report_dft_clock_gating_configuration
report_dft_clock_gating_pin
report_isolation_cell
report_level_shifter
report_lib
report_mv_library_cells
report_power
report_power_calculation
report_power_domain
report_power_gating
report_power_pin_info
report_power_switch
report_pst
report_retention_cell
report_saif
report_self_gating
report_supply_net
report_supply_port
reset_clock_gate_latency
reset_dft_clock_gating_configuration
reset_switching_activity
rewire_clock_gating
saif_map
save_upf
set_cell_internal_power
set_clock_gate_latency
set_clock_gating_objects
set_clock_gating_registers
set_clock_gating_enable
set_clock_gating_style
set_cost_priority
set_design_attributes
set_dft_clock_gating_configuration
set_dft_clock_gating_pin
set_dft_power_control
set_domain_supply_net
set_dont_use
set_equivalent
set_isolation
set_isolation_cell
set_isolation_control
set_leakage_power_model
set_level_shifter
set_level_shifter_cell
set_multi_vth_constraint
set_port_attributes
set_power_clock_scaling
set_power_guide
set_power_prediction
set_power_switch_cell
set_query_rules
set_related_supply_net
set_replace_clock_gates
set_retention
set_retention_cell
set_retention_control
set_retention_control_pins
set_retention_elements
set_scenario_options
set_scope
set_self_gating_objects
set_self_gating_options
set_switching_activity
set_switching_activity_profile
set_upf_query_options
unset_power_guide
upf_version
write_saif
write_script
Power Compiler Variables
abstraction_enable_power_calculation
compile_power_domain_boundary_optimization
enable_golden_upf
enable_rule_based_query
golden_upf_report_missing_objects
hdlin_enable_upf_compatible_naming
link_allow_upf_design_mismatch
mv_allow_ls_on_leaf_pin_boundary
mv_allow_va_beyond_core_area
mv_input_enforce_simple_names
mv_insert_level_shifters_on_ideal_nets
mv_make_primary_supply_available_for_always_on
mv_no_always_on_buffer_for_redundant_isolation
mv_no_cells_at_default_va
mv_no_main_power_violations
mv_output_enforce_simple_names
mv_output_upf_line_indent
mv_output_upf_line_width
mv_skip_opcond_checking_for_unloaded_level_shifter
mv_upf_tracking
mv_use_std_cell_for_isolation
physopt_power_critical_range
power_cg_all_registers
power_cg_auto_identify
power_cg_balance_stages
power_cg_cell_naming_style
power_cg_derive_related_clock
power_cg_designware
power_cg_enable_alternative_algorithm
power_cg_ext_feedback_loop
power_cg_flatten
power_cg_gated_clock_net_naming_style
power_cg_ignore_setup_condition
power_cg_inherit_timing_exceptions
power_cg_iscgs_enable
power_cg_module_naming_style
power_cg_physically_aware_cg
power_cg_print_enable_conditions
power_cg_print_enable_conditions_max_terms
power_cg_reconfig_stages
power_cg_sequential_clock_gating
power_default_static_probability
power_default_toggle_rate
power_default_toggle_rate_type
power_do_not_size_icg_cells
power_enable_clock_scaling
power_enable_datapath_gating
power_enable_one_pass_power_gating
power_enable_power_gating
power_fix_sdpd_annotation
power_fix_sdpd_annotation_verbose
power_hdlc_do_not_split_cg_cells
power_keep_license_after_power_commands
power_lib2saif_rise_fall_pd
power_low_power_placement
power_min_internal_power_threshold
power_model_preference
power_opto_extra_high_dynamic_power_effort
power_preserve_rtl_hier_names
power_rclock_inputs_use_clocks_fanout
power_rclock_unrelated_use_fastest
power_rclock_use_asynch_inputs
power_remove_redundant_clock_gates
power_rtl_saif_file
power_sa_propagation_verbose
power_same_switching_activity_on_connected_objects
power_sdpd_message_tolerance
synlib_enable_analyze_dw_power
upf_allow_DD_primary_with_supply_sets
upf_allow_refer_before_define
upf_auto_iso_clamp_value
upf_auto_iso_enable_source
upf_auto_iso_isolation_sense
upf_block_partition
upf_charz_allow_port_punch
upf_charz_enable_supply_port_punching
upf_charz_max_srsn_messages
upf_create_implicit_supply_sets
upf_enable_legacy_block
upf_enable_relaxed_charz
upf_extension
upf_isols_allow_instances_in_elements
upf_iso_filter_elements_with_applies_to
upf_levshi_on_constraint_only
upf_name_map
upf_report_isolation_matching
upf_skip_ao_check_for_els_input
upf_suppress_etm_model_checking
upf_suppress_message_in_black_box
upf_suppress_message_in_etm
Power Compiler™
User Guide
Version L-2016.03-SP4, September 2016
Copyright Notice and Proprietary Information
©2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to
Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with
Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated
documentation is strictly prohibited.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective owners.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse
and is not responsible for such websites and their practices, including privacy practices, availability, and content.
Synopsys, Inc.
690 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com
Power Compiler™ User Guide, Version L-2016.03-SP4
ii
Copyright Notice for the Command-Line Editing Feature
© 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software
contributed to Berkeley by Christos Zoulas of Cornell University.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1.Redistributions of source code must retain the above copyright notice, this list of conditions and the following
disclaimer.
2.Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials provided with the distribution.
3.All advertising materials mentioning features or use of this software must display the following acknowledgement:
This product includes software developed by the University of California, Berkeley and its contributors.
4.Neither the name of the University nor the names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Copyright Notice for the Line-Editing Library
© 1992 Simmule Turner and Rich Salz. All rights reserved.
This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of the
University of California.
Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and
redistribute it freely, subject to the following restrictions:
1.The authors are not responsible for the consequences of use of this software, no matter how awful, even if they arise
from flaws in it.
2.The origin of this software must not be misrepresented, either by explicit claim or by omission. Since few users ever
read sources, credits must appear in the documentation.
3.Altered versions must be plainly marked as such, and must not be misrepresented as being the original software.
Since few users ever read sources, credits must appear in the documentation.
4.This notice may not be removed or altered.
Power Compiler™ User Guide, Version L-2016.03-SP4
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Power Compiler™ User Guide, Version L-2016.03-SP4
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Contents
About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxvi
xxviii
1.
Introduction to Power Compiler
Power Compiler Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Library Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Analysis Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Optimization Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Getting Started With Power Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command-Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
License Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading and Writing Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Power Compiler Design Flow
Power in the Design Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Optimization and Analysis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesis and Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Analysis and Reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-2
1-3
1-4
1-5
1-5
1-6
1-6
1-7
1-8
2-2
2-3
2-5
2-5
2-5
2-5
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Power Compiler™ User Guide
Power Compiler™ User Guide
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Version L-2016.03-SP4
3. Power Modeling and Calculation
Power Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculating Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Leakage Power Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multithreshold Voltage Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Power Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NLDM Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State and Path Dependency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rise and Fall Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Power Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Power Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Power Unit Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Calculation for Multirail Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using CCS Power Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Script Examples for Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. Generating SAIF Files
About Switching Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to SAIF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating SAIF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating SAIF Files From Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating SAIF Files From SystemVerilog or Verilog Simulations . . . . . .
Generating SAIF Files From VHDL Simulation. . . . . . . . . . . . . . . . . . . . . .
Generating SAIF Files From VCD Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Converting a VCD File to a SAIF File . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating SAIF Files from FSDB Output Files . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Switching Activity Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTL Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTL Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTL SAIF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
3-2
3-2
3-2
3-2
3-3
3-4
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-10
3-10
3-12
3-14
3-14
3-15
4-2
4-2
4-3
4-4
4-5
4-13
4-14
4-14
4-15
4-15
4-15
4-15
4-17
4-18
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Gate-Level Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-Level Verilog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verilog Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-Level SAIF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Switching Activity Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHDL Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTL Testbench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTL SAIF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. Annotating Switching Activity
Types of Switching Activity to Annotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Annotating Switching Activity Using RTL SAIF Files . . . . . . . . . . . . . . . . . . . . . . . .
Using the Name-Mapping Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrating the RTL Annotation With PrimeTime PX . . . . . . . . . . . . . . . . . . . . .
Annotating Switching Activity Using Gate-Level SAIF Files . . . . . . . . . . . . . . . . . . .
Reading SAIF Files Using the read_saif Command . . . . . . . . . . . . . . . . . . . . .
Reading SAIF Files Using the merge_saif Command . . . . . . . . . . . . . . . . . . . .
Annotating Inferred Switching Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Annotating Switching Activity Using the set_switching_activity Command. . . . . . . .
Fully Versus Partially Annotating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyzing the Switching Activity Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Removing the Switching Activity Annotation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Objects Without Annotated Switching Activity . . . . . . . . . . . . . . . . . . . . . . .
Default Switching Activity Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagating the Switching Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deriving the State- and Path-Dependent Switching Activity . . . . . . . . . . . . . . .
6. Performing Power Analysis
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identifying Power and Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Factors Affecting the Accuracy of Power Analysis . . . . . . . . . . . . . . . . . . . . . .
Switching Activity Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Activity Propagation and Accuracy. . . . . . . . . . . . . . . . . . . . . . .
Chapter 1: Contents
Contents
4-20
4-20
4-21
4-22
4-23
4-23
4-24
4-24
5-2
5-2
5-3
5-4
5-4
5-5
5-6
5-7
5-8
5-11
5-12
5-12
5-13
5-13
5-14
5-15
6-2
6-2
6-3
6-3
6-4
6-4
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Power Compiler™ User Guide
Power Compiler™ User Guide
L-2016.03-SP4
Version L-2016.03-SP4
Overriding Library Power Characterization. . . . . . . . . . . . . . . . . . . . . . . . .
Performing Gate-Level Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the report_power Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the report_power_calculation Command . . . . . . . . . . . . . . . . . . . . .
Analyzing Power With Partially Annotated Designs . . . . . . . . . . . . . . . . . . . . . . . . .
Power Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performing Power Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Correlation Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyzing the Design For Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characterizing a Design for Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting the Power Attributes of Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Report Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Net Power Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Power Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hierarchical Power Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Report for Block Abstraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7. Clock Gating
Introduction to Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Clock-Gating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock-Gating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling or Disabling Clock Gating on Design Objects. . . . . . . . . . . . . . . . . . .
Inserting Clock Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the compile_ultra -gate_clock Command . . . . . . . . . . . . . . . . . . . . . . . .
Using the insert_clock_gating Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock-Gate Insertion in Multivoltage Designs . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Gating Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inserting Clock Gates in the RTL Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inserting Clock Gates in Gate-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
6-5
6-5
6-6
6-9
6-9
6-10
6-11
6-11
6-12
6-13
6-15
6-15
6-17
6-18
6-19
6-20
6-21
6-23
7-3
7-5
7-5
7-6
7-8
7-9
7-10
7-10
7-10
7-11
7-11
7-11
7-12
viii
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