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VITA 
PO Box 19658, Fountain Hills, AZ 85269 
PH: 480-837-7486 
Email: info@vita.com 
URL: http://www.vita.com 
VITA Draft Standard for Trial Use 
VITA 46.7 
Ethernet on VPX Fabric Connector 
Abstract 
The objectives of this standard are to assign backplane Ethernet links to the VPX P1/J1 connector and to provide 
rules and recommendations for the use of Ethernet over backplane media. 
Draft Revision 0.09 
Publication Date: June 15, 2010 
 
Trial Use Motivation  
This trial use draft standard is being issued to allow designers to utilize VITA 46.7 while certain electrical 
requirements at the system level are more fully defined. These requirements have to do with apportionment of 
electrical budgets among the backplane channel, transmit (Tx) module, and receive (Rx) module. The VITA 68 
Channel Compliance working group is addressing many of these requirements. Designers are advised that the 
results of VITA 68 may alter the requirements in Section 5 of this standard. 
 
Trial Use Period 
Publication of this draft standard for trial use and comment has been approved by the VITA Standards 
Organization. Distribution of this draft standard for comment shall not continue beyond 18 months from the date 
of publication and may be withdrawn sooner at the discretion of the VITA 46.7 working group.  It is expected 
that following this trial use period, this draft standard, revised as necessary, will be submitted to the American 
National Standards Institute for approval as an American National Standard. Suggestions for revision should be 
directed to Scott Goedeke, Northrop Grumman, scott.goedeke@ngc.com with copy to John Rynearson, VITA, 
techdir@vita.com. 
 
 
 
 
Copyright 2010 by VITA, the VMEbus International Trade Association. All rights reserved. Permission of the 
publisher is required to reproduce this document or any part of it in any form. 
 
 
 
Copyright  2010 by VITA, the VMEbus International Trade Association.  All rights reserved.  Permission of the 
publisher is required to reproduce this document or any part of it in any form. 
 
 
 
 
 
 
VITA Draft Standard for Trial Use 
VITA 46.7, Rev 0.09 
 
Table of Contents 
Introduction........................................................................................................... 7	
  
1	
  
Ethernet Technology Overview ........................................................................... 7	
  
1.1	
  
1.2	
   Objective................................................................................................................ 8	
  
1.3	
  
Terminology ........................................................................................................ 10	
  
1.3.1	
   Specification Key Words .................................................................................... 10	
  
1.3.2	
   Glossary ............................................................................................................... 12	
  
References............................................................................................................ 17	
  
1.4	
  
2	
  
VITA 46.7 Compliance ....................................................................................... 18	
  
3U Plug-in module Minimum Requirements ................................................... 19	
  
2.1	
  
2.2	
  
6U Plug-in module Minimum Requirements ................................................... 19	
  
Backplane Minimum Requirements ................................................................. 19	
  
2.3	
  
Plug-in modules................................................................................................... 20	
  
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Backplane Requirements.................................................................................... 23	
  
Electrical .............................................................................................................. 26	
  
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Nomenclature ...................................................................................................... 27	
  
 
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VITA Draft Standard for Trial Use 
VITA 46.7, Rev 0.09 
 
Tables 
Table 1: Glossary .............................................................................................................. 12	
  
Table 2:  Plug-in module P1 Connector Pin Assignments................................................ 21	
  
Table 3:  Plug-in module P1 Connector Signal Definitions ............................................. 21	
  
Table 4:  P1 Connector Port/Link Assignments ............................................................... 22	
  
Table 5:  Backplane Slot J1 Connector Pin Assignments................................................. 24	
  
Table 6:  Backplane J1 Signal Definitions........................................................................ 25	
  
Table 7:  VITA 46.7 Port Capability Nomenclature......................................................... 27	
  
 
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Task Group 
At the time this standard was competed, task group membership included: 
 
VITA Draft Standard for Trial Use 
 
Name 
Grant Bechthold 
Lori Bechtold 
Steve Cecil 
James Demers 
David Dix 
Doug Endo 
Robert Evans 
Bob Ford 
Fred Fons 
Jim Goldenberg 
H. Scott Goedeke 
Claus Gross 
Val Georgiev 
Mike Gust 
Ian Hames 
Bill Hanna 
Rex Harvey 
Melissa Heckman 
Eric Hickey 
Richard Hodges 
Dean Holman 
Ben Jeffrey 
Pete Jha 
Steve Konsowski 
Andreas Lenkisch 
Paul Mesibov 
Michael Munroe 
Robert Normoyle 
Company 
Allen-Vanguard 
Boeing 
NSWC Crane 
Hypertronics 
Amphenol 
Raytheon 
Meritec 
Boeing 
Foxconn 
GE Fanuc 
Northrop Grumman 
PCI Systems 
 
Mercury 
CWCEC 
Boeing 
Parker 
Elma/Bustronic 
Amphenol 
Parker 
Mercury 
Molex 
CWCEC 
Northrop Grumman 
Pentair 
Pentek 
Bustronic Corp. 
DRS 
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VITA 46.7, Rev 0.09 
 
 
VITA Draft Standard for Trial Use 
 
 
Bob Patterson 
David Pepper 
Greg Powers 
Andy Reddig 
Greg Rocco 
Mac Rush 
John Rynearson 
Brian Sanderson 
Pat Shaw 
John Streyle 
Andrew Stringer 
Ivan Straznicky 
Bob Sullivan 
Bruce Thomas 
Kevin Thorson 
Serge Tissot 
Dan Toohey 
Keith Vieira 
Ben Winder 
Tyco 
GE Fanuc ES 
Tyco 
TekMicro 
Mercury 
Emerson 
VITA 
CWCEC 
GD-Canada 
GE Aviation 
Lockheed Martin 
CWCEC 
Hybricon 
CWCEC 
Lockheed Martin 
Kontron 
Mercury 
Carlo Gavazzi 
CWCEC 
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Comments, Corrections, or Additions 
Anyone wishing to provide comments, corrections, and/or additions to this proposed draft 
standard may direct their input toward the draft editor: 
 
H. Scott Goedeke  
Northrop Grumman Electronic Systems 
7323 Aviation Blvd. 
Baltimore, MD 21240 
USA 
PH: 1-410-993-7205 
EMAIL: scott.goedeke@ngc.com 
 
The best way to provide corrections and small additions is via marking up the specific 
pages and e-mailing them to the VITA 46.7 draft editor. For longer additions, the editor 
still prefers to receive textual information via e-mail. If mechanical drawings are 
involved, it is preferred that they be done with AutoCAD. This document is being 
prepared with Microsoft Word 2003 for Windows compatible computers. 
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VSO and Other Standards 
Information on other standards being developed by the VSO, VME Product Directories, 
VME Handbooks, and general information on the VME market is available from the 
VITA office at the address and telephone number listed on the front cover of this 
document. 
 
Change Bars 
Once released, change bars will be used in each revision to indicate modifications from 
the immediately previous revision. 
 
Draft Summary 
This is the preliminary draft of this standard. The original content of this draft standard 
was presented and agreed upon at the March 17th, 2010 VSO meeting.  See the draft 
history for a summary list of the major changes made to each draft. 
 
Draft History 
Draft No.  Date 
0.01 
0.02 
0.03 
0.04 
0.05 
0.06 
December 3, 2007 
January 25, 2008 
July 21, 2008 
August 19, 2008 
October 6, 2008 
March 5, 2009 
Comments & Major Changes/Updates 
Initial Draft 
Updated title page 
Updated references to IEEE 802.3-2008 
Updated Table of Contents, eliminated glyphs 
Changes resulting from WG ballot 
Added nomenclature paragraph; added KR; 
added ability to claim pin mapping 
compliance with Ethernet standards other 
than KX, KX4 and KR;  
Reversed all but editorial changes made in 
revision 0.06.  The 0.06 additions will be 
addressed by VITA 65. 
Add 10GBASE-BX4 as voted by the 
Working Group at the 11-19-2010 VSO 
meeting.  Add reference to VITA 68. 
Addressed ballot comments provided at 3-17-
2010 VSO meeting. 
0.07 
May 11, 2009 
0.08 
November 19, 2009 
0.09 
April 27, 2010 
 
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Introduction 
VITA 46.7, Rev 0.09 
 
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The embedded computing industry serves markets tending to need data plane 
interconnect technologies that push the state-of-the-art.  One method of achieving high 
performance is to implement switched serial fabric technologies.  VPX provides a means 
to implement switched serial technologies in a manner enabling implementers to tailor 
their architecture with the appropriate fabric for their application.  The benefits of 
switched serial interconnect technologies over parallel multi-drop buses include but are 
not limited to: 
•  Higher transaction bandwidth 
•  Higher aggregate bandwidth 
•  Lower link latency 
•  Less contention for the interconnect medium 
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•  Less routing real estate consumed 
 
Increased scalability 
The VPX base standard (VITA 46.0) defines physical features of VPX components. 
“Dot” standards further define additional sets of protocol layer standards that define 
specific serial or parallel interconnects used in a system implementation. 
 
VITA 46.7 defines the mapping of Ethernet signals to the VPX allocated fabric space 
mapped across the backplane on the P1/J1 connector for payload modules.   It does not 
address switch slot pin assignments.  Ethernet variants abound.  As defined by IEEE 
802.3, it includes many implementations differentiated in numerous ways, but primarily 
by media of transmission.  For the VPX switched serial fabric implementation, the media 
is a backplane.  Consequently, VITA 46.7 confines the specific Ethernet implementation 
to operation over electrical backplanes.  The first IEEE 802.3 definition of Ethernet over 
backplane media occurred in revision 802.3ap.  Subsequently, this revision has been 
included in IEEE 802.3-2008.  Prior to the release of revision 802.3ap, the only standard 
defining Ethernet over a backplane was the PICMG 3.1 specification “Ethernet/Fibre 
Channel for AdvancedTCA™ Systems” published by the Peripheral Component 
Interconnect (PCI) Industrial Computers Manufacturers Group (PICMG).  A considerable 
supply base exists supporting PICMG 3.1 in comparison to IEEE 802.3ap backplane 
Ethernet.  Therefore, to take advantage of this supply base, and to ease the transition to 
IEEE standard backplane Ethernet, VITA 46.7 also supports PICMG 3.1 
implementations.  These include PICMG 3.1 only as well as a mix of IEEE and PICMG 
compliant ports.  For mixed cases, VITA 46.7 provides guidance for interoperability. 
 
 
1.1  Ethernet Technology Overview 
The ubiquitous Ethernet computer networking protocol was invented in 1972 and 
standardized as IEEE 802.3 in 1982.  The original standard and subsequent updates 
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specified Ethernet protocol over cables up until the release of IEEE 802.3-2008 which 
defined Ethernet over a backplane.   
 
An Ethernet network may be constructed in several different ways within the confines of 
the IEEE 802.3 standard.  The choice of specific architectures is beyond the scope of this 
standard.   
 
The Ethernet Fat Pipe consists of four transmit and four receive serial differential signal 
pairs.  Each transmit and receive pair is also known as a logical lane.  Therefore, the Fat 
Pipe is a four lane (x4 logical lane) physical interface.  This is the configuration defined 
for 10GBASE-KX4 in IEEE 802.3-2008 Clause 71.  The same configuration is used for 
XAUI defined by Clause 47 and 10GBASE-BX4 defined by PICMG 3.1.  The PICMG 
specification borrows significant content from XAUI to define the electrical 
requirements. 
 
The most ubiquitous Ethernet version to date, 1000BASE-T, uses a Thin Pipe consisting 
of four bi-directional serial differential signal pairs instead of eight uni-directional pairs 
as in KX4 and BX4.   It encodes information using four level pulse-amplitude modulation 
(PAM5) instead of a binary bitstream.  1000BASE-T is defined by IEEE 802.3-2005 
Clause 40 and the 10 Gbps version, 10GBASE-T, is defined by IEEE 802.3an-2006 
Clause 55.  1000BASE-T and 10GBASE-T implementations are intended for cable 
media.  Although backplane channels could be designed to reliably carry them, there are 
no industry standards defining their use in backplanes.  Therefore, VITA 46.7 does not 
include 1000BASE-T or 10GBASE-T.   
 
Another type of Thin Pipe for Ethernet is reduced XAUI, known as RXAUI.  It was 
originated by Dune Networks, now part of Broadcom.  RXAUI consists of four uni-
directional serial differential signal pairs; two transmit and two receive.  It uses OIF CEI-
6G-SR which defines the interface as 6.25 Gbps over up to 20 cm of printed circuit board 
and one connector.  This is unsuitable for a VPX backplane which could be as long 50 cm 
and have two connectors.  Therefore, it was not included in VITA 46.7. 
 
The Ultra-thin Pipe consists of one transmit and one receive serial differential signal pair 
(1x logical lane) over printed circuit board.  This is the configuration defined for 
1000BASE-KX in IEEE 802.3-2008 Clause 70 and 1000BASE-BX in PICMG 3.1.   
 
Another type of Ultra Thin Pipe for Ethernet is 1000BASE-CX defined by IEEE 802.3-
2005 Clause 39.  However, it is defined for InfiniBand® twin-axial cable, not backplanes, 
so it is not suitable for VITA 46.7i. 
 
 
1.2  Objective 
The objectives of this standard are: 
 
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